KR20100019968A - Coating-developing apparatus, coating-developing method and storage medium - Google Patents

Abstract

PURPOSE: A coating-developing apparatus, a coating-developing method and a storage medium are provided to improve treatment quantity by rapidly sending back a substrate of a setting module after setting completion. CONSTITUTION: A recipe is selected(S1). A return schedule preparation part makes a return schedule of lot(S2). A controller practices processing toward the wafer of lot (S3). A temperature setting processing of the heat module is initiated(S4). The optimal time of the main arm is calculated(S5). According to the comparison result of the running time and optimal time, the following cycle 23 is processed(S6). The calculation about the optimal time is operated(S7). The atmosphere control of the main arm is determined through the comparison of the running time of the optimal time and executes cycle 23(S8). The optimal time of the main arm about each heat module is calculated(S9). The cycle 25 is processed after the waiting time of the main arm(S10).

Description

Coating, developing apparatus, method and storage medium {COATING-DEVELOPING APPARATUS, COATING-DEVELOPING METHOD AND STORAGE MEDIUM}

The present invention is, for example, a coating, a developing apparatus, a method and a coating, and a developing method of applying a resist liquid to a substrate such as a semiconductor wafer or an LCD substrate (glass substrate for liquid crystal display), developing processing after exposure, and the like. A storage medium having stored thereon a program for executing the same.

In the manufacturing process of a semiconductor device and an LCD substrate, formation of a resist pattern is performed with respect to a board | substrate by the technique called photolithography. In this technique, for example, a resist liquid is applied to a substrate such as a semiconductor wafer (hereinafter referred to as a wafer) to form a liquid film on the surface of the wafer, and the photoresist is used to expose the resist film, followed by development. It is carried out by a series of processes to obtain a desired pattern by performing.

Such a process is generally performed using the resist pattern forming apparatus which connected the exposure apparatus to the application | coating which develops application | coating or image development of a resist liquid, and a developing apparatus. In this apparatus, for example, as shown in FIG. 7, the carrier 10 containing a plurality of wafers is carried into the carrier stage 11 of the carrier stacking portion 1A, and the wafers in the carrier 10. Is transmitted to the processing unit 1B by the delivery arm 12. After the formation of the anti-reflection film in the anti-reflection film formation module (not shown) or the formation of the resist film in the application module 13 is performed in the processing portion 1B, the exposure apparatus is provided via the interface portion 1C. It is conveyed to (1D). On the other hand, the wafer after the exposure process is returned to the processing unit 1B again, and the developing module 14 performs the developing process, after which the wafer is returned to the original carrier 10. Before or after the formation process of the anti-reflection film or the resist film or before and after the development process, the wafer heat treatment or the cooling process is performed, and the heating module which performs these heat treatments, the cooling module which performs the cooling treatment, and the like are the shelf modules 15 (15a to 15). It is arranged in multiple stages at 15c, and the wafer is conveyed between each module by the main arm 16 (16A, 16B) provided in the process part 1B. Here, in carrying out the above-described processing, as described in Patent Document 1, the wafers are conveyed in accordance with a transfer schedule in which each module is transferred to which module at which timing in advance.

By the way, in the apparatus described above, the wafer A of the selection lot A and the wafer B of the subsequent lot B, which are sets of a plurality of wafers of the same kind, discharged from one carrier, have a carrier stacking portion 1A. ) Is continuously discharged to the processing unit 1B to perform the treatment, and the same heating module is used between the lot A and the lot B. The heating temperature may change.

In this case, conventionally, the temperature setting time (time required for temperature change) in the heating module is predicted to control the timing of dispensing from the carrier stacking portion 1A in the late stage lot B. Is done. This timer control will be described taking the transfer schedule shown in FIG. 8 as an example. The vertical axis of the conveyance schedule represents a cycle, and the horizontal axis represents a module to be conveyed, respectively. In addition, it is assumed that FOUP is a carrier, M1 to M5 are modules, and in this example, temperature setting processing is performed in module M4.

And the control time T1 of the said dispensing timing is calculated | required by following formula (1).

[Equation 1]

T1 = P + Q-R

P: time until the wafer of the selection lot A is taken out from the module M4

Q: Temperature regulation time

R: time until the wafer of the late lot (B) is carried into the said module M4

Where P is [process remaining time in module M1] + [travel time to module M2 + process time in module M2] + [travel time to module M3 + module M3] Process time at] + [movement time to module M4 + process time at module M4], for example, 15 seconds.

Further, R denotes [travel time to module M1 + process time at module M1] + [travel time to module M2 + process time at module M2] + [module M3] Travel time to + process time in module M3], for example, 20 seconds.

When the temperature control time Q is 30 seconds, the control time T1 is thereby set to P + Q-R = (15 + 30)-(20) = 25 seconds, and the late stage lot B by this 25 seconds. It is delaying the release of the first wafer. However, the main arm 16 adjusts the cycle time to the slowest process time (the time that adds the transfer time of the wafer to the module M4 and the time required for processing) according to the transfer schedule. Although it is controlled to perform one conveyance cycle by time, in practice, since the number of wafers carrying moving stacks by the main arm differs depending on the cycle, the cycle may be executed for a shorter or longer time than this cycle time. After the wafer has finished the process in the module M4, the carrying out of the module M4 by the main arm 16 is not immediately performed, but is received by the main arm 16 in the module M4. There is a case where a state of waiting for an error occurs. Since the waiting time is not included in the above-described calculation formula, even if the timer control as described above is performed, the wafer B of the late lot B arrives quickly in the module M4, or the arrival of the timer is not performed. There is a case of delay.

In this manner, when the time at which the wafer B of the late stage lot B arrives at the module M4 is earlier, the temperature setting process is not completed at the module M4, and thus the wafer B is transferred to the module. Inevitably, since the main arm 16 has to wait in the state of holding the wafer, there is a possibility that the transfer cycle cannot be performed and the situation may stop. On the other hand, if the time of arrival to the said module M4 is delayed, although the temperature setting process is already complete | finished in the said module M4 already, the process of carrying out the wafer W is carried out by the module ( A state in which the M4) side waits occurs, and a conveyance interval with the wafer A of the selection lot A occurs more than necessary, and a supply delay of the wafer B of the late development lot B to the exposure apparatus occurs. There is a risk of causing a decrease in productivity. Therefore, when the wafer B of the late lot B arrives early in the said module M4, or arrival is delayed, the throughput will fall.

However, in Patent Document 2, the substrate is conveyed in the order of the first temperature control module, the first coating module, the first heating module, the second temperature control module, the second coating module, the second heating module, and the cooling module. In the apparatus provided with the evacuation module capable of evacuating the substrate, after the last substrate of the selection lot has finished the heat treatment in the second heating module, the heating temperature of the second heating module is adjusted to the temperature according to the substrate of the later development lot. In the step of changing to, the substrate heated by the first heating module leading to the first substrate is transferred to the evacuation module from the next conveyance cycle of the conveyance cycle in which the substrate at the head of the late stage lot is conveyed to the second temperature control module. After changing the heating temperature of the said 2nd heating module so that it may fill sequentially, the structure which conveys the board | substrate in the said evacuation module to the downstream module sequentially is proposed. There is. However, in this configuration, since the substrate is held in the evacuation module, it may take a long time until all the processes are completed for the wafer, and the problem of the present invention cannot be solved.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2004-193597

[Patent Document 2] Japanese Patent Application Laid-Open No. 2008-34746

This invention is made | formed under such a situation, The objective is to provide the technique which can aim at the improvement of a throughput, when setting processing is performed in a module to be set between a starting lot and a later lot.

For this reason, the application | coating and developing apparatus of this invention load the carrier which accommodated the several board | substrate, and the carrier loading part provided with the transmission means which transfers a board | substrate between carriers, and the board | substrate delivered from this carrier mounting part. Forming a coating film on the substrate, and having a processing unit for developing the substrate after exposure;

In the processing unit, the substrate conveying means conveys the substrate to a temperature control module for controlling the temperature of the substrate, a coating module for applying the substrate to the coating liquid, a heating module for heating the substrate, and a developing module for developing the substrate. ,

When the place where the said board | substrate is put is called a module, based on the conveyance schedule set previously, the board | substrate conveying means forms the state in which the board | substrate with smaller order is located in the module of a downstream side rather than the board | substrate with larger order, thereby In the application | coating and the image development apparatus by which conveyance of a board | substrate is performed by executing one conveyance cycle and completing the said conveyance cycle, and then carrying out the following conveyance cycle,

After completion | finish of a process by the said module about the board | substrate of the selection lot discharged from one carrier and consisting of at least one of the said application module and a heating module, before the board | substrate of a later lot is conveyed to the said module, A setting target module in which the setting processing is performed;

In the transfer schedule, after carrying out the last substrate of the selection lot to the processing unit, and executing one transfer cycle for the time required for the setting process until the first substrate of the late lot is transferred to the processing unit. Means for creating a return schedule to empty the cycle by the number of delay cycles obtained by dividing by the cycle time, which is the maximum time required;

In the created return schedule, the setting target module is finished before the execution cycle that is the cycle in which the setting processing is performed in the setting target module and in which the remaining time of the setting processing is performed in the setting target module is completed and the next cycle is started. Each time, a proper time for executing the next cycle is obtained, and the longest of these is compared with the execution time for executing the execution cycle, and when the titration time is long, the difference between the titration time and the execution time is determined. And means for controlling the substrate conveying means to wait for the start of the next cycle of the execution cycle for a corresponding time period.

At this time, the appropriate time is {(setting processing remaining time in the setting target module) + (the running time of the execution cycle)-(in the cycle in which the substrate of the late stage lot is loaded into the setting target module, Time required for the transfer means to transfer the substrate)} ÷ (the number of cycles from the execution cycle to the cycle in which the wafer of the subsequent lot is loaded into the module to be set). In addition, the start of the next cycle means that the substrate transfer means receives the substrate transferred from the carrier mounting portion to the processing portion. For example, the setting target module is a heating module, and the setting processing is a changing processing of the heating temperature.

Moreover, the application | coating and developing method of this invention load the carrier which accommodated several board | substrate, The carrier loading part provided with the conveyance means which performs the transfer of a board | substrate between carriers, and the board | substrate delivered from this carrier loading part. Forming a coating film on the substrate, and having a processing unit for developing the substrate after exposure;

The said processing part conveys a board | substrate with respect to the temperature control module which temperature-controls a board | substrate by a board | substrate conveyance means, the coating module which apply | coats a coating liquid to a board | substrate, the heating module which heats a board | substrate, and the developing module which performs a development process with respect to a board | substrate,

When the place where the said board | substrate is put is called a module, based on the conveyance schedule set previously, the board | substrate conveying means forms the state in which the board | substrate with smaller order is located in the module of a downstream side rather than the board | substrate with larger order, thereby In the application | coating and image development method by which conveyance of a board | substrate is performed by executing one conveyance cycle and completing the said conveyance cycle, and then carrying out the following conveyance cycle,

In the said module, it consists of at least one of the said application | coating module and a heating module, and after completion | finishes a process by the said module about the board | substrate of the selection lot discharged | emitted from one carrier, before the board | substrate of a later lot is conveyed to the said module, And a setting object module to which setting processing is performed,

In the transfer schedule, after the last substrate of the starting lot is transferred to the processing unit, one transfer cycle is executed for the time required for the setting process until the first substrate of the late lot is transferred to the processing unit. A process of creating a return schedule to empty the cycle by the number of delay cycles obtained by dividing the cycle time, which is the maximum time required at the time;

In the created return schedule, before the end of the execution cycle, which is a cycle in which the setting processing is performed in the setting target module and a cycle in which the remaining time of the setting processing is performed in the setting target module, and before the next cycle, the setting target is set. For each module, an appropriate time for executing the next cycle is obtained, and if the proper time is long by comparing the longest proper time among these and the execution time for executing the execution cycle, the difference between the appropriate time and the execution time And a step of controlling the substrate conveying means to wait for the start of the next cycle of the execution cycle for a time corresponding to.

At this time, the appropriate time is {(setting processing remaining time in the setting target module) + (the running time of the execution cycle)-(in the cycle in which the substrate of the late stage lot is loaded into the setting target module, Time required for the transfer means to transfer the substrate)} ÷ (the number of cycles from the execution cycle to the cycle in which the wafer of the subsequent lot is loaded into the module to be set).

In addition, the storage medium of the present invention is used in a coating and developing apparatus in which a processing unit forms a coating film on a substrate received from a carrier stacking unit on which a carrier containing a plurality of substrates is loaded, and at the same time, develops a substrate after exposure. It is a storage medium storing a computer program to be stored, wherein the program is characterized in that a step group is woven to execute the application and development methods.

As mentioned above, in this invention, when processing the board | substrate of a starting lot and the board | substrate of a late lot in the same setting target module, after processing with respect to the board | substrate of these starting lot, after performing a process with respect to the board | substrate of a late lot. When setting processing is performed in the said setting object module before, after completion | finish of the setting process of the said module, the throughput of a late lottery lot can be conveyed to the said setting object module quickly, and the improvement of a throughput can be aimed at.

First, the resist pattern forming apparatus 2 which connected the exposure apparatus to the application | coating and developing apparatus of this invention is demonstrated, referring drawings. 1 shows a plan view of an embodiment of the device, and FIG. 2 is a schematic perspective view. In the figure, reference numeral B1 denotes a carrier stacking section for carrying in and out of a substrate C, for example, a wafer C, for example, 13 sheets hermetically stored. The plurality of stacking sections 21 of the carrier C are arranged. The carrier station 22 which can be loaded, the opening-and-closing unit 23 provided on the front wall surface when viewed from the carrier station 22, and the processing unit B2 to take out the wafer W from the carrier C, which will be described later. A delivery means 24 is provided for delivery to).

A processing unit B2 surrounded by a housing 25 is connected to the inner side of the carrier stacking unit B1, and the shelf module in which the modules of the heating / cooling system are multiplexed in sequence from the front side is connected to the processing unit B2. (A1, U2, U3) and the main arm [A] which comprises the board | substrate conveying means which delivers the wafer W between these shelf modules U1-U3 and each module of the liquid processing modules U4, U5 mentioned later. (A1, A2)] are alternately arranged. That is, the shelf modules U1, U2 and U3 and the main arms A1 and A2 are arranged in a line in front and rear when viewed from the carrier loading part B1 side, and each connection portion has an opening for wafer conveyance not shown. The wafer W can move freely from the inside of the processing unit B2 to the shelf module U3 on one end side to the shelf module U3 on the other end side.

The shelf modules U1, U2, and U3 have a configuration in which various modules for performing pre- and post-processing of the processing performed in the liquid processing modules U4 and U5 are stacked in multiple stages, for example, ten stages. The combination is a transfer module TRS, a temperature control module CPL for adjusting the wafer W to a predetermined temperature, a heating module CLH for heat treatment of the wafer W, and a coating of the resist liquid. A heating module CPH for later heating the wafer W, a heating module PEB for heating the wafer W before the developing treatment, and a heating module POST for heating the wafer W after the developing treatment. ), Etc. are included.

The liquid processing modules U4 and U5 are, for example, resists on the antireflection film forming module BCT and the wafer W that apply the antireflection film forming chemical to the wafer W, as shown in FIG. 2. The coating module COT for applying the liquid, the developing module DEV for supplying the developing solution to the wafer W, and the developing module DEV for developing are stacked in multiple stages, for example, five stages.

The exposure part B4 is connected to the inner side of the shelf module U3 in the said processing part B2 through the interface part B3. This interface part B3 is comprised by the 1st conveyance chamber 31 and the 2nd conveyance chamber 32 which are provided back and forth between the process part B2 and the exposure part B4, and can raise and lower in each, and the vertical axis periphery. It is provided with the 1st conveyance arm 33 and the 2nd conveyance arm 34 which can be rotated and retracted. In addition, the shelf module U6 provided with the transfer module etc. laminated | stacked up and down is provided in the 1st conveyance chamber 31, for example.

As said heating module CPH, for example, it is equipped with the heating plate for loading and heating the wafer W on it, and the cooling plate which also serves as a conveyance arm, The wafer between the main arm A and the heating plate ( The apparatus of the structure which performs delivery of W) by a cooling plate, ie, can perform heat cooling by one module, is used.

The main arm A will be described. This main arm A is a module (where the wafer W is placed) in the processing unit B2, for example, each processing module of the shelf modules U1 to U3 and each of the liquid processing modules U4 and U5. It is configured to transfer wafers between modules. As a result, the holding arms are configured to be able to move back and forth, and to be rotatable around the vertical axis, and to support the back peripheral region on the back side of the wafer W, and the support arms move forward and back independently of each other. It is configured to do so.

An example of the flow of the wafer W in such a resist pattern formation system is demonstrated with reference to FIG. 3, The wafer W in the carrier C mounted in the carrier mounting part B1 is the process part B2. Is transferred to the transfer module (TRSA) of the shelf unit (U1), from which the temperature control module (CPL) → antireflection film forming module (BCT) → heating module (CLH) → temperature control module (CPL) → coating module (COT) ) Is transferred to the path of the transfer module TRS → the heating module CPH → the interface unit B3 → the exposure unit B4, and the exposure process is performed here. On the other hand, the wafer W after the exposure treatment is returned to the processing unit B2, and the heating module PEB → the temperature control module CPL → the developing module DEV → the heating module POST and the temperature control module CPL are turned on. It conveys by the path | route of the delivery module TRSA of the unit U1, and returns to the carrier C of the carrier mounting part B1 from here.

At this time, in the processing unit B2, the main arms A (A1, A2) receive the wafer from the transfer module TRSA of the shelf unit U1, and transfer the wafer through the temperature control module CPL. After conveying to the heating module CPH sequentially along the conveyance path mentioned above, the wafer W after exposure processing is received from the interface part B3, and the said conveyance is conveyed through the heating module PEB etc. via the heating module PEB. It is comprised so that it may convey to the delivery module TRSA sequentially along a path | route, and performs a conveyance cycle in the process part B2 in this way. In this conveyance cycle, conveyance from the delivery module TRSA to the temperature control module CPL is the first conveyance by the main arm A, as shown in FIG. 3, in which case the conveyance module TRSA conveys. It becomes the start module of the cycle. Since the wafer W is transferred from the carrier mounting portion B1 to the transfer module TRSA, the transfer of the wafer W to the transfer module TRSA transfers the wafer W to the processing unit B2. By receiving the main arm A from the delivery module TRSA, the conveyance cycle is started.

And the resist pattern forming apparatus mentioned above manages the recipe of each process module, the recipe of the conveyance flow (transfer path) of the wafer W, the process in each process module, the transfer means 24, the main The control part 4 which consists of a computer which performs drive control of arm A1, A2, etc. is provided. This control part 4 has a program storage part which consists of a computer program, for example, each program operation part for forming the predetermined | prescribed resist pattern with respect to the operation | movement of the whole resist pattern forming apparatus, ie, the wafer W, A program, for example, made of software is provided that includes a step (command) group so that the process in the processing module, the conveyance of the wafer W, and the like are performed. And by reading these programs by the control part 4, the control part 4 controls the operation | movement of the whole resist pattern forming apparatus. The program is stored in the program storage unit in a state of being stored in a storage medium such as a flexible disk, a hard disk, a compact disk, a magnet optical disk, a memory card, or the like.

FIG. 4 shows the configuration of the control unit 4, which is actually constituted by a CPU (central processing module), a program, a memory, and the like. However, in the present invention, the wafer W before development processing is characterized by the present invention. Some of the related components will be described in a block. In FIG. 4, the code | symbol 40 is a bus, The recipe storage part 41, the recipe selection part 42, the setting processing part 43, the conveyance schedule preparation part 44, the wait control part 45, and conveyance to this bus 40 are carried out. The control part 46 is connected.

The recipe storage section 41 is a portion corresponding to the storage section. For example, a plurality of recipes in which a conveyance recipe in which the conveyance path of the wafer W is recorded and processing conditions performed on the wafer W are recorded. It is stored. The recipe selection section 42 is a site for selecting a suitable one from the recipe stored in the recipe storage section 41. For example, the recipe selection section 42 is capable of inputting the number of wafers processed, the type of resist, the temperature during heat treatment, and the like.

The setting processing unit 43 finishes a predetermined process in the module to be set by the wafer A of one lot (hereinafter referred to as "lot A"), which is a set of a plurality of substrates of the same type drawn out from one carrier. After that, it is a means for outputting a command to effect setting processing on the module. The setting process means a process for adjusting the state of the module, such as a temperature change process or an adjustment process such as a dummy-dispensing process in the coating module COT. In this example, the module to be set is a heating module (CPH), and the setting processing in this module means that the heating temperature is transferred to the wafer B of another lot (hereinafter referred to as "lot B"). Process to change the temperature accordingly. Therefore, the command which changes the temperature of a heating plate is output to the heating module CPH after the heat processing in the said heating module CPH of the wafer A of the lot A is complete | finished.

Based on the conveying recipe, the conveyance schedule preparing unit 44 assigns a sequence of contents such as which module to convey at which timing to all the wafers in the lot, for example, an order to the wafers, and thus the order and angle of the wafers. It is a means for creating a conveyance schedule created by arranging the conveyance cycle data in which the modules correspond to the conveyance cycles in time series. At this time, the said transfer schedule preparation part 44 transfers the last wafer A of the selection lot A to the said processing part B2, and then transfers the first wafer B of the said latent lot B to the said processing part ( Until the transfer to B2), the transfer schedule is created so that the cycle is emptied by the number of delay cycles obtained by dividing the time required for the setting process by the cycle time, which is the maximum time required to execute one transfer cycle.

In the transfer schedule, the waiting control section 45 finds an appropriate time for executing the next cycle for each module to be set, and ends the predetermined execution cycle and starts the next cycle. And the execution time of the execution cycle, when the proper time is long, the main arm A is controlled to wait for a time corresponding to the difference between the proper time and the execution time and the start of the next cycle of the execution cycle. Means.

The transfer control section 46 controls the transfer means 24 or the main arms A1 and A2 so as to transfer the wafer written in the transfer cycle data to the module corresponding to the wafer with reference to the transfer schedule. Means for executing a conveyance cycle.

Subsequently, the operation of the present embodiment will be described with reference to FIGS. 5 and 6. First, the operator selects a recipe prior to starting the processing for the wafer W as a substrate, but as described above, an antireflection film is formed as a coating film and a resist film is formed thereon as an example. Listen and explain. In the present invention, the transfer path of the wafer W to the module to be set is characterized by the above. Therefore, the temperature setting process is performed on the heating module CPH after the resist film is formed to the heating module CPH as an example. Focusing on the conveyance path of will be described.

First, as shown in FIG. 5, the operator has an anti-reflection film for the five wafers A01 to A05 of the lot A, and the five wafers B01 to B05 of the subsequent lot B. The recipe in the case of forming the coating film provided with a resist film is selected (step S1). Subsequently, the conveyance schedule preparation unit 44 creates a conveyance schedule of the lot A and the lot B based on the selected recipe (step S2).

At this time, a transfer schedule is created between the lot A and the lot B so as to delay the dispensing of the wafer from the carrier stacking portion B1 to the transfer module TRSA by the number of delay cycles obtained by the following equation (2). .

[Equation 2]

Number of delay cycles = setting processing time ÷ cycle time

The setting processing time is a time required for the setting processing, and in this example, the time required for the temperature setting processing of the heating module CPH is referred to, for example, 90 seconds. In addition, a cycle time means the maximum time required in order to perform one conveyance cycle of a conveyance schedule, and is 22.8 second in this example. Therefore, the number of delay cycles = 90 seconds ÷ 22.8 seconds = 3.95, rounded to four.

Here, among the modules in the processing unit B2, the slowest process time (the time in which the transfer time of the wafer to the module plus the time required for the processing) becomes the rate speed time in the transfer cycle. Rate rate is the cycle time.

An example of the said conveyance schedule is shown in FIG. In this figure, the vertical axis is a cycle, and each module is described in the order along the conveyance path of the wafer W on the horizontal axis. In the different types of modules, the module on the left side in FIG. 6 is a module upstream of the conveyance path. As it goes to the right side, it becomes a module downstream of a conveyance path | route. In addition, BCT1 and BCT2 mean using two antireflection film formation modules, and CPH1 to CPH5 mean using five heating modules in a conveyance schedule.

The main arm A is provided with two or more holding arms, and is sequentially moved from the wafer in the downstream module to the module one after the other in order, so that the wafer having the smaller order is downstream than the wafer having the larger order. By forming a state located in the module of, by executing one cycle (conveying cycle), and ending the cycle, the process proceeds to the next cycle, and executes each cycle sequentially, in order by the above-described path. The wafers are sequentially transported to perform a predetermined process.

In this transfer schedule, the first wafer A01 of the lot A is loaded into the anti-reflection film forming module BCT1 in cycle 3, and the wafer A01 is also in the anti-reflection film forming module BCT1 even in cycle 4. The process is performed. In Cycle 5, the wafer A01 is taken out from the antireflection film forming module BCT1 by one holding arm of the main arm A, and is held on the other holding arm of the main arm A. FIG. The wafer A03 is carried in to the anti-reflection film forming module BCT1, and the wafer A01 held on one of the holding arms is then placed on one downstream side of the anti-reflection film forming module BCT2. It is made to carry in into phosphorus heating module CLH1.

Returning the description to the number of delay cycles, as described above, the number of delay cycles is 4, so that the transfer schedule is created so as to delay delivery of the wafer from the carrier stacking portion B1 to the transfer module TRSA by the number of delay cycles. do. That is, the first wafer B01 of the lot B is transferred to the transfer module TRSA after the last wafer A05 of the lot A is transferred to the transfer module TRSA, and then empty the number of cycles 4 as empty cycles. The return schedule is created to be delivered to. That is, the last wafer A05 of the lot A is transferred to the transfer module TRSA in cycle 5, then emptied as empty cycles by 4 cycles, after which the first wafer B01 of the lot B is In cycle 10 it is delivered to the delivery module TRSA.

Subsequently, the control unit 4 outputs an instruction to each unit while referring to the created transfer schedule, executes the process for the wafer A of the lot A (step S3), and executes up to cycle 22 according to the transfer schedule as it is. do. At this time, the temperature setting process of the heating module CPH1 is started in cycle 22 (step S4). In addition, the oblique part in the conveyance schedule of FIG. 6 means that the temperature setting process is performed.

Subsequently, at the end of the execution cycle in which the standby control unit 45 satisfies all of the following conditions (1) and (2), whether or not to perform standby control of the main arm A before the next cycle is started. Judge. Here, before the next cycle is started, the main arm A is returned to the position facing the transfer module TRSA, which is the start module of the transfer cycle, from which the next cycle is about to start. In addition, the atmospheric control of the main arm A means controlling the receipt of the wafer from the transfer module TRSA by the main arm A to wait for a predetermined time.

Condition (1) There is a past situation that setting processing is performed in a certain module to be set.

Condition (2) Remaining time of setting processing exists

Here, when the condition (1) is described, the fact that the setting process has been performed in a certain setting target module means that the setting processing has been performed in the setting target module. In this example, in the heating module CPH1, Since the temperature setting process which is a setting process is started in cycle 22, when the cycle 22 is complete | finished, there exists a past situation that the setting process was performed in the said heating module CPH1. Therefore, in the conveyance schedule shown in the figure, the end of the cycle that satisfies the condition (1) is the end of the cycle 22 to the cycle 29.

In addition, about condition (2), in this example, since the temperature setting which is a setting process in cycle 25 is complete | finished in heating module CPH1, cycle 22-cycle 24 turn into a cycle in which the remaining time of a setting process exists. Therefore, in the conveyance schedule shown in the figure, the end of the cycle that satisfies the condition (1) is the end of the cycle 22 to the cycle 28.

As described above, in the transfer schedule, the end time of the execution cycle that satisfies the above conditions (1) and (2) is the end time of the execution cycles 22 to 28, and these execution cycles 22 to 28 In the following, the proper time T2 of the main arm A is calculated before starting the next cycles 23 to 29, and it is determined whether or not the standby control of the main arm A is to be performed based on the calculation result. Here, the appropriate time T2 is an ideal time for the main arm A to execute the next cycle of the execution cycle, and is calculated based on the following expression (3).

[Equation 3]

Proper time (T2) = (I + II-III) ÷ IV

I: setting processing remaining time in the module to be set

II: execution time of the execution cycle

III: Movement loading time of the main arm A in the cycle in which the wafer B of the subsequent lot B is loaded into the module to be set.

IV: number of cycles from execution cycle until wafer B of subsequent lot B is loaded into the module to be set

Specifically, calculation of the proper time T2 of the main arm A when cycle 22 ends and cycle 23 is about to start will be described. In this case, the execution cycle is cycle 22, the module to be set is the heating module CPH1, and I to IV are as follows. The execution time II of the execution cycle is a time required when the execution cycle is actually executed, and the execution time is changed because the control for carrying back at regular intervals is not performed.

I: 73 seconds

II: Execution time of execution cycle 22 is 26 seconds

III: The cycle in which the wafer B01 is loaded into the heating module CPH1 is cycle 26, and the wafers W moved and stacked in this cycle 26 are B05, B02 and B01, and the transfer loading time is 9.5 seconds.

IV: The number of cycles from execution cycle 22 to cycle 26 where the wafer B01 is loaded into the heating module CPH1 is from (26 to 22) to 4

Thereby, the said titration time T2 is computed from Formula 3 by T2 = (73 + 26-9.5) /4=22.375 second → 22.4 second (step S5).

Then, whether or not the standby control of the main arm A is to be performed is compared with the appropriate time T2 and the execution time (26 seconds) of the execution cycle 22. When the proper time T2 is longer, the main arm is longer. It is judged that the standby control of (A) is executed, and if not, the standby control is not executed. In this example, since it is the appropriate time T2 <execution time, it is determined that the standby control is not executed, and the following cycle 23 is executed without performing the standby control of the main arm A (step S6).

Subsequently, cycle 23 ends and standby control of the main arm when cycle 24 is about to start is demonstrated. In this case, the execution cycle is cycle 23, and the module to be set is the heating module CPH1 and the heating module CPH2, which are calculated for the appropriate time T2 in each case (step S7). It is determined whether or not the standby control of the main arm is to be performed by comparing the longer appropriate time T2 with the execution time of the execution cycle 23 (step S8).

First, about heating module CPH1, I thru | or IV are as follows.

I: 53 seconds

II: The execution time of execution cycle 23 is 20 seconds

III: Since the wafer B01 is loaded into the heating module CPH1 in cycle 26, the moving loading time is 9.5 seconds as described above.

IV: The number of cycles from execution cycle 23 to cycle 26 where the wafer B01 is loaded into the heating module CPH1 is from (26 to 23) to 3

As a result, the appropriate time T2 is calculated from the equation 3 from T2 = (53 + 20-9.5) ÷ 3 = 21.167 seconds → 21.2 seconds.

Similarly, about heating module CPH2, I thru | or IV are as follows.

I: 77 seconds

II: The execution time of execution cycle 23 is 20 seconds

III: The wafer B02 is loaded into the heating module CPH2 in cycle 27, and the wafers W moved and stacked in this cycle 27 are B02 and B03, and the transfer loading time is 6 seconds.

IV: The number of cycles from execution cycle 23 to cycle 27 in which the wafer B02 is loaded into the heating module CPH2 is from (27 to 23) to 4

Thereby, the titration time T2 is calculated from equation 3 as T2 = (77 + 20-6) ÷ 4 = seconds → 22.75 seconds → 22.8 seconds.

Thus, since the titration time T2 in the heating module CPH1 is 21.2 sec, and the titration time T2 in the heating module CPH2 is 22.8 sec, the longer titration time T2 (22.8 sec) and Compare the execution time (20 seconds) of execution cycle 23. In this case, since the appropriate time T2> execution time, the waiting time T3 of the main arm is determined by the appropriate time T2-execution time. In this case, waiting time T3 is calculated | required as 22.8 second-20 second = 2.8 second, For example, it rounds up and performs waiting control of the main arm A for 3 second. That is, in this example, when execution cycle 23 is finished and the next cycle 24 is to be started, the main arm A corresponds to the waiting time at the position facing the delivery module TRSA which is the start point of the cycle. After atmospheric adjustment by a timer (3 seconds), the wafer B05 is received from the heating module CLH4, and cycle 24 is started in this way (step S8).

In addition, the standby control of the main arm A when cycle 24 is complete | finished and cycle 25 is about to start is demonstrated. In this case, the module to be set is the heating module CPH1, the heating module CPH2, and the heating module CPH3, and the execution cycle is cycle 24.

First, about heating module CPH1, I thru | or IV are as follows.

I: 33 seconds

II: The execution time of execution cycle 24 is 20 seconds

III: The wafer B01 is loaded into the heating module CPH1 in cycle 26, and the moving stacking time in this cycle 26 is 9.5 seconds as described above.

IV: The number of cycles from execution cycle 24 to cycle 26 where the wafer B01 is loaded into the heating module CPH1 is from (26 to 24) to 2

Thereby, the titration time T2 is calculated | required from Formula 3 by T2 = (33 + 20-9.5) /2=21.75 second-> 21.8 second.

Subsequently, about heating module CPH2, I thru | or IV are as follows.

I: 57 seconds

II: The execution time of execution cycle 24 is 20 seconds

III: The wafer B02 is loaded into the heating module CPH2 in cycle 27, and the moving stacking time in this cycle 27 is 6 seconds as described above.

IV: The number of cycles from execution cycle 24 to cycle 27 where the wafer B02 is loaded into the heating module CPH2 from (27 to 24) to 3

Thereby, appropriate time T2 is calculated | required from Formula 3 to T2 = (57 + 20-6) / 3 <= 23.67 second-> 23.7 second.

Lastly, for the heating module CPH3, I to IV are as follows.

I: 76 seconds

II: The execution time of execution cycle 24 is 20 seconds

III: The wafer B03 is loaded into the heating module CPH3 in cycle 28, and the wafers W moved and stacked in this cycle 28 are B04 and B03, and the transfer loading time is 6 seconds.

IV: The number of cycles from execution cycle 24 to cycle 28 where the wafer B03 is loaded into the heating module CPH3 is from (28 to 24) to 4

Thereby, appropriate time T2 is calculated | required from Formula 3 as T2 = (76 + 20-6) / 4 <22.5 second.

Thus, the titration time T2 in the heating module CPH1 is 21.8 sec, the titration time T2 in the heating module CPH2 is 23.7 sec, and the titration time T2 in the heating module CPH3 is Since it is 22.5 seconds (step S9), the longest appropriate time T2 (23.7 second) is compared with the execution time of execution cycle 24 (20 second). In this case, since the appropriate time T2> execution time, the waiting time T3 (3.7 seconds → 4 seconds rounded) of the main arm A is determined by the appropriate time T2-execution time, and the main arm A ), The next cycle 25 is started (step S10).

As described above, the cycle 22 to cycle 28 are used as execution cycles, and these execution cycles are terminated, and the appropriate time for executing the next cycle for each module to be set is determined before starting the next cycle. When the titration time is long by comparing the titration time with the execution time of the execution cycle, the control of the main arm A to wait for a time corresponding to the difference between the titration time and the execution time and the start of the next cycle of the execution cycle. The remaining cycles are executed in accordance with the above-described return schedule.

In such a resist pattern forming apparatus, it is a case where the processing unit B2 continuously processes the wafer A of the selected lot A and the wafer B of the subsequent lot B, and the lot A Transfer timing of the wafer B to the module, even if the setting processing in the module to be set is performed between the process for the wafer A of the wafer A and the process for the wafer B of the lot B. It is possible to suppress the occurrence of this faster or slower situation.

In other words, at the time of preparing the transfer schedule, the cycle was emptied by the time required for the setting process, and the wafer W was discharged from the carrier stacking unit B1 to the processing unit B2. The conveyance timing of B) is accelerated, and generation | occurrence | production of the situation which conveys the wafer B to the said module before the said setting process is complete | finished can be suppressed.

In this way, since the wafer B is prevented from being transferred to the module before the setting processing is completed, the wafer B cannot be delivered to the module, and the main arm A holds the wafer B. Occurrence of the situation where the vehicle is stopped in the state where the transfer cycle cannot be performed can be prevented. Thereby, since a conveyance schedule can be performed sequentially in a stable state, without the main arm A stopping, the conveyance of a wafer can be performed smoothly and the throughput can be improved.

Further, in a cycle that satisfies a predetermined condition, an appropriate time T2 when the next cycle is executed is obtained. When this time is longer than the execution time of the execution cycle, it corresponds to the appropriate time T2-execution time. By controlling the timer of the main arm A so as to wait for receipt of the wafer W from the start module of the transfer cycle, it is suppressed that the transfer timing of the wafer B to the module is delayed. Immediately after the setting processing is completed, the wafer B01 can be brought into the setting target module. For this reason, it is suppressed that the conveyance space | interval with the wafer A of the selection lot A arises more than necessary, and generation | occurrence | production of the supply delay of the wafer to an exposure apparatus can be prevented. Thus, since the wafer can be smoothly conveyed from the processing unit B2 to the exposure apparatus B4, the throughput can be improved from this point as well.

Here, this titration time is for executing the next cycle of the execution cycle, which is obtained in consideration of past circumstances such as the setting processing remaining time and the execution time of the execution cycle in the module to be set, as shown in Equation 3 above. It is an ideal time. At the end of the execution cycle, this titration time is determined, the titration time is compared with the execution time, and the standby control of the main arm is performed only when the titration time is long, thereby reviewing the time for performing the next cycle at the end of the execution cycle. This enables control to wait for the start of the next cycle for the minimum time necessary when necessary. On the other hand, in the conventional control method, since the control is performed based on the cycle time, which is the maximum time of the transfer cycle, the waiting time becomes too long as compared with the case of obtaining an appropriate time for each execution cycle as in the present invention, and the module setting processing. After the completion of the process, the time until the wafer B is loaded into the module to be set becomes long.

In the above, as a setting object module of this invention, a coating module other than a heating module can be used. The coating module rotatably holds the wafer W by the spin chuck, and drops the coating liquid from the coating nozzle onto the wafer W on the spin chuck to rotate the wafer W, thereby rotating the wafer W. Although the coating liquid is applied to the coating liquid), the setting treatment in this case is a dummy-dispensing process of preliminarily discharging the coating liquid from the nozzle before supplying the coating liquid to the substrate. In addition, the setting process includes all the preparatory processes for processing the wafer such as the temperature control process of the resist liquid and the roughness setting process of the peripheral exposure apparatus.

Moreover, this invention isolate | separates the block for forming a resist film which contains the coating unit of a resist liquid, and the anti-reflective film formation unit, the block which performs a development process, the conveyance path | route which a wafer faces to an exposure apparatus from a carrier block, and exposure. It is also applicable to the application | coating which formed the conveyance path toward a carrier block from an apparatus each independently, and the conveyance control of the wafer W in the developing apparatus. Moreover, this invention can be applied also to the application | coating and developing apparatus which process not only a semiconductor wafer but also board | substrates, such as a liquid crystal display glass substrate (LCD substrate).

1 is a plan view showing an embodiment of a resist pattern forming apparatus according to the present invention.

2 is a perspective view showing the resist pattern forming apparatus.

3 is a plan view showing a conveyance path of a wafer W in a processing unit in the resist pattern forming apparatus.

4 is a configuration diagram showing a part of a control unit in the resist pattern forming apparatus.

5 is a process chart for explaining the operation of the resist pattern forming apparatus.

FIG. 6 is a conveyance schedule illustrating an example of a conveyance schedule used in the resist pattern forming apparatus. FIG.

7 is a plan view showing a conventional coating and developing apparatus.

8 is a configuration diagram showing an example of a conventional transport schedule.

<Explanation of symbols for the main parts of the drawings>

W: semiconductor wafer

C: Carrier

B1: carrier loading part

B2 processing unit

B3 interface

B4: exposed part

A1, A2: main arm

4: control unit

24: means of delivery

43: setting processing unit

44: return schedule preparation unit

45: standby control unit

46: return control unit

Claims (7)

The carrier which accommodated the several board | substrate is mounted, The carrier mounting part provided with the conveyance means which delivers a board | substrate between carriers, The board | substrate after exposure, forming a coating film in the board | substrate conveyed from this carrier mounting part, Has a processing unit for developing the In the processing unit, the substrate conveying means conveys the substrate to a temperature control module for controlling the temperature of the substrate, a coating module for applying the coating liquid to the substrate, a heating module for heating the substrate, and a developing module for developing the substrate. , When the place where the said board | substrate is put is called a module, based on the conveyance schedule set previously, the board | substrate conveying means forms the state in which the board | substrate with smaller order is located in the module of a downstream side rather than the board | substrate with larger order, thereby In the application | coating and the image development apparatus by which conveyance of a board | substrate is performed by executing one conveyance cycle and completing the said conveyance cycle, and then carrying out the following conveyance cycle, At least one of the said application | coating module and a heating module, and after completion | finish of a process by the said module with respect to the board | substrate of the selection lot discharged | emitted from one carrier, setting in the said module before the board | substrate of a later lot is conveyed to the said module. A setting target module to be processed, In the transfer schedule, after carrying out the last substrate of the selection lot to the processing unit, and executing one transfer cycle for the time required for the setting process until the first substrate of the late lot is transferred to the processing unit. Means for creating a return schedule to empty the cycle by the number of delay cycles obtained by dividing by the cycle time, which is the maximum time required; In the created return schedule, before the end of the execution cycle, which is a cycle in which the setting processing is performed in the setting target module and a cycle in which the remaining time of the setting processing is performed in the setting target module, and before the next cycle, the setting target is set. For each module, a proper time for executing the next cycle is obtained, and the longest of these is compared with the execution time for executing the execution cycle, and when the titration time is long, the difference between the titration time and the execution time And a means for controlling the substrate transfer means to wait for the start of the next cycle of the execution cycle for a time equivalent to. The cycle according to claim 1, wherein the appropriate time is determined by: {(setting processing remaining time in the module to be set in question) + (the execution time of the execution cycle)-(cycle in which the substrate of the late lot is loaded into the module to be set in this setting) In the time required for the substrate conveying means to deliver the substrate)} ÷ (the number of cycles from the execution cycle to the cycle in which the wafer of the subsequent lot is loaded into the module to be set). An application | coating and developing apparatus characterized by the above-mentioned. The coating and developing apparatus according to claim 1 or 2, wherein the start of the next cycle is that the substrate transfer means receives the substrate transferred from the carrier loading portion to the processing portion. The coating and developing apparatus according to claim 1 or 2, wherein the setting target module is a heating module, and the setting processing is a change processing of a heating temperature. The carrier which accommodated the several board | substrate is mounted, The carrier mounting part provided with the conveyance means which delivers a board | substrate between carriers, The board | substrate after exposure, forming a coating film in the board | substrate conveyed from this carrier mounting part, Has a processing unit for developing the In the processing unit, the substrate conveying means conveys the substrate to a temperature control module for controlling the temperature of the substrate, a coating module for applying the coating liquid to the substrate, a heating module for heating the substrate, and a developing module for developing the substrate. , If the place where the said board | substrate is placed is called a module, based on the conveyance schedule set previously, the board | substrate with a small order will form the state which is located in the module of a downstream side rather than the board with a large order, based on the conveyance schedule preset, In the application | coating and image development method by which conveyance of a board | substrate is performed by performing a conveyance cycle after performing a conveyance cycle by performing one conveyance cycle by this, After completion | finish of a process by the said module about the board | substrate of the selection lot discharged from one carrier and consisting of at least one of the said application module and a heating module, before the board | substrate of a later lot is conveyed to the said module, And a setting target module where setting processing is performed, In the transfer schedule, after carrying out the last substrate of the selection lot to the processing unit, and executing one transfer cycle for the time required for the setting process until the first substrate of the late lot is transferred to the processing unit. Creating a return schedule to empty the cycle by the number of delay cycles obtained by dividing by the cycle time, which is the maximum time required; In the created return schedule, before the end of the execution cycle, which is a cycle in which the setting processing is performed in the setting target module and a cycle in which the remaining time of the setting processing is performed in the setting target module, and before the next cycle, the setting target is set. For each module, a proper time for executing the next cycle is obtained, and the longest of these is compared with the execution time for executing the execution cycle, and when the titration time is long, the difference between the titration time and the execution time And a step of controlling the substrate conveying means to wait for the start of the next cycle of the execution cycle for a time equivalent to. The cycle according to claim 5, wherein the appropriate time is determined by: {(setting processing remaining time in the module to be set in question) + (the execution time of the execution cycle)-(cycle in which the substrate of the late lot is loaded into the module to be set in this setting). In the time required for the substrate conveying means to deliver the substrate)} ÷ (the number of cycles from the execution cycle to the cycle in which the wafer of the subsequent lot is loaded into the module to be set). A coating and developing method characterized by the above-mentioned. A storage medium in which a processing unit forms a coating film on a substrate received from a carrier stacking unit on which a carrier containing a plurality of substrates is loaded, and performs development on a substrate after exposure, and stores a computer program for use in a developing apparatus. The said program is a storage medium characterized by the step group which is woven so that the application | coating and developing method of Claim 5 or 6 may be performed.

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