JP4639623B2 - Electro-optical device and electronic apparatus - Google Patents

Description

The present invention relates to a technique for preventing a direct current component from being applied to an electro-optical material for a long time in an electro-optical device using an electro-optical material such as liquid crystal.

An electro-optical device that performs a predetermined display by electro-optical change of an electro-optical material generally has a configuration in which pixels are provided corresponding to intersections of a plurality of scanning lines and a plurality of data. Here, in an electro-optical device using liquid crystal as an electro-optical material, the element substrate and the counter substrate sandwich the liquid crystal. Among these, on the element substrate side, a switching element (typically a thin film transistor) that is turned on when the scanning line is selected, and a switching element corresponding to each of the intersections of the scanning line and the data line, When turned on, a pair with a pixel electrode to which an image signal supplied to the data line is applied is provided, and on the opposite substrate side, a common electrode is opposed to each pixel electrode with a liquid crystal interposed therebetween. Provided.

In this configuration, the amount of light transmitted through the liquid crystal layer with the liquid crystal sandwiched between the pixel electrode and the common electrode varies depending on the effective value of the voltage between the two electrodes, depending on the alignment film or polarizer that determines the initial alignment state of the liquid crystal. To do. For this reason, when the switching element is turned on by selecting the scanning line and an image signal having a voltage corresponding to the brightness (gradation) of the pixel is supplied to the data line, the intersection of the scanning line and the data line occurs. The corresponding pixel can be made to have a gradation corresponding to the voltage of the image signal. By repeating this operation for all of the pixels,
A predetermined display can be performed. Since this liquid crystal deteriorates due to the application of a direct current component, the voltage of the image signal applied to the pixel electrode is alternately high (positive) and low (negative) at predetermined intervals with respect to the potential of the common electrode. Inverted so as to be supplied.

By the way, in this electro-optical device, for example, when the power is turned off, the liquid crystal layer has a property of holding the voltage of the image signal last applied to the pixel electrode due to its capacitive property. Since the image signal is not inverted after the power supply is cut off, the electric charge remains and the DC component is applied. As a result, the liquid crystal and the alignment film are deteriorated. For this reason, after the power is turned on again, a so-called burn-in phenomenon occurs in which a false image irrelevant to the image signal is fixedly generated in that portion.
As a technique for preventing such burn-in phenomenon, for example, a process of grounding the common electrode to the lower potential (ground potential) of the power supply is provided as a series of sequences before shutting off the power supply or stopping the display. A device that leaks charges held in a liquid crystal layer is known (see Patent Document 1).
JP 2001-147416 A (see paragraphs 0068 and 0077 and FIG. 8).

However, even if the common electrode is grounded to the ground potential in this way, the common electrode is in a floating state after the power is shut off or the display is stopped.
If the time during which the common electrode is grounded to the lower potential is short, there is a possibility that electric charges remain in the liquid crystal layer. In particular, in a configuration in which a storage capacitor is provided in parallel with the liquid crystal layer in order to reduce charge leakage of the liquid crystal layer during display, the capacitance of the liquid crystal layer is apparently increased,
Since the charge is less likely to leak, the possibility that the charge remains in the liquid crystal layer is increased.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide an electro-optical device and an electronic apparatus that prevent the occurrence of a burn-in phenomenon in an electro-optical material.

An electro-optical device according to an embodiment of the invention includes a scanning line, a data line, a scanning line driving circuit that selects the scanning line with a power supply voltage based on a ground potential , and the data line with the power supply voltage. A data line driving circuit for selecting and supplying an image signal to the selected data line; a pixel electrode to which the image signal supplied to the data line is applied when the scanning line is selected; and the pixel electrode A common electrode opposed to each other with an electro-optic material interposed therebetween, electrically inserted between the data line and the pixel electrode, and turned on when the scanning line is selected, and a semiconductor layer, a transistor including a gate electrode layer and a wiring layer, and a conductive electrode electrically connected to the common electrode, and a ground line for supplying the ground potential to the scanning line driving circuit, an external terminal for inputting a signal from the outside The external terminal and is provided so as to electrically connect the conductive electrode, and the common potential line for supplying a common potential to the common electrode via the conductive electrode, and the common potential line and the ground line A resistor electrically connected to the common potential wiring and the ground wiring, and the common potential wiring includes a first side and a second side intersecting the first side, A third side intersecting with the second side, and the ground wiring intersects the fourth side with a fourth side having a portion facing the first side, and the second side. A fifth side extending in the same direction as the side of the first side, and a sixth side having a portion that intersects the fifth side and faces the third side of the common potential wiring, and , together with those obtained by patterning the gate electrode layer, said first side, said first side The sixth side that direction, and characterized in that the patterning in a zigzag shape in said second side and said second plane spatial provided by the fifth side opposite to the side .
The resistance value of the resistor of the electro-optical device according to an embodiment of the invention may be 100 kΩ or more and 500 kΩ or less.
An electronic apparatus according to an embodiment of the invention includes the electro-optical device described above.
An electro-optical device according to an embodiment of the present invention includes a plurality of scanning lines, a plurality of data lines, a scanning line driving circuit that sequentially selects the scanning lines with a power supply voltage based on a ground line, and the ground line. The data line is selected with a power supply voltage based on the data line, and the data line driving circuit for supplying an image signal to the selected data line, and when the scanning line is selected, the image signal supplied to the data line is applied. A pixel electrode, a common electrode opposed to each of the pixel electrodes with an electro-optic material interposed therebetween, and a resistor electrically connected between the common electrode and the ground line. And According to this configuration, since the common electrode is grounded to the ground line via the resistor, the charge held in the capacitive component that sandwiches the electro-optic material by the pixel electrode and the common electrode after the power is shut off, Leak through resistance. For this reason, the direct current component is not applied to the capacitive component for a long time.

In the present invention, when the image signal is supplied via one or more image signal lines provided on the element substrate, the electro-optical material is deteriorated by the voltage held on the image signal line. there is a possibility. Therefore, in such a case, a configuration may be adopted in which a resistor is electrically connected between the image signal line and the ground line.
Also, if the resistance value of the resistor is too high, it takes time to leak charges,
If it is too low, a current flows through the resistor and power consumption increases. Therefore, the resistance value of the resistor is preferably 100 kΩ or more and 500 kΩ or less.

Furthermore, the present invention includes a transistor that is electrically inserted between the data line and the pixel electrode and is turned on when the scanning line is selected, and includes a semiconductor layer, a gate electrode layer, and a wiring layer. The resistor preferably has a configuration in which the gate electrode layer is patterned. According to this configuration, when the transistor is formed on the element substrate, the resistor is also formed, so that it is not necessary to add a separate process. Furthermore, in this configuration, the gate electrode layer as the resistor may be formed by patterning fine lines in a twisted manner. This makes it possible to stably form a high resistance in a relatively narrow region.
In addition, since the electronic apparatus according to the present invention includes the electro-optical device, high-quality display is possible without causing a burn-in phenomenon.

The best mode for carrying out the present invention will be described below with reference to the drawings.
First, the electro-optical device according to the embodiment uses liquid crystal as an electro-optical material and performs predetermined display by electro-optical change, and is used as a light valve of a projector.
FIG. 1A is a perspective view showing a configuration of the liquid crystal panel 100 excluding an external circuit in the electro-optical device, and FIG. 1B is a cross-sectional view taken along line bb ′ in FIG. FIG. 1 is a cross-sectional view
(C) is sectional drawing of the cc 'line in Fig.1 (a).
As shown in these drawings, the liquid crystal panel 100 is a peripheral circuit built-in type, and includes an element substrate 101 on which various elements and pixel electrodes 118 are formed, and a counter substrate 102 on which a common electrode 108 and the like are provided. In addition, the sealing material 104 including spacers (not shown) is bonded so that the electrode formation surfaces face each other while maintaining a certain gap, and an TN (Twisted Nematic) type liquid crystal, for example, is used as an electro-optical material in the gap. 105 is enclosed.

Here, glass, quartz, or the like is used for the element substrate 101, and transparent glass or the like is used for the counter substrate 102. In the present embodiment, since the liquid crystal panel 100 is a transmissive type, the element substrate 101 also has transparency, but in the case of a reflective type, it may be opaque like a semiconductor substrate. The sealing material 104 is formed in a frame shape along the periphery of the counter substrate 102, but a part thereof is opened to enclose the liquid crystal 105. For this reason, the liquid crystal 10
After the sealing of 5, the opening is sealed with a sealing material 106.

Next, a sampling signal output circuit, which will be described later, is formed in a region 140 a on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104. Furthermore, the area 140a
A plurality of mounting terminals 107 are formed on the outer peripheral portion of the, and various signals from an external circuit (not shown) are input.
In addition, a scanning line driving circuit, which will be described later, is formed in each of the two side regions 130a adjacent to the one side, so that the scanning lines are driven from both sides. Note that if the delay of the scanning signal supplied to the scanning line is not a problem, a configuration in which the scanning line driving circuit is formed on only one side may be employed. Note that a common wiring used for two scanning line driving circuits is formed in the remaining one side region.

FIG. 1C is a cross-sectional view when the liquid crystal panel 100 is broken along one piece of the sealing material 104. As shown in this figure, the common electrode 108 of the counter substrate 102 is connected to the element substrate 1.
Electrical conduction is achieved by the conductive electrode 109 provided on the element substrate 101 and the conductive material 103 such as silver paste at the four corners of the bonding portion with 01.
In addition, although not illustrated, the counter substrate 102 is provided with a light shielding film (black matrix) in a display area where the pixel electrodes 118 are arranged and a non-display area surrounding the display area. This light shielding film is provided in the display area so as to avoid the area facing the pixel electrode 118,
While preventing a decrease in contrast, the non-display area functions as a frame (parting).
In addition, an alignment film (not shown) that is rubbed so that the major axis direction of molecules in the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates is provided on the opposing surfaces of the element substrate 101 and the counter substrate 102. On the other hand, a polarizer (not shown) corresponding to the orientation direction is provided on each back side.

In this configuration, the light passing between the pixel electrode 118 and the counter electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules if the effective voltage value of the liquid crystal layer is zero, while the effective voltage value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in the transmission type, in the normally white mode in which polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side, the effective voltage value of the liquid crystal layer is zero. If so, the light transmittance is maximized to produce a white display, while the amount of transmitted light decreases as the effective voltage value increases, and finally the black display has the smallest transmissivity.
In FIG. 1B and FIG. 1C, the common electrode 108, the pixel electrode 118,
Although the mounting terminal 107 has a thickness, this is a convenient measure for indicating the formation position, and is actually thin enough to be ignored with respect to the substrate.

Next, an electrical configuration of the element substrate 101 in the liquid crystal panel 100 described above will be described. FIG. 2 is a schematic diagram showing this configuration.
As shown in this figure, the element substrate 101 is provided with a plurality of mounting terminals 107 for inputting various signals from an external circuit. A signal input via these mounting terminals 107 is supplied to each part via wiring.
Here, the signal supplied via the mounting terminal 107 will be briefly described. First,
VssY and VddY are the lower voltage (ground potential) and the higher voltage of the power source in the scanning line driving circuit 130, respectively, and the scanning line driving circuit 130 via the wirings 132 and 134, respectively.
To be supplied.
Further, VssX and VddX are the lower voltage and the higher voltage of the power supply in the sampling signal output circuit 140, and are supplied to the sampling signal output circuit 140 via the wirings 142 and 144, respectively.
Note that the lower side of the power supply voltage is connected to the scanning line driving circuit 130 and the sampling signal output circuit 140.
Are divided into VssY and VssX for the sake of convenience, but are actually common. Similarly, the higher side of the power supply voltage is also divided into VddY and VddX for each of the scanning line driving circuit 130 and the sampling signal output circuit 140, but is actually common.

Secondly, Vid1 to Vid6 are image signals supplied from an external circuit, and in accordance with the dot clock signal DCLK, one system of video signals Vid supplied in synchronization with vertical scanning and horizontal scanning is supplied to six systems. Is an image signal that is distributed six times and expanded six times on the time axis, and has a voltage corresponding to the gradation (brightness) of the pixel. Six of the image signal lines 171 are wirings for supplying the image signals Vid1 to Vid6, respectively. Each of the image signal lines 171 is
Each is grounded to the wiring 142 via the resistor 164.

Third, LCcom is a voltage signal applied to the common electrode 108. For this reason, the voltage L
Ccom is supplied to the four conductive electrodes 109 via the wiring 182. Here, the conductive electrode 1
09 is provided at points corresponding to the four corners of the sealing material 104 used for bonding to the counter substrate 102. Therefore, when the element substrate 101 is actually bonded to the counter substrate 102, the conductive electrode 109 and the common electrode 108 are connected via the conductive material 103,
The voltage LCcom is applied to the common electrode 108. Note that the wiring 182 connecting the mounting terminal 107 and the conductive electrode 109 is grounded to the wiring 132 through the resistor 162.
The voltage LCcom is constant with respect to the time axis, and the external circuit distributes the image signals Vid1 to Vid6 to, for example, the high-order side and the low-order side every horizontal scanning period with reference to the voltage LCcom. ing. In addition, the conductive electrode 109 is provided at the four corners in the present embodiment, but the reason why the conductive electrode 109 is provided is to apply the voltage LCcom to the counter electrode 108 via the conductive material 103. The conductive electrode 109 may be provided at least one place.
On the other hand, in this embodiment, the voltage LCcom is commonly applied to one of the storage capacitors, as will be described later, and is also supplied to each pixel 110 via the capacitor line 175.
In addition, a predetermined clock signal or the like is supplied to the scanning line driving circuit 130 and the sampling signal output circuit 140 in addition to this, but since it is not directly related to the present invention, explanation of these signal waveforms, signal lines, etc.・ The illustration is omitted.

Now, in the display area 110a of the element substrate 101, a plurality of scanning lines 112 are arranged in a row (Y
) Are arranged in parallel along the direction, and a plurality of data lines 114 are arranged in parallel along the column (X) direction, and a pixel 110 is provided corresponding to each intersection. Here, for convenience of explanation, if the total number of scanning lines 112 is “m” and the total number of data lines 114 is “6n” (m and n are integers), the pixels are the same as the scanning lines 112. Corresponding to each intersection with the data line 114, it is arranged in a matrix of m rows × 6n columns.

When this pixel 110 is viewed as a single element substrate 101, as shown in FIG. 3A, switching for controlling the pixel at a portion where the scanning line 112 and the data line 114 intersect is electrically performed. While the gate of the TFT 116 as an element is connected to the scanning line 112, TF
The source of T116 is connected to the data line 114, and the drain of the TFT 116 is connected to a rectangular transparent pixel electrode 118. The pixel 110 is also provided with a storage capacitor 119 having one end connected to the drain of the TFT 116 and the other end commonly connected to the capacitor line 175.
Since the liquid crystal panel 100 has a configuration in which the liquid crystal 105 is sandwiched between the electrode formation surfaces of the element substrate 101 and the counter substrate 102 as described above, each pixel 110 has a configuration shown in FIG.
As shown in b), a liquid crystal layer is formed by the pixel electrode 118, the counter electrode 108, and the liquid crystal 105 sandwiched between the two electrodes.

The description returns to FIG. 2 again. As shown in FIG. 6, the scanning line driving circuit 130 scans the scanning signal G <b> 1 that sequentially becomes H level exclusively during the horizontal effective scanning period in the horizontal scanning period (1 </ b> H).
, G2,..., Gm are respectively supplied to the scanning lines 112 of 1 to m rows.
In addition, the sampling signal output circuit 140 sequentially sequentially outputs H in the horizontal effective display period.
Sampling signals S1, S2,..., Sn that are levels are output. Note that the details of the scanning line driving circuit 130 and the sampling signal output circuit 140 are not directly related to the present invention, and thus will not be described and illustrated.

Subsequently, each sampling circuit 150 is composed of an N-channel TFT (sampling switch) provided for each data line 114. This sampling switch is for sampling each of the image signals Vid1 to Vid6 supplied via the six image signal lines 171 to the data line 114.
Specifically, in order to generalize and describe the data line 114, an integer j that satisfies 1 ≦ j ≦ 6n
2, the sampling switch in which the drain is connected to one end of the j-th data line 114 counted from the left in FIG. 2, if the remainder obtained by dividing j by 6 is “1”, the source is It is connected to the image signal line 171 to which the signal Vid1 is supplied. Similarly, each of the sampling switches whose drains are connected to the data lines 114 whose remainders obtained by dividing j by 6 are “2”, “3”, “4”, “5”, “0” Are connected to image signal lines 171 to which signals Vid2 to Vid6 are supplied. For example, in FIG.
The source of the sampling switch whose drain is connected to the data line 114 in the first column is “1
Since the remainder of dividing “1” by 6 is “5”, the image signal line 171 to which the signal Vid5 is supplied.
Connected to.

Further, the sampling signal S (i + 1) is commonly supplied to the gates of the six sampling switches whose drains are connected to the data line 114 whose quotient is i obtained by dividing (j−1) by 6 respectively. For example, in the data lines 114 in the seventh column to the twelfth column, (j−1) is “6” to
Since the quotient obtained by dividing this number by 6 is “1”, the sampling signal S2 is commonly supplied to the gates of the sampling switches corresponding to these data lines 114.
Therefore, for example, when the sampling signal S2 becomes H level, the image signals Vid1 to Vid.
id6 is sampled on the data lines 114 in the seventh to twelfth columns. For this reason, the sampling signal output circuit 140 and the sampling circuit 150 constitute a data line driving circuit.
In the present embodiment, the six data lines 114 having the relationship in which the same sampling signal is supplied to the gate of the sampling switch are considered as one block.

Next, the detailed configuration of the pixel 110 described above will be described with reference to FIG. FIG. 4 is a plan view showing the detailed configuration thereof. In FIG. 4, only the outline of the pixel electrode 118 serving as the uppermost conductive layer is indicated by a broken line for understanding.
In this figure, the first layer, which is the lowest layer of the conductive layer, is a semiconductor layer 30 obtained by patterning a polysilicon layer into an island shape, and its surface is covered with an insulating film formed by thermal oxidation. The second layer is a gate electrode layer obtained by patterning polysilicon or the like, and the scanning line 1 extending in the X direction.
12 and the capacitor line 175 are formed. The third layer is a wiring layer obtained by patterning a good conductive metal layer such as aluminum, and forms the data line 114 extending in the Y direction. Further, the fourth layer is obtained by patterning a transparent conductive layer such as ITO (Indium Tin Oxide), and forms the pixel electrode 118. Note that these conductive layers are electrically insulated by an insulating layer.

Here, the capacitor line 175 is provided so as to extend in the X direction in parallel with the scanning line 112, but in a portion intersecting with the data line 114 extending in the Y direction, It is formed so as to protrude to the front side (upper side in FIG. 4) so as to overlap. In such a wiring, the semiconductor layer 30 starts from the point where the data line 114 and the capacitor line 175 intersect, the extending direction of the capacitor line 175 (right direction in FIG. 4), and the capacitor line 1 below the data line 114.
It extends in a total of three directions, 75 projecting directions (upward) and opposite directions (downward), and is approximately T
It is formed in a letter shape.

A portion of the semiconductor layer 30 that overlaps with the scanning line 112 is a channel region. In other words, a portion of the scanning line 112 that intersects the semiconductor layer 30 (shaded portion in FIG. 4).
Is used as the gate electrode 116G. Further, the semiconductor layer 30 includes the source region 1.
16S and drain region 116D are provided. The source region 116 </ b> S is connected to the data line 114 through the contact hole 51, while the drain region 116 </ b> D is connected to the pixel electrode 118 through the contact hole 53. In addition, a part of the drain region 116 </ b> D in the semiconductor layer 30 functions as one electrode of the storage capacitor 119. That is, in the storage capacitor 119, the semiconductor layer 30 has the drain region located below the capacitor line 175 as one electrode and the capacitor line 175 itself as the other electrode.
The insulating film formed on the surface is sandwiched.
As described above, the semiconductor layer 30 is formed in a state of being hidden under the region where the scanning line 112, the data line 114, and the capacitor line 175 are formed. On the other hand, a light shielding layer (not shown) is provided below the semiconductor layer 30 to prevent light from entering from the lower surface side of the element substrate. For this reason, since the TFT 116 has a structure in which light does not easily enter from both the observation side and the back side of the element substrate, it is possible to prevent deterioration in characteristics due to light leakage, an increase in off-resistance, and the like.

Next, the configuration of the resistor 162 and its periphery will be described. FIG. 5A shows a resistor 162.
It is a top view which shows the structure of these.
In this figure, wirings 132 and 182 are obtained by patterning a wiring layer which is the third layer of the display region 110a. Note that only the wirings 132 and 182 are shown here, but the other wirings 134, 142, and 144, the image signal line 171 and the conductive electrode 109 are also patterned by wiring layers that are the third layer. is there.
The resistor 162 is formed by patterning the gate electrode layer, which is the second layer of the display region 110a, in a distorted manner (zigzag shape) as shown in FIG.
The other end is connected to the wiring 182 through the contact hole 282, while being connected to the wiring 132 through 32.

Here, the resistor 162 includes the wiring 132 that supplies the lower power supply voltage (ground voltage) in the scanning line driving circuit 130 via the mounting terminal 107 and the conductive electrode 1 via the mounting terminal 107.
09 is interposed between the wiring 182 that supplies the voltage LCcom to 09 and has a high resistance from the viewpoint of suppressing the through current and the power consumption (details will be described later as 100 k).
Ω to about 500 kΩ).
Although the gate electrode layer has a higher resistivity than the wiring layer, it has a conductivity that does not cause a problem when used as the scanning line 112 or the like, and thus cannot be simply adopted as the high resistance as described above.
Therefore, in this embodiment, the gate electrode layer, which is the main body of the resistor 162, is made into a thin line state with a narrow line width and a long line length in order to increase resistance and suppress the formation area as much as possible. Patterned in a twisted pattern.

Although not particularly illustrated, each of the resistors 164 electrically inserted between the image signal line 171 and the wiring 142 is also formed by patterning the gate electrode layer as the second layer in the same manner as the resistor 162. The
If the pitch between the image signal lines 171 is narrow, and the resistors 164 are formed on the same line,
Since it becomes difficult to secure a formation region in a direction orthogonal to the extending direction of the image signal line 171, for example, as shown in FIG. 2, the resistor 164 is sequentially shifted in the same direction,
It is preferable to arrange them alternately.
In addition, since the regions where the resistors 162 and 164 are formed are regions that do not contribute to display, the regions are preferably covered with a light shielding layer.

Scanning line driving circuit 130, sampling signal output circuit 140, sampling circuit 150
The peripheral circuit components such as the above are also formed by a common process with the TFT 116 in the display region 110a.
Specifically, the constituent elements of the peripheral circuit are also TFTs 200 as shown in FIG.
The semiconductor layer 202 is obtained by patterning the semiconductor layer 30 that is the first layer in the TFT 116, and the gate electrode 212 is obtained by patterning the gate electrode layer that is the second layer, and its source (S), drain ( D) The electrode is obtained by patterning the wiring layer as the third layer.
That is, since the resistors 162 and 164 are formed in common with the display region 110a and components such as peripheral circuits including wiring, the manufacturing process is not complicated when the resistors 162 and 164 are added.

Next, the operation of the electro-optical device according to the above configuration will be described.
First, a display operation during a period in which the power is turned on will be described. As shown in FIG. 6, the scanning line driving circuit 130 scans the scanning signal G1, which sequentially becomes H level exclusively in the horizontal effective scanning period in one horizontal scanning period (1H) over one vertical scanning period (1F). G
2, ..., Gm is output. Note that since the scanning line driver circuit 130 uses (VddY−VssY) as a power supply, the H level potential of the scanning signal is VddY and the L level potential is VssY.
It is.
Here, paying attention to the horizontal effective scanning period when the scanning signal G1 becomes H level, the sampling signal output circuit 140 outputs sampling signals S1, S2,..., Sn that become sequentially H level exclusively during the horizontal effective display period. To do. The sampling signal output circuit 140
Uses (VddX−VssX) as the power supply, so the H level potential of the sampling signal is V
It is ddX, and the L level potential is VssX.
On the other hand, one system of image signals Vid is distributed to six systems of image signals Vid1 to Vid6 by an external circuit, and is expanded six times with respect to the time axis. Here, when the pixels 110 in the first row are written with positive polarity, the image signals Vid1 to Vid6 become higher voltages than the voltage LCcom as the pixels are black.
In FIG. 6, the voltage Vb (+) corresponds to a voltage that causes the pixel to become black with the lowest luminance in the case of positive writing, and is slightly lower (or equal) than the high-side voltages VddX and VddY. . Further, the voltage Vg (+) corresponds to a voltage that makes a pixel gray, which is an intermediate point between the lowest luminance and the highest luminance, in the case of positive polarity writing.

Now, when the scanning signal G1 becomes H level, all the TFTs 116 in the pixels 110 in the first row of the display area 110a counted from the top in FIG. 2 are turned on. In this state, when the sampling signal S1 becomes H level, each of the image signals Vid1 to Vid6
In FIG. 2, the data lines 114 are sampled on the first to sixth columns of data lines 114 from the left. Therefore, the sampled image signals Vid1 to Vid6 are used as the scanning lines 112 in the first row.
Are applied to the pixel electrodes 118 of the pixels 110 corresponding to the intersections of the data lines 114 in the first to sixth columns.
Thereafter, when the sampling signal S2 becomes H level, each of the image signals Vid1 to Vid6 is sampled on the data lines 114 in the 7th to 12th columns, respectively. For this reason,
The sampled image signals Vid1 to Vid6 are respectively applied to the pixel electrodes 118 of the pixels 110 corresponding to the intersections of the scanning lines 112 in the first row and the data lines 114 in the 6th to 12th columns.

Similarly, when the sampling signals S3,..., Sn sequentially become active levels,
The image signals Vid1 to Vid6 are sampled on the six data lines 114 in the 13th to 18th columns, ..., (6n-5) to 6n columns, respectively, and these image signals Vid1 to Vid6 are 1
The pixel electrode 11 of the pixel 110 that intersects the sixth scanning line 112 and the six data lines 114.
8 will be written respectively. As a result, writing to all the pixels in the first row is completed.
When writing to all the pixels in the first row is completed, the scanning signal G1 becomes L level, and all the TFTs 116 in the pixels 110 in the first row are turned off. However, due to the capacitance of the storage capacitor 119 and the liquid crystal layer itself, the pixel electrode The voltage written when the TFT 116 is turned on is held in 118, and the gradation corresponding to the held voltage is maintained.

Next, the operation during the period in which the scanning signal G2 is at the H level is the same as the period during which the scanning signal G1 is at the H level, and the sampling signals S1, S2, S3,. Writing to the pixels 110 in the second row is completed. However, since the writing polarity is inverted in the second row and becomes negative, the image signals Vid1 to Vid6 become lower in voltage than the voltage LCcom as the pixels are made black.
In FIG. 6, the voltage Vb (−) corresponds to a voltage that makes the pixel black in the case of negative writing, and is slightly higher (or equal) than the high-side voltages VssX and VssY of the power supply.
. The voltage Vg (−) corresponds to a voltage that makes the pixel gray in the case of negative polarity writing.

Similarly, the scanning signals G3, G4,..., Gm become H level, and writing is performed on the pixels in the third row, fourth row,. As a result, the positive polarity writing is performed for the pixels in the odd-numbered rows, while the negative polarity writing is performed for the pixels in the even-numbered rows, and all of the pixels in the first to m-th rows in this one vertical scanning period. The writing is completed over the entire time.
Note that the period between the horizontal effective scanning periods corresponds to a horizontal blanking period. In this horizontal blanking period, the image signals Vid1 to Vid6 take a voltage corresponding to black and are inverted in polarity.

In the next one vertical scanning period (1F), similar writing is performed. At this time, the writing polarity for the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows. Thus, in the period when the power is turned on,
Since the writing polarity with respect to the pixel is switched every vertical scanning period, a direct current component is not applied to the liquid crystal 105 or the alignment film.

Thus, if the power is turned on, positive polarity writing and negative polarity writing are executed alternately, so that no direct current component is applied to the liquid crystal 105 or the alignment film. However, when the power is turned off, the voltage last written to the pixel electrode 118 is continuously held by the capacitance of the storage capacitor 119 and the liquid crystal layer itself, so that a direct current component is applied to the liquid crystal 105 and the alignment film. It will be. In contrast, in the present embodiment, the common electrode 108 is connected to the wiring 132 to which the lower voltage of the power source is applied via the conductive material 103 → the conductive electrode 109 → the wiring 182 → the resistor 162.
Therefore, after the power supply is cut off, the charges accumulated in the liquid crystal layer leak quickly. For this reason, the direct current component is prevented from being applied to the liquid crystal 105 and the alignment film for a long time,
It is possible to continue to maintain a high-quality display state without burn-in.

Further, depending on the external circuit, the image signal line 171 may be in a high impedance state after the power is shut off. In this case, the image signal line 171 holds the voltage of the last sampled image signal when the power is turned off. Here, since the off-resistance (general TFT off-resistance) such as the switch of the sampling circuit 150 and the TFT 116 of the pixel 110 is relatively low, the voltage of the data line 114 and the voltage of the pixel electrode 118 are maintained. There is a tendency to approach the voltage on line 171. On the other hand, in the present embodiment, each of the image signal lines 171 is grounded to the wiring 142 to which the lower voltage of the power source is applied via the resistor 164, so that the voltage of the image signal line 171 is When the power is cut off, it becomes zero immediately. For this reason, the voltage of the data line 114 and the pixel electrode 118 also becomes zero within a short time, and similarly, a direct current component is prevented from being applied to the liquid crystal 105 and the alignment film for a long time.

As described above, the resistance values of the resistors 162 and 164 are desirably high resistance from the viewpoint of suppressing power consumption. However, if the resistance is increased without limitation, the charge is less likely to leak after the power is cut off, and a DC component is applied to the liquid crystal 105 and the alignment film for a long time, making it impossible to achieve the initial purpose. In addition, it is generally difficult to stably form such a high resistance by a semiconductor process. On the other hand, if the resistance values of the resistors 162 and 164 are lowered, the electric charge is likely to leak after the power is turned off, but the through current flowing during the power-on period is increased, and the power consumption cannot be reduced.
Under such circumstances, the inventor of the present application experimentally obtained an appropriate resistance value, and if the resistance value is 100 kΩ or more, the power consumption is not a problem, and the resistance value is 500 kΩ or less. If so, it was determined that it would not affect the decrease in charge leakage rate.

In the above-described embodiment, the image signal Vid is converted into the 6-channel image signals Vid1 to Vi.
However, the number of channels to be expanded is not limited to “6”.
The above is sufficient, and the present invention can also be applied to driving for selecting data lines dot-sequentially and line-sequentially without developing image signals.
Further, in the above-described embodiment, the description has been given of the normally white mode in which white display is performed when the effective voltage value between the counter electrode 108 and the pixel electrode 118 is small. However, the normally black mode in which black display is performed may be used. good.
In the above-described embodiment, the TN type is used as the liquid crystal, but BTN (Bi-stable Twisted Ne) is used.
matic) and ferroelectric types such as bistable types with memory properties, polymer dispersed types, and dyes that have anisotropy in visible light absorption in the long and short axis directions of molecules (guests) ) May be dissolved in a liquid crystal (host) having a certain molecular arrangement, and a GH (guest host) type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules may be used.

In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods. The above has been described by taking a liquid crystal as an example of the electro-optical material, but it can be widely applied to an electro-optical material whose characteristics deteriorate when a direct current component is applied for a long time.

<Electronic equipment>
Next, a projector using the above-described liquid crystal panel 100 as a light valve will be described as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment.
FIG. 7 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 includes a lamp unit 21 made of a white light source such as a halogen lamp.
02 is provided. The projection light emitted from the lamp unit 2102 is R (by the three mirrors 2106 and two dichroic mirrors 2108 arranged inside.
The light valve 100 is divided into three primary colors of red, G (green), and B (blue), and corresponds to each primary color.
Guided to R, 100G and 100B, respectively. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal panel 100 in the above-described embodiment, and R, G, and R supplied from a processing circuit (not shown).
It is driven by an image signal corresponding to each color of B.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight.
Therefore, after the images of the respective colors are combined, the projection lens 2114 is displayed on the screen 2120.
As a result, a color image is projected.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to the primary colors of R, G, and B is incident by 108, there is no need to provide a color filter. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The left-right reversed image is displayed in the direction opposite to the horizontal scanning direction by the light valve 100G.

In addition to the electronic device described with reference to FIG. 7, the direct view type, for example, a mobile phone, personal computer, television, video camera monitor, car navigation device, pager, electronic notebook, calculator, word processor , Workstations, videophones, POS terminals, digital still cameras, devices equipped with touch panels, and the like. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. 2 is a block diagram showing an electrical configuration of an element substrate of the same electro-optical device. FIG. FIG. 3 is an equivalent circuit diagram illustrating a configuration of a pixel in the electro-optical device. FIG. 3 is a plan view illustrating a configuration of a pixel in the electro-optical device. FIG. 5A is a plan view illustrating a configuration of a resistor in the electro-optical device, and FIG. 5B is a plan view illustrating a configuration of a transistor in the electro-optical device. 6 is a timing chart showing the operation of the electro-optical device. It is a figure which shows the structure of the projector to which the same electro-optical apparatus is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Liquid crystal panel, 108 ... Common electrode, 109 ... Conduction electrode, 110 ... Pixel, 112 ...
Scan line 114 ... Data line 116 ... TFT 118: Pixel electrode 130 ... Scan line drive circuit 140 ... Sampling signal output circuit 150 ... Sampling circuit 132,134
142, 144 ... wiring, 162, 164 ... resistance, 171 ... image signal line, 2100 ... projector

Claims (3)

Scanning lines;
Data lines,
A scanning line driving circuit for selecting the scanning line with a power supply voltage based on the ground potential ;
A data line driving circuit for selecting the data line with the power supply voltage and supplying an image signal to the selected data line;
A pixel electrode to which an image signal supplied to the data line is applied when the scanning line is selected;
A common electrode facing the pixel electrode with an electro-optic material interposed therebetween;
A transistor that is electrically inserted between the data line and the pixel electrode and is turned on when the scanning line is selected; and includes a semiconductor layer, a gate electrode layer, and a wiring layer;
A conductive electrode electrically connected to the common electrode;
Ground wiring for supplying the ground potential to the scanning line driving circuit;
An external terminal for inputting an external signal;
A common potential wiring provided to electrically connect the external terminal and the conduction electrode, and supplying a common potential to the common electrode through the conduction electrode;
A resistor electrically connected to the common potential line and the ground line between said ground line and the common potential line,
Comprising
The common potential wiring has a first side, a second side that intersects the first side, and a third side that intersects the second side,
The ground wiring includes a fourth side having a portion facing the first side, a fifth side crossing the fourth side and extending in the same direction as the second side, And a sixth side having a portion that intersects with the third side and faces the third side of the common potential wiring,
The resistor is obtained by patterning the gate electrode layer and faces the first side, the sixth side facing the first side, the second side, and the second side. An electro-optical device, wherein the electro-optical device is patterned in a zigzag manner in a planar space provided by the fifth side .   The electro-optical device according to claim 1, wherein a resistance value of the resistor is 100 kΩ or more and 500 kΩ or less. An electronic apparatus comprising the electro-optical device according to claim 1 or 2.

Images