JP4753618B2

JP4753618B2 - Display device

Info

Publication number: JP4753618B2
Application number: JP2005143157A
Authority: JP
Inventors: みちる千田; 良一横山
Original assignee: 三洋電機株式会社
Priority date: 2004-05-21
Filing date: 2005-05-16
Publication date: 2011-08-24
Anticipated expiration: 2025-05-16
Also published as: JP2006011392A

Description

The present invention relates to a display device in which pixel circuits are arranged in a matrix.

Conventionally, a liquid crystal display device is known as a display device that can be thinned and miniaturized and has low power consumption, and is used as a display for various devices. This liquid crystal display device (hereinafter referred to as LCD) has a structure in which two substrates each having an electrode formed on the opposite surface side are sealed with liquid crystal interposed therebetween, and a voltage signal is applied between the electrodes. Display is performed by controlling the light transmittance from the light source by controlling the alignment of the liquid crystal whose optical characteristics change depending on the alignment state.

Here, it is known that when a DC voltage is continuously applied between the electrodes formed on the opposite surface side of the substrate, the alignment state of the liquid crystal molecules is fixed, that is, a so-called burn-in problem occurs. Conventionally, as a voltage signal for driving a liquid crystal, an AC voltage signal whose polarity with respect to a reference voltage is periodically inverted is employed.

As a method of reversing the polarity of the liquid crystal driving voltage signal, in a liquid crystal display device in which a plurality of pixels are arranged in a matrix, inversion for each frame and for each vertical scanning (1 V) unit (or for each field). Inversion is known for one horizontal scanning (1H) unit and one pixel (one dot) unit. One frame unit is, for example, one frame unit in the NTSC signal, and one field unit corresponds to each unit (for example, odd field and even field) of a plurality of fields constituting one frame.

The dot inversion method for inverting the polarity in units of one pixel (dot) shown in Patent Document 1 is preferable because the inversion hardly affects the display quality among the above methods. However, there is a problem that the driving method tends to be complicated.

In the dot inversion method, Patent Document 1 proposes changing the voltage of the SC line, which is a line serving as a base of the storage capacitor.

JP 2003-150127 A

However, in the configuration of Patent Document 1, two SC lines are required. Therefore, the problem caused by arranging these two SC lines must be solved.

The present invention is a display device in which pixel circuits are arranged in a matrix, and each pixel circuit has one end connected to a data line to which a data signal is supplied and a gate connected to a selection line. Is set to H level or L level, and the pixel TFT is turned on and off, one end is connected to the other end of the pixel TFT, the other end is connected to the storage capacitor line, and the voltage of the data signal supplied from the data line is A storage capacitor for holding, and a liquid crystal element in which one electrode is connected to the other end of the pixel TFT and the other electrode is held at a common power supply potential, and the storage capacitor line turns on the pixel TFT. After the data signal on the data line is written to the storage capacitor, the first level changes to the second level, thereby shifting the voltage applied to the liquid crystal element. Two storage capacitor lines are provided corresponding to each pixel circuit row, and the plurality of pixel circuits arranged in the row direction are connected to one of the two storage capacitor lines. The two storage capacitor lines have two kinds of potentials, and the capacitance values generated at the intersections of the two storage capacitor lines and the data line are set to be substantially the same. And

The two types of potentials are preferably shifted in the opposite direction when one potential is shifted from positive to negative direction or from negative to positive direction.

As described above, according to the present invention, the polarity of the two storage capacitor lines is inverted, and the capacitance value generated at the intersection of the two storage capacitor lines and the data line. Are set almost the same. For this reason, when the voltages of the two storage capacitor lines are inverted, the fluctuation of the potential of the data line can be reduced, and adverse effects on the display can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic configuration of the present embodiment. The pixel circuit 1 is arranged in a matrix over the entire display area. The matrix arrangement may be a zigzag shape instead of a perfect lattice shape. The display may be monochrome or full color, and in the case of full color, the normal pixels are three colors of RGB, but it is also preferable to add pixels of a specific color including white as necessary.

As shown in the figure, one pixel circuit 1 has an n-channel pixel TFT 10 whose drain is connected to the data line DL, and a liquid crystal element 12 and a storage capacitor 14 connected to the source of the pixel TFT 10. . A gate line GL disposed for each horizontal scanning line is connected to the gate of the pixel TFT 10.

The liquid crystal element 12 is configured such that a pixel electrode provided individually for each pixel is connected to the source of the pixel TFT 10, and a common electrode common to all the pixels is opposed to the pixel electrode with a liquid crystal interposed therebetween. The common electrode is connected to the common electrode power source Vcom.

In the storage capacitor 14, the extended portion of the semiconductor layer that constitutes the source of the pixel TFT 10 is directly used as one electrode, and a part of the capacitor line SC formed so as to face the oxide film via the oxide film serves as a counter electrode. Note that the portion that becomes the electrode of the storage capacitor 14 may be separated from the portion of the pixel TFT 10 as another semiconductor layer, and both may be connected by metal wiring.

Here, there are two capacitance lines SC, SC-A and SC-B, for one row (horizontal scanning line), and the storage capacitance of each pixel circuit is SC-A and SC-B in the horizontal scanning direction. Are connected alternately. In the pixel circuit shown in this figure, the storage capacitor 14 is connected to the capacitor line SC-A, and the storage capacitor 14 of the adjacent pixel is connected to the capacitor line SC-B.

A vertical driver 20 is connected to the gate line GL, and the vertical driver 20 sequentially selects the gate lines GL one by one every horizontal period and sets them to the H level. The vertical driver 20 has a shift register, receives a signal STV indicating the start of one vertical scanning period, sets the first stage of the shift register to the H level, and then shifts the H level one by one by a clock signal, for example. Thus, the gate lines GL of each horizontal scanning line are sequentially selected one by one and set to the H level. Here, for example, the H level of the gate line GL is the VDD potential, the L level is the VSS potential, and these power supply voltages VDD and VSS are supplied to the vertical driver 20, whereby the gate line GL that is the output of the vertical driver is output. H level and L level are set.

The SC driver 22 outputs two voltage levels to the two storage capacitor lines SC-A and SC-B.

Although not shown, the display device is also provided with, for example, a horizontal driver, and controls line-sequential supply of the input video signal to the data line DL. That is, in this example, the horizontal driver outputs a sampling clock for each pixel in accordance with the clock of the video signal for each pixel, and the video signal (data signal) for one horizontal scanning line is turned on / off by this sampling clock. Latch. Then, a data signal for each pixel of one latched horizontal scanning line is output to the data line DL over one horizontal scanning period.

Actually, there are three types of video signals, RGB, and each pixel in the vertical direction is one of the same color pixels of R, G, and B. Therefore, a data signal of any one of RGB is set in the data line DL.

In the apparatus of this embodiment, a dot inversion AC application method is employed. That is, in each pixel (dot) in the horizontal scanning direction, a voltage applied to the pixel electrode of the liquid crystal element 12 is applied as a data signal having a polarity opposite to that of the common electrode voltage Vcom.

Shown on the left side of FIG. 3 is a data signal having the first polarity, and a hypotenuse of a triangle written as Vvideo indicates a data signal (write voltage) corresponding to luminance. The data signal is a voltage difference (dynamic range) of Vb from the black level to the white level, and the voltage applied to the pixel electrode after the voltage shift is white when the voltage is high centered on Vcom, and is black when the voltage is low. ing. Therefore, in this example, the black level is Vcom−Vb / 2, and the white level is Vcom + Vb / 2. Further, as shown on the right side of FIG. 3, the adjacent pixels have a second polarity opposite to the first polarity, and the black level is Vcom + Vb / 2 and the white level is Vcom−Vb / 2. ing.

Then, as shown in FIG. 2, after the on period of the pixel TFT ends and data writing ends, the capacitance lines SC-A and SC-B shift by a predetermined voltage ΔVsc. In this example, a normally black vertical alignment (VA) type liquid crystal is used as the liquid crystal. A normally white TN liquid crystal can also be used. For the pixel on the left side of FIG. 3, the capacitor line SC-A is connected, and Vsc is shifted in the higher voltage direction by ΔVsc. In addition, for the pixel on the right side of FIG. 3, the capacitor line SC-B is connected, and Vsc is shifted in the lower direction by ΔVsc.

As a result, as shown in FIG. 3, the data signal applied to the pixel electrode is shifted by a voltage corresponding to ΔVsc, and this is applied between Vcom. Here, ΔVsc is set to a voltage corresponding to the threshold voltage Vath at which the change in transmittance according to the applied voltage of the liquid crystal is started, and display by the liquid crystal element 12 is possible by the shifted voltage. Become. The dynamic range of the data signal is set so that the shifted dynamic range is a voltage difference from the black level to the white level in the display.

In FIG. 3, Va (W) is the shift amount of the white level data signal, and Va (B) is the shift amount of the black level data signal, and these shift amounts are determined by ΔVsc. Vb is the voltage difference (dynamic range) between the black level and the white level of the data signal, and Vb 'is the dynamic range after the shift.

FIG. 4 shows a schematic plan configuration of the display panel. Thus, the data lines DL are arranged for each column in the column (vertical scanning) direction, and the two storage capacitor lines SC-A and SC-B are arranged in each row in the row (horizontal scanning line) direction. Yes.

In the figure, the data lines DL are linear with the same width, but this is not necessary. When the data line DL is used for light shielding between the pixels, it is preferable to increase the line width at that portion. Further, in the case of the delta type arrangement, the data line DL is necessarily bent.

In addition, the capacity lines SC-A and SC-B have a portion where the storage capacitor 14 is formed to ensure the capacity. Further, in this example, the adjacent pixel portion is also used as the storage capacitor 14. That is, by extending the semiconductor layer (the electrode on the opposite side of the storage capacitor line SC-A) forming the storage capacitor 14 in the left pixel in the figure to the adjacent pixel, a part of the adjacent pixels is also between the pixels. It is used as a storage capacitor 14. Further, as will be described later, the lower part of the data line is also used as a part of the storage capacitor 14.

Note that it is also preferable to reduce the line width only in this portion so that the area of the intersection of the data line DL and the storage capacitor lines SC-A and SC-B becomes small.

The two storage capacitor lines SC-A and SC-B have the same area crossing the data line DL. As a result, the capacitance values of the parasitic capacitances constituting the storage capacitor lines SC-A and SC-B and the data line DL become the same, and the potential of the data line DL is inverted when the storage capacitor lines SC-A and SC-B are inverted. Can be reduced, and adverse effects on the display can be reduced.

FIG. 5 shows a cross-sectional view of a portion where one storage capacitor line SC is arranged. Thus, the buffer layer 102 is provided on the glass substrate 100, and the semiconductor layer SCL is provided thereon. The semiconductor layer SCL forms the pixel TFT 10 and the like, but the illustrated portion is a portion where the storage capacitor 14 is formed. An oxide film 104 is formed on the semiconductor layer SCL. The oxide film 104 is formed by the same process as the gate oxide film of the pixel TFT 10. A storage capacitor line SC is formed on the gate oxide film 104. The storage capacitor line SC is formed by the same process as the gate electrode of the pixel TFT 10.

An interlayer insulating film 106 is formed on the storage capacitor line SC, and a data line DL is formed thereon.

Further, the planarization layer 108 is formed so as to cover the data line DL, and the pixel electrode 30 is formed thereon. Although not shown, a liquid crystal layer is provided on the pixel electrode 30 via an alignment film, and a counter substrate on which a common electrode is formed is disposed, and the liquid crystal layer is sandwiched.

Thus, the storage capacitor line SC and the data line DL are opposed to each other through the interlayer insulating film 106 at the intersection. Therefore, a capacity is generated in this portion. In this example, the semiconductor layer SCL extends below the intersecting portion, and this portion is also used as a part of the storage capacitor 14.

FIG. 6 shows the transmittance of the TN liquid crystal and the VA liquid crystal with respect to the applied voltage. In the case of TN liquid crystal, when the voltage applied to the liquid crystal is increased, the initial transmittance is a constant high level (white level), and when the voltage applied to the liquid crystal exceeds the threshold voltage, the transmittance is increased. It begins to decrease, and then the transmittance decreases at a constant rate and reaches a certain low level (black level). On the other hand, in the case of VA liquid crystal, when the voltage applied to the liquid crystal is increased, the initial transmittance is a constant low level (black level), and when the voltage applied to the liquid crystal exceeds the threshold voltage, transmission is performed. The rate begins to increase, and then the transmittance increases at a constant rate and reaches a certain high level (white level).

The TN liquid crystal and the VA liquid crystal have different voltage ranges (dynamic ranges) necessary for display, but in this embodiment, the voltage range can be adjusted by changing ΔVsc.

In the present embodiment, the SC driver 22 uses either the power supply voltage VDD or VSS used in the vertical driver 20 as the H level voltage (Vsc (H)) in the capacitor line SC (SC-A or SC-B). ) Or L level voltage (Vsc (L)). In addition to the VDD and VSS, the GND potential is also supplied to the vertical driver 20. That is, the vertical driver 20 has a shift register for driving the gate line GL, and the GND potential is used in this shift register. Therefore, the GND potential can be used for either the H level voltage (Vsc (H)) or the L level voltage (Vsc (L)). Therefore, in the SC driver 22, it is also preferable to use the potential used in the vertical driver 20 for both the H level voltage (Vsc (H)) and the L level voltage (Vsc (L)). Furthermore, other potentials can be used as long as they are potentials input to the panel. In the following description, basically, the case where VDD or VSS is used for one of the H level voltage (Vsc (H)) and the L level voltage (Vsc (L)) of the SC driver 22 will be described as an example. To do.

That is, as shown in FIG. 7, a display control signal that is at the H level during the period during which the H level is supplied to the capacitor line SC is supplied to the control terminals of the switches SW1 and SW2. Each of the switches SW1 and SW2 has a configuration in which an n-channel TFT and a p-channel TFT are connected in parallel. The gate of the p-channel TFT of the switch SW1 and the gate of the n-channel TFT of the switch SW2 are connected to each other. A signal obtained by inverting the display control signal using an inverter is supplied, and the display control signal is supplied to the gate of the n-channel TFT of the switch SW1 and the gate of the p-channel TFT of the switch SW2. For example, VDD or Vsc (H) is input to the input of the switch SW1, and Vsc (L) or VSS is input to the input of the switch SW2. The outputs of the switches SW1 and SW2 are connected to the capacity line SC-A or SC-B.

That is, the SC driver 22 needs two voltages to drive the capacitance lines SC-A and SC-B. In this embodiment, one of them is VDD or VSS used in the vertical driver 20. It is said. For example, when Vsc (L) is used for the L level, the H level is set to VDD, and when Vsc (H) is used for the H level, the L level is set to VSS. Therefore, in the display device, it is only necessary to generate either Vsc (H) or Vsc (L), and the power supply circuit can be simplified. Further, since the SC driver 22 is provided close to the vertical driver 20, the wiring for inputting VDD or VSS inputted to the vertical driver 20 to the SC driver 22 may be short.

Note that one circuit shown in FIG. 7 is provided for one capacitor line SC (SC-A or SC-B). For example, Vsc (L is set so that the difference between the H level and the L level is ΔVsc. ) Is determined for VDD or Vsc (H) is determined for VSS.

7, when the display control signal is at the H level, the switch SW1 is turned on, for example, Vsc (H) is output. When the display control signal is at the L level, the switch SW2 is turned on, for example, Vss. Is output.

Here, the structure and operation of a pixel in a VA mode display device using VA liquid crystal will be described with reference to FIGS.

8A and 8B are schematic cross sections of a VA mode liquid crystal display device (LCD) using VA liquid crystal, and an AA line of an LCD having a schematic planar structure as shown in FIG. 8C as an example. The cross-sectional structure along is shown. In this LCD, a rubbing-less type in which a rubbing treatment is not applied is usually used for the alignment film. For this reason, the initial alignment of the liquid crystal has no pretilt, and the liquid crystal molecules are aligned with the major axis direction in the normal direction of the substrate when no voltage is applied. As shown in FIGS. 8A and 8B, the liquid crystal molecules 60 initially aligned in the vertical direction have a low initial voltage when voltage is applied between the common electrode 40 and the pixel electrode 30 of the LCD. The direction in which the weak electric field generated in the state (see the electric lines of force indicated by the dotted line in the figure) is inclined obliquely at the end of the pixel electrode 30 and the liquid crystal molecules are tilted by the oblique electric field following the voltage increase. Is defined.

For example, as shown in the drawing, each of the pixel regions can be divided into different directions in a plurality of regions within one pixel region by providing an orientation dividing unit 50 as illustrated. In the example of FIG. 8, the alignment division part 50 can be configured by providing a protrusion on the electrode absence region (window) or the electrode, and both the common electrode 40 and the pixel electrode 30 are bent in the vertical direction of the screen. It is formed in a pattern extending to However, the present invention is not limited to such a pattern. For example, by providing a pattern in which the upper and lower ends in the longitudinal direction are divided into two forks in one pixel region, an electrode absence region (window) and a protrusion are provided. It may be configured. By such an alignment division unit 50, as shown in FIGS. 8A and 8B, the boundary of the liquid crystal alignment direction in one pixel can be fixed to the division unit 50, and the pixels in the direction in which the liquid crystal molecules fall down. The boundary position in the inside is different for each pixel and each driving timing, and adverse effects on display quality such as rough display are prevented.

In the present embodiment, a transmissive LCD that displays only with light from a light source arranged behind the panel and adopts a transparent conductive electrode such as ITO for both the pixel electrode and the common electrode is reflected as a pixel electrode. Reflective LCD that displays light by reflecting light from outside light using metal electrodes. Furthermore, it is used in any type of transflective LCD that functions as a transmissive mode when a light source is used and as a reflective mode when the light source is turned off. Is possible. Reflective LCDs, transflective LCDs, and the like are required to further improve contrast, but by performing polarity inversion as in this embodiment, for example, in reflective or transflective LCDs in ECB mode. Display with sufficiently high contrast.

It is a figure which shows the structure of embodiment. It is a figure which shows the signal waveform of capacitive line SC-A, SC-B. It is a figure which shows the state of the shift of a voltage. It is a figure which shows the planar structure of a pixel circuit. It is a figure which shows the cross-sectional structure of a pixel circuit. It is a figure which shows the transmittance | permeability change of TN liquid crystal and VA liquid crystal. It is a figure which shows the structure of SC driver. It is a figure which shows the structure and operation | movement of a pixel of VA mode.

Explanation of symbols

1 pixel circuit, 12 liquid crystal element, 14 holding capacitor, 20 vertical driver, 22 driver, 30 pixel electrode, 40 common electrode, 50 alignment division part, 60 liquid crystal molecule, DL data line, GL gate line, SC capacitor line, SW1, SW2 switch.

Claims

A display device in which pixel circuits are arranged in a matrix,
Each pixel circuit
A pixel TFT having one end connected to a data line to which a data signal is supplied, a gate connected to a selection line, and being turned on / off by setting a selection signal of the selection line to H level or L level;
A storage capacitor electrode connected to the other end of the pixel TFT, the storage capacitor electrode is thus formed on the opposing storage capacitor line, a storage capacitor for holding a voltage of the data signal supplied from the data line,
A liquid crystal element in which one electrode is connected to the other end of the pixel TFT and the other electrode is held at a common power supply potential;
With
The storage capacitor line turns on the pixel TFT and writes a data signal on the data line to the storage capacitor, and then changes from the first level to the second level, thereby applying a voltage applied to the liquid crystal element. Shift,
Two storage capacitor lines are provided corresponding to the row of each pixel circuit, and the plurality of pixel circuits arranged in the row direction are connected to one of the two storage capacitor lines, Each of the two storage capacitor lines has an H level potential and an L level potential,
Capacitance values generated at the intersections of the two storage capacitor lines and the data lines are set to be substantially the same ,
The storage capacitor line forming the storage capacitor in the pixel region corresponding to the pixel TFT has a line width larger than a line width of a portion where the storage capacitor line intersects the data line,
A portion of the storage capacitor line having a large line width extends to a data line connected to an adjacent pixel, forms the storage capacitor electrode and a storage capacitor, and
A crossing portion of the storage capacitor line that crosses the data line is formed by extending the storage capacitor electrode to the crossing portion, thereby forming the storage capacitor also in the crossing portion. Display device.
The display device according to claim 1,
The display device according to claim 1, wherein when the potential of one of the two types is shifted from positive to negative, or from negative to positive, the other potential is shifted in the opposite direction.