JP4636827B2 - Circuit module - Google Patents
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- JP4636827B2 JP4636827B2 JP2004222820A JP2004222820A JP4636827B2 JP 4636827 B2 JP4636827 B2 JP 4636827B2 JP 2004222820 A JP2004222820 A JP 2004222820A JP 2004222820 A JP2004222820 A JP 2004222820A JP 4636827 B2 JP4636827 B2 JP 4636827B2
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- mounting substrate
- wiring layer
- fixing hole
- fixing plate
- circuit module
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15162—Top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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Description
本発明は回路モジュールおよび電子機器に関し、特に、基板の固定に用いられる固定孔を具備する回路モジュールおよび電子機器に関する。 The present invention relates to a circuit module and an electronic apparatus, and more particularly to a circuit module and an electronic apparatus having a fixing hole used for fixing a substrate.
電子機器の小型化および高機能化に伴い、その内部に収納される実装基板においては、多層配線構造が主流になっている。図６を参照して、多層配線基板の製造方法の一例を説明する（下記特許文献１を参照）。 Along with the downsizing and higher functionality of electronic devices, multilayer wiring structures have become mainstream in mounting boards housed therein. An example of a method for manufacturing a multilayer wiring board will be described with reference to FIG. 6 (see Patent Document 1 below).
先ず、図６（Ａ）を参照して、樹脂等の絶縁性の材料から成る基材１００の表面および裏面に第1の銅箔１０１Ａおよび第２の銅箔１０１Ｂを密着させる。 First, referring to FIG. 6A, first copper foil 101A and second copper foil 101B are brought into close contact with the front and back surfaces of base material 100 made of an insulating material such as resin.
次に、図６（Ｂ）を参照して、第1の銅箔１０１Ａおよび第２の銅箔１０１Ｂの選択的なエッチングを行うことにより、第1の配線層１０２Ａおよび第２の配線層１０２Ｂを形成する。更に、絶縁層１０３Ａを介して配線層を積層させ、図６（Ｃ）に示すような、多層の配線構造を実現する。ここで、接続部１０４は、各配線層同士を電気的に接続するための部位である。そして、半導体素子等の回路素子が実装基板の表面に実装されることにより、回路モジュールが完成する。
Next, referring to FIG. 6B, by selectively etching the first copper foil 101A and the second copper foil 101B, the first wiring layer 102A and the second wiring layer 102B are formed. Form. Further, a wiring layer is stacked with the
図６（Ｄ）を参照して、実装基板１０５の接続構造を説明する。実装基板１０５には、段差が設けられた貫通孔１０６が形成されている。そして、ビス１０７の押圧力により、実装基板１０５は固定される。貫通孔１０６には段差が設けられ、円柱状の溝として設けられているので、ビス１０７のヘッドは、貫通孔１０６に収納させる。
しかしながら、電子機器の薄型化のために実装基板自体も薄型化が行われており、その厚さは、０．５ｍｍ程度に成る場合がある。このような場合に、実装基板１０５が薄いために、従来例のような段差を有する貫通孔１０６を形成することが困難であった。従って、ビスのヘッドが厚み方向に突出してしまう問題等が発生していた。 However, in order to reduce the thickness of electronic devices, the mounting substrate itself is also reduced in thickness, and the thickness may be about 0.5 mm. In such a case, since the mounting substrate 105 is thin, it is difficult to form the through hole 106 having a step as in the conventional example. Therefore, there has been a problem that the screw head protrudes in the thickness direction.
更にまた、貫通孔１０６を実装基板１０５の周辺部に配置すると、貫通孔１０６付近の実装基板１０５の機械的強度が弱くなる。従って、ビスの押圧力により、貫通孔１０６の周辺部の実装基板１０５にひび割れが発生していた。 Furthermore, when the through hole 106 is disposed in the peripheral portion of the mounting substrate 105, the mechanical strength of the mounting substrate 105 in the vicinity of the through hole 106 is weakened. Therefore, cracks occurred in the mounting substrate 105 around the through hole 106 due to the pressing force of the screws.
このひびが発生すると、その周囲の実装基板自体が小片のごみとなる場合が有る。またガラス繊維が入った実装基板では、ひびの界面からガラス繊維が露出し、そのガラス繊維がごみとして落下する。これらのごみは、実装基板を装着するセット、シャーシー等の中で点在することになり、不良の原因となる。 When this crack occurs, the surrounding mounting substrate itself may become small pieces of dust. In the mounting substrate containing glass fiber, the glass fiber is exposed from the interface of the crack, and the glass fiber falls as dust. These dusts are scattered in a set, chassis or the like on which the mounting board is mounted, and cause defects.
またこのひびにより、固定板を実装する場合の平坦度が出なくなり、ビス止め作業等において、作業性を悪化させる場合がある。 In addition, the cracks do not provide flatness when the fixing plate is mounted, and workability may be deteriorated in screwing work or the like.
本発明は上述した問題点を鑑みて成されたものであり、本発明の主な目的は、貫通孔が設けられる箇所の実装基板の機械的強度が確保された回路モジュールおよび電子機器を提供することにある。 The present invention has been made in view of the above-described problems, and a main object of the present invention is to provide a circuit module and an electronic apparatus in which the mechanical strength of a mounting board at a place where a through hole is provided is ensured. There is.
本発明の回路モジュールは、一主面に配線層が露出する実装基板と、前記配線層に電気的に接続された回路素子と、前記実装基板を厚み方向に貫通して設けられた固定孔とを具備し、前記固定孔を、前記実装基板の外周端部と連続して形成することを特徴とする。 The circuit module according to the present invention includes a mounting board with a wiring layer exposed on one main surface, a circuit element electrically connected to the wiring layer, and a fixing hole provided through the mounting board in the thickness direction. And the fixing hole is formed continuously with an outer peripheral end portion of the mounting substrate.
更に本発明の回路モジュールは、少なくとも１層の配線層を有する実装基板と、前記実装基板側辺の近傍に設けられ、前記側辺と連続して開口された固定孔と、前記固定孔の周囲にＣ状に露出した前記配線層に、接着手段を介して固着された固定板と、前記配線層に電気的に接続された回路素子とを有することを特徴とする。 Furthermore, the circuit module of the present invention includes a mounting board having at least one wiring layer, a fixing hole provided in the vicinity of the side of the mounting board and continuously open to the side, and a periphery of the fixing hole. And a circuit board electrically connected to the wiring layer, and a fixing plate fixed to the wiring layer exposed in a C shape via an adhesive means.
本発明の電子機器は、筐体と、前記筐体に内蔵される回路モジュールを具備し、前記回路モジュールは、少なくとも１層の配線層を有する実装基板と、前記実装基板側辺の近傍に設けられ、前記側辺と連続して開口された固定孔と、前記固定孔の周囲にＣ状に露出した前記配線層に、接着手段を介して固着された固定板と、前記配線層に電気的に接続された回路素子とを有し、前記回路モジュールは、前記固定板に当接するビスを介して、前記筐体の内壁に固定されることを特徴とする。 The electronic device of the present invention includes a housing and a circuit module built in the housing, and the circuit module is provided in the vicinity of the mounting substrate having at least one wiring layer and the side of the mounting substrate. A fixing hole opened continuously to the side, a fixing plate fixed to the wiring layer exposed in a C shape around the fixing hole via an adhesive means, and an electrical connection to the wiring layer And the circuit module is fixed to the inner wall of the casing through a screw abutting against the fixing plate.
本発明の回路モジュールおよび電子機器に依れば、実装基板を厚み方向に貫通する固定孔を、実装基板の外周端部と連続して形成している。即ち、外周端部と固定孔との間に位置する部分の実装基板を切除している。従って、実装基板の周辺部に固定孔を設けた場合でも、実装基板の部分的な機械的強度の低下が抑止されている。このことから、固定孔がビスにより固定された場合でも、ビスの押圧力による実装基板のひび割れを抑止することができる。 According to the circuit module and the electronic device of the present invention, the fixing hole penetrating the mounting substrate in the thickness direction is formed continuously with the outer peripheral end portion of the mounting substrate. That is, the part of the mounting substrate located between the outer peripheral end and the fixing hole is cut off. Therefore, even when a fixing hole is provided in the peripheral portion of the mounting substrate, a partial reduction in mechanical strength of the mounting substrate is suppressed. For this reason, even when the fixing hole is fixed with a screw, it is possible to suppress cracking of the mounting substrate due to the pressing force of the screw.
回路モジュール１の構成を説明する。図１（Ａ）は回路モジュール１の平面図であり、図１（Ｂ）はその断面図である。 The configuration of the circuit module 1 will be described. 1A is a plan view of the circuit module 1, and FIG. 1B is a cross-sectional view thereof.
実装基板２は、セットの形状により色々な形に加工されるが、ここでは矩形の形状で説明する。実装基板２の表面には半導体素子３Ａ等の回路素子が固着されている。実装基板２は、多層の配線構造がその内部に構成され、ここでは一例として４層の配線層から成る多層配線構造が形成されている。具体的には、下層から、第１の配線層１８Ａ、第２の配線層１８Ｂ、第３の配線層１８Ｃ、第４の配線層１８Ｄから成る４層の配線層が構成されている。そしてこれらの配線層１８は、第１の絶縁膜１２Ａ、第２の絶縁膜１２Ｂ、第３の絶縁膜１２Ｃを介して積層されている。更に、各配線層１８は、所望の箇所にて絶縁膜１２を貫通して電気的に接続されている。ここで、実装基板２に形成される配線層の数は、４層以外でも良く、例えば１層や２層等でも良い。更に、５層以上の多層配線でも良い。実装基板２の厚みは、例えば５００μｍ程度である。尚、実装基板２の平面的な形状は、回路モジュール１が内蔵される精密機器により、矩形以外の複雑な形状でも良い。 The mounting substrate 2 is processed into various shapes depending on the shape of the set. Here, the mounting substrate 2 will be described as a rectangular shape. Circuit elements such as the semiconductor element 3A are fixed to the surface of the mounting substrate 2. The mounting substrate 2 has a multilayer wiring structure formed therein, and here, as an example, a multilayer wiring structure including four wiring layers is formed. Specifically, four wiring layers including a first wiring layer 18A, a second wiring layer 18B, a third wiring layer 18C, and a fourth wiring layer 18D are formed from the lower layer. These wiring layers 18 are stacked via the first insulating film 12A, the second insulating film 12B, and the third insulating film 12C. Furthermore, each wiring layer 18 penetrates the insulating film 12 at a desired location and is electrically connected. Here, the number of wiring layers formed on the mounting substrate 2 may be other than four layers, for example, one layer or two layers. Furthermore, it may be a multilayer wiring of five or more layers. The thickness of the mounting substrate 2 is, for example, about 500 μm. The planar shape of the mounting substrate 2 may be a complicated shape other than a rectangle depending on the precision device in which the circuit module 1 is built.
実装基板２の表面には、複数個の回路素子が実装されている。ここでは、回路素子として半導体素子３Ａ、３Ｅ、チップ素子３Ｂ、３Ｃが、実装基板２の表面に電気的に接続されて固着されている。これらの回路素子３は、実装基板２の表面から露出する配線層に電気的に固着されている。また、これらの回路素子を、実装基板２の裏面に固着しても良い。 A plurality of circuit elements are mounted on the surface of the mounting substrate 2. Here, the semiconductor elements 3A and 3E and the chip elements 3B and 3C are electrically connected and fixed to the surface of the mounting substrate 2 as circuit elements. These circuit elements 3 are electrically fixed to the wiring layer exposed from the surface of the mounting substrate 2. Further, these circuit elements may be fixed to the back surface of the mounting substrate 2.
半導体素子３Ａは例えば、トランジスタ、ダイオード、ＩＣチップ等である。ここではＩＣチップが、フェイスダウンの状態で実装基板２の表面に配置されている。フェイスダウンで実装される半導体素子３Ａには、アンダーフィルが下面に設けられる。 The semiconductor element 3A is, for example, a transistor, a diode, an IC chip, or the like. Here, the IC chip is arranged on the surface of the mounting substrate 2 in a face-down state. An underfill is provided on the lower surface of the semiconductor element 3A mounted face down.
チップ素子３Ｂは、例えば、チップコンデンサ、チップ抵抗、インダクタ、コイルまたはセンサ等である。これらのチップ素子３Ｂは、半田または導電ペーストを介して、実装基板２から露出する配線層に電気的に接続されている。また、比較的小型のチップ素子３Ｃは、複数個が密集されて実装基板２上に固着されている。 The chip element 3B is, for example, a chip capacitor, a chip resistor, an inductor, a coil, or a sensor. These chip elements 3B are electrically connected to the wiring layer exposed from the mounting substrate 2 via solder or conductive paste. Further, a plurality of relatively small chip elements 3 </ b> C are closely packed and fixed on the mounting substrate 2.
外部端子５は、部分的に露出する配線層１８から成り、電気信号の入出力を行う部位である。また、実装基板２の表面および裏面の両面に、外部端子５を形成することも可能である。 The external terminal 5 is composed of a partly exposed wiring layer 18 and is a part for inputting and outputting electrical signals. It is also possible to form the external terminals 5 on both the front and back surfaces of the mounting substrate 2.
第１および第２の固定板４Ａ、４Ｂは、中央部に円形のビス孔が設けられた円盤状の金属板である。これらの固定板は、実装基板２に穿設された固定孔９を被覆するように、実装基板２に固着されている。ここでは、第１の固定板４Ａが実装基板２の角部(または側辺)付近（紙面上では右上）に固着されている。第２の固定板４Ｂは、第１の固定板４Ａに対向する角部付近（紙面上では左下）の実装基板２に固着されている。ここで、固定板４を、実装基板２の各角部付近に４つ配置しても良い。このことにより、回路モジュール１の実装をより安定して行うことができる。また固定板４の形状は、矩形等の円形以外の形状でも良い。 The first and second fixing plates 4A and 4B are disk-shaped metal plates each having a circular screw hole at the center. These fixing plates are fixed to the mounting substrate 2 so as to cover the fixing holes 9 formed in the mounting substrate 2. Here, the first fixing plate 4A is fixed near the corner (or side) of the mounting substrate 2 (upper right on the paper surface). The second fixing plate 4B is fixed to the mounting substrate 2 in the vicinity of the corner facing the first fixing plate 4A (lower left on the paper surface). Here, four fixing plates 4 may be disposed near each corner of the mounting substrate 2. Thereby, the circuit module 1 can be mounted more stably. Further, the shape of the fixed plate 4 may be a shape other than a circle such as a rectangle.
図２を参照して、実装基板２の構造を説明する。図２（Ａ）は、半導体素子３Ａ等の回路素子３を除外した状態の実装基板２の状態を示している。図２（Ｂ）は、第１の固定孔９Ａが設けられる付近の実装基板２の拡大図である。 The structure of the mounting substrate 2 will be described with reference to FIG. FIG. 2A shows a state of the mounting substrate 2 in a state where the circuit element 3 such as the semiconductor element 3A is excluded. FIG. 2B is an enlarged view of the mounting board 2 in the vicinity where the first fixing hole 9A is provided.
図２（Ａ）を参照して、実装基板２の表面には、最上層の配線層である第４の配線層１８Ｄが部分的に露出してパッドを構成している。具体的には、回路素子３の実装を行うためのパッドが、露出する第４の配線層１８Ｄにより形成されている。また、略円形に形成される固定孔９を囲むように、第４の配線層１８Ｄが実装基板２の表面に露出している。 Referring to FIG. 2A, a fourth wiring layer 18D, which is the uppermost wiring layer, is partially exposed on the surface of mounting substrate 2 to form a pad. Specifically, a pad for mounting the circuit element 3 is formed by the exposed fourth wiring layer 18D. Further, the fourth wiring layer 18 </ b> D is exposed on the surface of the mounting substrate 2 so as to surround the fixing hole 9 formed in a substantially circular shape.
第１の固定孔９Ａは、図２の如く、実装基板２を厚み方向に貫通して設けた孔であり、実装基板２の周辺部に設けられている。紙面上では、第１の固定孔９Ａは、実装基板２の上側の周辺部に形成されている。更に、第１の固定孔９Ａは、実装基板２の側辺の近傍に配置される。そして、第１の固定孔９Ａの内側と実装基板２の外周部が連続して形成されている。即ち、第１の固定孔９Ａの平面的な形状は、「ＣまたはΩ」の如き形状と成っている。 As shown in FIG. 2 , the first fixing hole 9 </ b > A is a hole that penetrates the mounting substrate 2 in the thickness direction, and is provided in the peripheral portion of the mounting substrate 2. On the paper surface, the first fixing hole 9 </ b> A is formed in the upper peripheral portion of the mounting substrate 2. Further, the first fixing hole 9 </ b> A is disposed in the vicinity of the side of the mounting substrate 2. The inside of the first fixing hole 9A and the outer peripheral portion of the mounting substrate 2 are formed continuously. That is, the planar shape of the first fixing hole 9A is a shape such as “C or Ω”.
第２の固定孔９Ｂは、紙面上では、実装基板２の下側の周辺部に形成されている。また、第２の固定孔９Ｂは、閉じた円形に成っている。更に、第２の固定孔９Ｂを囲むように、第４の配線層１８Ｄが、円形に露出している。ここで、第２の固定孔９Ｂと、実装基板２の外周部との距離Ｄ１は、例えば０．５ｍｍ程度である。両者の距離がこの程度であれば、実装基板２の局所的な機械的強度の低下を抑止しでき、切除領域Ａ１を設けずに固定孔を形成することができる。 The second fixing hole 9B is formed in the lower peripheral portion of the mounting substrate 2 on the paper surface. The second fixing hole 9B has a closed circular shape. Further, the fourth wiring layer 18D is exposed in a circle so as to surround the second fixing hole 9B. Here, the distance D1 between the second fixing hole 9B and the outer peripheral portion of the mounting substrate 2 is, for example, about 0.5 mm. If the distance between the two is about this level, a decrease in local mechanical strength of the mounting substrate 2 can be suppressed, and the fixing hole can be formed without providing the cut region A1.
ここで図２Ａでは、実装される回路素子の電極が図示されているが、当然、配線等、通常の多層基板と同様に、色々なパターンが形成される。つまりリング状の第４の配線層１８Ｄは、この最表面の導電パターンと同一材料で、同時に形成される。 Here, in FIG. 2A, the electrodes of the circuit elements to be mounted are shown, but naturally, various patterns such as wirings are formed as in a normal multilayer substrate. That is, the ring-shaped fourth wiring layer 18D is formed simultaneously with the same material as the conductive pattern on the outermost surface.
図２（Ｂ）を参照して、第１の固定孔９Ａを詳述する。上述したように、第１の固定孔９Ａは、実装基板２の外周端部と連続して形成されている。換言すると、実装基板２の、第１の固定孔９Ａと外周端部に挟まれる部分を切除している。つまり、リング状のパターンを仮に配置したと考えると、第４の配線層１８Ｄは、実装基板２と近接した領域を所定の幅で切除した如き形状である。ここでは、切除される領域をＡ１としている。このように、機械的強度が弱い領域Ａ１を予め切除することにより、使用状況下にてこの領域Ａ１が破損することを防止することができる。 With reference to FIG. 2B, the first fixing hole 9A will be described in detail. As described above, the first fixing hole 9 </ b> A is formed continuously with the outer peripheral end portion of the mounting substrate 2. In other words, the portion of the mounting substrate 2 that is sandwiched between the first fixing hole 9A and the outer peripheral end is cut out. In other words, assuming that a ring-shaped pattern is arranged, the fourth wiring layer 18D has a shape such that a region close to the mounting substrate 2 is cut out with a predetermined width. Here, the region to be excised is A1. In this way, by previously cutting out the region A1 having a low mechanical strength, it is possible to prevent the region A1 from being damaged under use conditions.
また実装されるセットの精密度により不良を防止するために以下の対策を施しても良い。つまり実装基板２の絶縁材料に、ガラス繊維やフィラーが入っている場合は、この部分には、ビスが挿入されるため、少なくともこの切除領域Ａ１の側面、またはこの切除領域Ａ１と固定孔の内側側面を絶縁樹脂等でカバーし、ガラス繊維やフィラーが取れないような工夫が必要になる。また必要によっては、実装基板２のカット面全域を被覆しても良い。 Further, the following measures may be taken in order to prevent defects depending on the precision of the mounted set. That is, when glass fiber or filler is contained in the insulating material of the mounting substrate 2, since screws are inserted into this portion, at least the side surface of the cut region A1 or the inside of the cut region A1 and the fixing hole It is necessary to cover the side with an insulating resin or the like so that glass fibers and fillers cannot be removed. If necessary, the entire cut surface of the mounting substrate 2 may be covered.
図３を参照して、第１の固定孔９Ａと第１の固定板４Ａとの接続構造を説明する。 A connection structure between the first fixing hole 9A and the first fixing plate 4A will be described with reference to FIG.
図３（Ａ）を参照して、固定板４は、円盤状の金属から成り、ビス孔４Ｃと固定孔９とが重畳するように、半田６を介して実装基板２に固着されている。具体的には、第４の配線層１８Ｄが、固定孔９を囲むように、実装基板２の下面に露出している。そして、露出する部分の第４の配線層１８Ｄに、第１の固定板４Ａが接着されることで、第１の固定板４Ａが実装基板２に固着される。導電性の接着剤を介して第１の固定板４Ａが実装基板２に固着されることから、第１の固定板４Ａは電気的に実装基板２に接続される。また、第１の固定板４Ａは、半導体素子等の他の回路素子と共に、実装基板２の表面に固着されている。従って、第１の固定板４Ａを含む全ての部品をリフロー工程にて、一括して実装基板2の表面に固着することが可能となる。 Referring to FIG. 3A, the fixing plate 4 is made of a disk-shaped metal, and is fixed to the mounting substrate 2 via the solder 6 so that the screw holes 4C and the fixing holes 9 overlap each other. Specifically, the fourth wiring layer 18 </ b> D is exposed on the lower surface of the mounting substrate 2 so as to surround the fixing hole 9. Then, the first fixing plate 4A is adhered to the mounting substrate 2 by bonding the first fixing plate 4A to the exposed fourth wiring layer 18D. Since the first fixing plate 4A is fixed to the mounting substrate 2 via the conductive adhesive, the first fixing plate 4A is electrically connected to the mounting substrate 2. The first fixing plate 4A is fixed to the surface of the mounting substrate 2 together with other circuit elements such as semiconductor elements. Therefore, all components including the first fixing plate 4A can be fixed to the surface of the mounting substrate 2 at a time in the reflow process.
固定板４の材料としては薄い金属が好ましい。具体的には、固定板４の厚みは１００μｍから１５０μｍ程度とすることができる。このように、薄い金属から固定板４を形成することにより、ビスの押圧力が固定板４に作用した場合でも、固定板４自体が変形することで応力を吸収することができる。従って、ビスの押圧力による実装基板２の損傷を防止することができる。 A thin metal is preferable as the material of the fixing plate 4. Specifically, the thickness of the fixing plate 4 can be about 100 μm to 150 μm. Thus, by forming the fixing plate 4 from a thin metal, even when the pressing force of the screw acts on the fixing plate 4, the stress can be absorbed by the deformation of the fixing plate 4 itself. Therefore, the mounting substrate 2 can be prevented from being damaged by the pressing force of the screws.
更に、固定板４の材料としては、ニッケルを少なくとも表面に有する金属が好適である。その理由は、ニッケルは錆びにくく、ろう材に対して濡れ性があるからである。具体的には、固定板４としては、表面にニッケルのメッキ膜が形成されたＣｕやＦｅから成る金属板、ニッケルから成る金属板が採用される。ＡｕやＡｇでも良いが、メッキ膜を形成するコストを考慮すると、固定板４としてはニッケルから成る金属板を採用することが好ましい。尚、ニッケルを固定板４の材料として採用する場合は、還元処理されたニッケルを使用することが好ましい。還元処理とは、ニッケルの表面に水素ガス等を吹き付けながら加熱する処理である。この処理を行うことにより、ニッケルの表面が錆びるのを防止することが可能となる。また、固定板４の材料として、アルミニウムを採用することも可能である。 Further, the material of the fixing plate 4 is preferably a metal having nickel at least on the surface. The reason is that nickel is not easily rusted and has wettability to the brazing material. Specifically, a metal plate made of Cu or Fe having a nickel plating film formed on the surface or a metal plate made of nickel is employed as the fixed plate 4. Although Au or Ag may be used, it is preferable to adopt a metal plate made of nickel as the fixing plate 4 in consideration of the cost of forming the plating film. When nickel is used as the material of the fixing plate 4, it is preferable to use reduced nickel. The reduction process is a process of heating while blowing hydrogen gas or the like on the surface of nickel. By performing this treatment, it is possible to prevent the nickel surface from rusting. Further, aluminum can be used as the material of the fixing plate 4.
例えば、駆動部やセンサ部を有する精密機器等のセットでは、酸化物等のパーティクル等がその内部で発生した場合、不具合が起きる。アルミニウムは、その表面に酸化アルミニウム（アルマイト）が形成される。この酸化物は、緻密でアルミニウムに密着しているため、ごみの発生が無い。一方、本形態の固定板４は、防錆性に優れた材料であることから、上記した精密機器の筐体内部への適用が可能である。 For example, in a set of precision instruments having a drive unit and a sensor unit, a problem occurs when particles such as oxides are generated inside the set. Aluminum has aluminum oxide (alumite) formed on its surface. Since this oxide is dense and in close contact with aluminum, there is no generation of dust. On the other hand, since the fixing plate 4 of this embodiment is a material excellent in rust prevention, it can be applied to the inside of the casing of the precision instrument described above.
図３（Ｂ）を参照して、第１の固定孔９Ａを覆うように、第１の固定板４Ａが実装基板２に固着されている。第１の固定孔９Ａは、実装基板２の外周部と連続して形成されているので、閉じた円形と成っていない。従って、固定用のビスを第１の固定孔９Ａに直に固着するのは困難である。そこで、本形態では、円盤状の第１の固定板４Ａを、第１の固定孔９Ａを覆うように実装基板２に固着している。そして、固定を行うビスは、第１の固定板４Ａに当接する。このことにより、第１の固定板４Ａを介して、実装基板２を固定することができる。また、切断線Ｌ１の箇所にて、第１の固定板４Ａを切断しても良い。このことにより、実装基板２の外周端部から突出する部分の、第１の固定板４Ａが除去される。 Referring to FIG. 3B, first fixing plate 4A is fixed to mounting substrate 2 so as to cover first fixing hole 9A. Since the first fixing hole 9A is formed continuously with the outer peripheral portion of the mounting substrate 2, it does not form a closed circle. Therefore, it is difficult to fix the fixing screw directly to the first fixing hole 9A. Therefore, in this embodiment, the disk-shaped first fixing plate 4A is fixed to the mounting substrate 2 so as to cover the first fixing hole 9A. And the screw which fixes is contact | abutted to 4 A of 1st fixing plates. As a result, the mounting substrate 2 can be fixed via the first fixing plate 4A. Further, the first fixing plate 4A may be cut at the position of the cutting line L1. As a result, the portion of the first fixing plate 4A protruding from the outer peripheral end of the mounting substrate 2 is removed.
図４（Ａ）の断面図を参照して、固定板４は、固定孔９を覆うように実装基板２に固着されている。そして、ビス孔４Ｃを貫通するビス８Ａが、固定板９を押圧ねじ止めすることにより、実装基板２が固定されている。 With reference to the cross-sectional view of FIG. 4A, the fixing plate 4 is fixed to the mounting substrate 2 so as to cover the fixing hole 9. The mounting board 2 is fixed by screwing the fixing plate 9 with screws 8A that penetrate the screw holes 4C.
ビス８Ａは、ヘッド８Ｂの下部が固定板４を押圧することで、回路モジュール１を固定する機能を有する。また、ビスのヘッド８Ｂは、固定孔９の内部から固定板４に直に当接している。従って、固定板４を介して、ビス８Ａと第１の配線層１８Ａとは電気的に接続されている。即ち、本形態の回路モジュール１では、固定板４を外部端子の一つとして用いることができる。一例として、固定板４およびビス８Ａを介して、第１の配線層１８Ａを接地電位に接続することもできる。更に、ヘッド８Ｂは、実装基板２に設けた固定孔９に収納されている。従って、ヘッド８Ｂは、実装基板２の厚み部分に収納される。 The screw 8A has a function of fixing the circuit module 1 when the lower portion of the head 8B presses the fixing plate 4. The screw head 8B is in direct contact with the fixing plate 4 from the inside of the fixing hole 9. Accordingly, the screw 8A and the first wiring layer 18A are electrically connected via the fixing plate 4. That is, in the circuit module 1 of this embodiment, the fixing plate 4 can be used as one of the external terminals. As an example, the first wiring layer 18A can be connected to the ground potential via the fixing plate 4 and the screw 8A. Further, the head 8 </ b> B is accommodated in a fixing hole 9 provided in the mounting substrate 2. Therefore, the head 8 </ b> B is housed in the thickness portion of the mounting substrate 2.
図４（Ｂ）は、固定孔９が形成される箇所の平面拡大図である。この図を参照して、固定孔９、ビスのヘッド８Ｂおよびビス孔４Ｃは円形の平面的形状となっている。そして、これら３つの構成要素は、同心円の如き関連構成となっている。これらの大小関係は、固定孔９＞ヘッド８Ｂ＞ビス孔４Ｃの順番で大きく形成される。固定孔９がビスのヘッド８Ｂよりも大きく形成されることにより、ヘッド８Ｂを固定孔に収納させることができる。更に、ビスのヘッド８Ｂがビス孔４Ｃよりも大きく形成されることにより、ヘッド８Ｂにて、固定板４を押圧することができる。また、ビスのヘッド８Ｂには、ドライバーの先端部が嵌合するための凹部が形成されており、この凹部を介してビスを回転させることで、実装基板２の固定が行われる。 FIG. 4B is an enlarged plan view of a portion where the fixing hole 9 is formed. Referring to this figure, the fixing hole 9, the screw head 8B and the screw hole 4C have a circular planar shape. These three components have a related configuration such as a concentric circle. These magnitude relationships are formed in the order of fixing hole 9> head 8B> screw hole 4C. By forming the fixing hole 9 larger than the screw head 8B, the head 8B can be accommodated in the fixing hole. Furthermore, since the screw head 8B is formed larger than the screw hole 4C, the fixing plate 4 can be pressed by the head 8B. The screw head 8B is formed with a recess for fitting the tip of the driver, and the mounting substrate 2 is fixed by rotating the screw through the recess.
また図面では示していないが、本願の実装基板は放熱手段として有効である。例えば半導体チップの実装面として第４の配線層１８Ｄを形成し、これが第３、第２および第１の配線層と電気的に接続されていれば、半導体チップで発生した熱が固定板４に伝わり、この固定板４が精密機器の金属部分、例えばシャーシーの内側に接続されれば、そのまま放熱させることができる。近年、小型で高密度の精密機器があるが、このように固定板４を介せば、放熱でき、その分駆動能力を向上させることができる。 Although not shown in the drawings, the mounting board of the present application is effective as a heat dissipation means. For example, if the fourth wiring layer 18D is formed as the mounting surface of the semiconductor chip and is electrically connected to the third, second and first wiring layers, the heat generated in the semiconductor chip is applied to the fixing plate 4. If this fixing plate 4 is connected to a metal part of a precision instrument, for example, the inside of the chassis, it can be radiated as it is. In recent years, there is a small and high-density precision instrument, but heat can be dissipated through the fixing plate 4 in this way, and the driving ability can be improved accordingly.
次に図５の断面図を参照して、回路モジュール１の実装構成を説明する。 Next, the mounting configuration of the circuit module 1 will be described with reference to the cross-sectional view of FIG.
ここでは、回路モジュール１が基板２０に固定されている。具体的には、基板２０の凸部２１に埋め込まれるビス８Ａのねじ作用により、回路モジュール１が基板２０に固定されている。 Here, the circuit module 1 is fixed to the substrate 20. Specifically, the circuit module 1 is fixed to the substrate 20 by the screw action of the screws 8 </ b> A embedded in the convex portions 21 of the substrate 20.
実装基板２は、ここでは、第１の配線層１８Ａおよび第２の配線層１８Ｂから成る２層の配線層が形成されている。更に、実装基板２の表面および裏面の両面に、半導体素子３Ａ等の回路素子が固着されている。このように、実装基板２の両面に回路素子を固着することにより、回路モジュール１の実装密度を向上させることができる。 Here, the mounting substrate 2 is formed with two wiring layers including a first wiring layer 18A and a second wiring layer 18B. Furthermore, circuit elements such as the semiconductor element 3 </ b> A are fixed to both the front and back surfaces of the mounting substrate 2. Thus, the mounting density of the circuit modules 1 can be improved by fixing the circuit elements to both surfaces of the mounting substrate 2.
回路装置１０は、複数の素子が樹脂封止されたパッケージである。具体的には、半導体素子１１および受動素子１４が回路装置１０に内蔵されている。また、複数の素子により１つのシステムが内部に構築されたＳＩＰ（System In Package）を回路装置１０として採用することができる。このように、複数の素子がパッケージ化された回路装置１０を実装させることにより、実装基板２への回路素子の実装を簡略化することができる。更に、全ての回路素子を、リフロー工程にて面実装を行うことができる。 The circuit device 10 is a package in which a plurality of elements are sealed with resin. Specifically, the semiconductor element 11 and the passive element 14 are built in the circuit device 10. Further, a SIP (System In Package) in which one system is constructed by a plurality of elements can be adopted as the circuit device 10. As described above, by mounting the circuit device 10 in which a plurality of elements are packaged, the mounting of the circuit elements on the mounting substrate 2 can be simplified. Furthermore, all circuit elements can be surface-mounted in a reflow process.
上記した回路モジュール１の実装構造により、半導体素子３Ａ等の回路素子の接続信頼性を向上させることが可能となる。具体的には、回路モジュール１が実装される基板２０と、半導体素子３Ａ等の回路素子とは熱膨張係数が大きく異なる。例えば、基板２０としてアルミニウムを採用した場合は、その熱膨張係数は２３×１０−６／℃である。それに対して、半導体素子３Ａの熱膨張係数は、２．６×１０−６／℃である。従って、基板２０に直に半導体素子３Ａを固着した場合は、大きな熱応力が発生することから、半導体素子３Ａの接続信頼性は確保できない。そこで、本形態では、柔軟性を有する実装基板２に半導体素子３Ａ等の回路素子を固着して、この実装基板２を基板２０に固定している。このことにより、実装基板２により熱応力が緩衝されるので、半導体素子３Ａ等の回路素子の接続信頼性を確保することができる。 The mounting structure of the circuit module 1 described above makes it possible to improve the connection reliability of circuit elements such as the semiconductor element 3A. Specifically, the substrate 20 on which the circuit module 1 is mounted and the circuit element such as the semiconductor element 3A have greatly different thermal expansion coefficients. For example, when aluminum is adopted as the substrate 20, the coefficient of thermal expansion is 23 × 10 −6 / ° C. On the other hand, the thermal expansion coefficient of the semiconductor element 3A is 2.6 × 10 −6 / ° C. Therefore, when the semiconductor element 3A is fixed directly to the substrate 20, a large thermal stress is generated, so that the connection reliability of the semiconductor element 3A cannot be ensured. Therefore, in this embodiment, a circuit element such as the semiconductor element 3 </ b> A is fixed to the flexible mounting board 2, and the mounting board 2 is fixed to the board 20. As a result, the thermal stress is buffered by the mounting substrate 2, so that the connection reliability of circuit elements such as the semiconductor element 3 </ b> A can be ensured.
以上説明したように、切除領域Ａ１を設け、この切除領域Ａ１は、所定の間隔を有する。従って、お互いにその側面がこすれることが無いので、フィラー等の落下を防止できる。更に、固定孔の周りに、金属からなる導電パターンおよび固定板が配置されるので、固定孔周囲の平坦度も維持できる。よつて、モジュールとして固定が信頼性高く実現でき、駆動部やセンサ部を有する電子機器の誤動作も防止できる。 As described above, the excision area A1 is provided, and the excision area A1 has a predetermined interval. Therefore, since the side surfaces are not rubbed with each other, the fall of the filler or the like can be prevented. Furthermore, since the conductive pattern and the fixing plate made of metal are arranged around the fixing hole, the flatness around the fixing hole can be maintained. Therefore, fixing as a module can be realized with high reliability, and malfunction of an electronic device having a drive unit and a sensor unit can also be prevented.
１ 回路モジュール
２ 実装基板
３Ａ 半導体素子
３Ｂ チップ素子
３Ｃ チップ素子
４ 固定板
４Ｃ ビス孔
５ 外部端子
６ 半田
７ 被覆樹脂
８Ａ ビス
８Ｂ ヘッド
９ 固定孔
１２Ａ 第1の絶縁膜
１２Ｂ 第２の絶縁膜
１２Ｃ 第３の絶縁膜
１８Ａ 第1の配線層
１８Ｂ 第２の配線層
１８Ｃ 第３の配線層
１８Ｄ 第４の配線層
DESCRIPTION OF SYMBOLS 1 Circuit module 2 Mounting board 3A Semiconductor element 3B Chip element 3C Chip element 4 Fixing plate 4C Screw hole 5 External terminal 6 Solder 7 Coating resin 8A Screw 8B Head 9 Fixing hole 12A 1st insulating film 12B 2nd insulating film 12C 1st 3 Insulating film 18A First wiring layer 18B Second wiring layer 18C Third wiring layer 18D Fourth wiring layer
Claims (3)
前記露出配線層に電気的に接続された回路素子と、
前記実装基板の側辺の近傍であり、厚み方向に貫通して設けられたビス挿入用の固定孔とを具備し、
前記側辺と前記固定孔に挟まれる機械的強度の弱い部分が切除されて、前記固定孔の内壁と前記実装基板の側辺が連続して形成され、
前記実装基板の前記一主面に露出して前記固定孔を囲むように配置されたリング状の金属からなる配線層であり、前記実装基板の前記側辺と近接した領域が切除されて設けられ、表面には、Ｎｉ、ＡｕまたはＡｇがメッキにより設けられて、接着剤を介して固着されるＣｕまたはＦｅからなる固定板が設けられることを特徴とする駆動部やセンサ部を有する精密機器に内蔵されてビス止めされる回路モジュール。 A mounting substrate in which an insulating film containing a glass fiber or a filler and a wiring layer form a multilayer wiring structure and an exposed wiring layer exposed on one main surface is provided;
A circuit element electrically connected to the exposed wiring layer;
It is in the vicinity of the side of the mounting substrate, and includes a fixing hole for screw insertion provided penetrating in the thickness direction,
A portion with weak mechanical strength sandwiched between the side edge and the fixing hole is cut off, and the inner wall of the fixing hole and the side edge of the mounting substrate are continuously formed,
A wiring layer made of a ring-shaped metal that is disposed so as to be exposed on the one principal surface of the mounting substrate and surround the fixing hole, and is provided by cutting away a region close to the side of the mounting substrate. In a precision instrument having a drive unit and a sensor unit, the surface is provided with a fixing plate made of Cu or Fe, which is provided with Ni, Au, or Ag by plating, and is fixed by an adhesive. Built-in and screwed circuit module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004222820A JP4636827B2 (en) | 2004-07-30 | 2004-07-30 | Circuit module |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2004222820A JP4636827B2 (en) | 2004-07-30 | 2004-07-30 | Circuit module |
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| JP2006041410A JP2006041410A (en) | 2006-02-09 |
| JP4636827B2 true JP4636827B2 (en) | 2011-02-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014002923A1 (en) * | 2012-06-26 | 2014-01-03 | 株式会社村田製作所 | Mounting board and light-emitting device |
| EP3057217A4 (en) * | 2013-10-07 | 2017-07-12 | Hitachi Automotive Systems, Ltd. | Power conversion device |
| WO2023074130A1 (en) * | 2021-10-25 | 2023-05-04 | ソニーグループ株式会社 | Electronic circuit and electronic device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613189U (en) * | 1992-07-28 | 1994-02-18 | 京セラ株式会社 | Circuit board fastening mechanism |
| JPH0741985U (en) * | 1993-12-24 | 1995-07-21 | 富士通テン株式会社 | Terminal board fixing structure |
| JPH08335752A (en) * | 1995-04-04 | 1996-12-17 | Matsushita Electric Ind Co Ltd | Flexible wiring board and its manufacture |
| JPH11317570A (en) * | 1998-05-06 | 1999-11-16 | Seiko Epson Corp | Electronic equipment |
| JPH11354946A (en) * | 1998-06-04 | 1999-12-24 | Matsushita Electric Ind Co Ltd | Grounding method and structure for printed-circuit board in electronic equipment |
| JP2000049424A (en) * | 1998-07-29 | 2000-02-18 | Canon Inc | Printed circuit board |
| JP2001036265A (en) * | 1999-06-11 | 2001-02-09 | Samsung Electronics Co Ltd | Electronic system with printed board mounting instrument |
| JP2003023273A (en) * | 2001-07-06 | 2003-01-24 | Kitagawa Ind Co Ltd | Screw mounting structure of printed wiring board, grounding structure thereof, and thin plate member |
| JP2004014580A (en) * | 2002-06-03 | 2004-01-15 | Nec Corp | Metal fitting mounting structure for printed-wiring board |
-
2004
- 2004-07-30 JP JP2004222820A patent/JP4636827B2/en not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613189U (en) * | 1992-07-28 | 1994-02-18 | 京セラ株式会社 | Circuit board fastening mechanism |
| JPH0741985U (en) * | 1993-12-24 | 1995-07-21 | 富士通テン株式会社 | Terminal board fixing structure |
| JPH08335752A (en) * | 1995-04-04 | 1996-12-17 | Matsushita Electric Ind Co Ltd | Flexible wiring board and its manufacture |
| JPH11317570A (en) * | 1998-05-06 | 1999-11-16 | Seiko Epson Corp | Electronic equipment |
| JPH11354946A (en) * | 1998-06-04 | 1999-12-24 | Matsushita Electric Ind Co Ltd | Grounding method and structure for printed-circuit board in electronic equipment |
| JP2000049424A (en) * | 1998-07-29 | 2000-02-18 | Canon Inc | Printed circuit board |
| JP2001036265A (en) * | 1999-06-11 | 2001-02-09 | Samsung Electronics Co Ltd | Electronic system with printed board mounting instrument |
| JP2003023273A (en) * | 2001-07-06 | 2003-01-24 | Kitagawa Ind Co Ltd | Screw mounting structure of printed wiring board, grounding structure thereof, and thin plate member |
| JP2004014580A (en) * | 2002-06-03 | 2004-01-15 | Nec Corp | Metal fitting mounting structure for printed-wiring board |
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| JP2006041410A (en) | 2006-02-09 |
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