JP4619060B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a wiring using a droplet discharge method and a method for manufacturing a semiconductor device. In particular, the present invention relates to a wiring manufacturing method and a semiconductor device manufacturing method for forming a conductor functioning as a pillar by a droplet discharge method in order to connect an upper layer pattern and a lower layer pattern.

In recent years, pattern formation by a droplet discharge method (inkjet method or the like) has been applied to the field of flat panel displays and has been actively developed. The droplet discharge method has many advantages such as no need for a mask for direct drawing, easy application to a large substrate, high material utilization efficiency, etc., so that an EL layer, a color filter, an electrode for a plasma display, etc. can be produced. Has been applied.

The process using the droplet discharge method has the great advantage that no mask is required, but when making contact between the lower layer and the upper layer, it is necessary to form a contact hole or a metal cylinder that functions as a pillar. For this purpose, a series of photolithography processes such as exposure and development are necessary.

As a method for forming a highly accurate and well-formed pillar, for example, an opening formed in a photoresist layer is filled with a non-photosensitive organic film, and the non-photosensitive organic film on the photoresist layer is formed into a photoresist layer. There is a method of obtaining a non-photosensitive organic film having a desired pattern by etching back the entire surface until the film is exposed, exposing and developing the entire surface of the photoresist layer, and removing the photoresist layer (see Patent Document 1).
JP 2001-267230 A (first page, FIG. 1)

When a photolithography process is used as in Patent Document 1, the number of processes increases, resulting in a decrease in yield.
In view of the above circumstances, an object of the present invention is to provide a method for manufacturing a wiring and a method for manufacturing a semiconductor device that do not require a photolithography process when connecting an upper layer pattern and a lower layer pattern.

In order to solve the above-described problems of the prior art, the following measures are taken in the present invention.

The wiring manufacturing method of the present invention includes a step of locally discharging a composition containing a conductive material so as to be in contact with a first pattern on a substrate to form a conductor functioning as a pillar, and the conductor covers the first pattern. Forming an insulator so as to be exposed, etching the insulator so that the conductor is exposed, and forming a second pattern so as to be in contact with the exposed conductor. . This manufacturing process is as shown in FIG.

According to a method for manufacturing a semiconductor device of the present invention, a step of forming a conductor functioning as a pillar by locally discharging a composition containing a conductive material so as to be in contact with an impurity region included in a semiconductor, the conductor is covered. Forming an insulator, etching the insulator so that the conductor is exposed, and forming a pattern so as to be in contact with the exposed conductor.

The method for manufacturing a semiconductor device of the present invention includes a step of forming an N-type semiconductor so as to be in contact with a first pattern, a step of stacking a semiconductor and a first insulator so as to be in contact with the N-type semiconductor, the first Forming a second pattern by discharging a composition so as to be in contact with the insulator, and simultaneously patterning the N-type semiconductor, the semiconductor, and the first insulator using the second pattern as a mask, Removing the second pattern; forming a conductor functioning as a pillar by locally discharging a composition containing a conductive material so as to be in contact with the first pattern; and covering the conductor. Forming the second insulator, etching the second insulator so that the conductor is exposed, and contacting the exposed conductor It characterized by having a step of forming a pattern. The semiconductor is an amorphous semiconductor, and the process is as shown in FIG.

Note that in the above manufacturing method, an N-type semiconductor is illustrated as a semiconductor including one conductivity type impurity; however, the present invention is not limited to this mode. As a semiconductor containing one conductivity type impurity, another conductivity type semiconductor may be used.

The method for manufacturing a semiconductor device of the present invention includes a step of forming a first pattern so as to be in contact with a first insulator formed on a semiconductor, and a step of adding an impurity to the semiconductor using the first pattern as a mask. A step of locally discharging a composition containing a conductive material so as to be in contact with an impurity region included in the semiconductor to form a conductor functioning as a pillar; and a second insulator so as to cover the conductor Forming the second insulator so that the conductor is exposed; and forming a second pattern so as to be in contact with the exposed conductor. The semiconductor is a polycrystalline semiconductor, and the process is as shown in FIG.

In the above method for manufacturing a wiring and a method for manufacturing a semiconductor device, the composition is discharged using a droplet discharge unit. The droplet discharge means corresponds to a nozzle having a discharge port and a head having one or a plurality of nozzles. The nozzle generates heat by generating a piezo element or a heating element. A heating body for extruding the solution is provided. Then, using the droplet discharge means, the composition is locally discharged and the composition is deposited to form a conductor. This conductor is preferably formed in a cylindrical shape. As the composition discharged from the discharge port, a composition obtained by decomposing or dispersing a conductive material such as silver, gold, copper, or indium tin oxide in a solvent is used. Further, the insulator formed so as to cover the conductor is etched by an etch back method or a CMP method. The insulator is formed by discharging a composition containing a resin.

A method of manufacturing a wiring for connecting upper and lower patterns by forming a conductor functioning as a pillar for connection with an upper layer pattern on a lower layer pattern, wherein the conductor is formed by a droplet discharge method. According to the present invention, the upper and lower patterns can be connected without forming a contact hole. Accordingly, the steps required for forming the contact hole, for example, steps such as resist coating, exposure, development, post-baking, and etching can be omitted, so that the yield can be improved.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
A method for manufacturing a wiring according to the present invention will be described with reference to FIGS.

As the substrate 10, a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process is used (see FIG. 1 (A)). A base film made of an insulator is formed on the substrate 10 as necessary. Then, a pattern 11 made of a conductor (conductor) or a semiconductor is formed on the substrate 10 by a known method such as a sputtering method, a vapor deposition method, a CVD method, or a droplet discharge method.

Next, the droplet discharge means 14 locally discharges a composition containing a conductive material so as to be in contact with the pattern 11, thereby forming the conductor 12 that functions as a pillar. The conductor 12 is preferably formed into a columnar shape by depositing the discharged composition. This is because when the cylindrical conductor 12 is used, the contact between the lower layer pattern and the upper layer pattern is reduced. It is because it is easy to take. In FIG. 1A, the composition is shown so that it can be seen.

The cylindrical shape is a three-dimensional shape surrounded by three cylindrical surfaces and two planes (hereinafter referred to as a first plane and a second plane) that intersect with the generatrix and are parallel to each other. The shape of the plane and the second plane are often the same circle. However, the cylindrical shape in the present invention includes a case where the shapes of the first plane and the second plane are different. Actually, the conductor 12 formed by the droplet discharge method is formed such that the area of the first plane of the lower layer is larger than the area of the second plane of the upper layer.
The cylindrical conductor 12 has a top surface diameter of 0.01 to 10 μm (preferably 0.1 to 5 μm), a bottom surface diameter of 0.1 to 100 μm (preferably 1 to 10 μm), and a height of 0. It is preferable to form with a thickness of 0.05 to 5 μm (preferably 0.1 to 3 μm). The diameter and height representing these conductors 12 greatly depend on the material of the lower layer and the upper layer and the discharge conditions.

In addition, the shape of the conductor 12 is not limited to a columnar shape, and may be any shape as long as the contact of the upper and lower patterns can be taken. It may be formed. As described above, the diameter and height of the conductor 12 depend on various parameters such as the material of the lower layer pattern 11 and the discharge conditions of the composition. For example, the height of the conductor 12 is lower. Depends on the material of the pattern 11. Specifically, it depends on whether the material of the pattern 11 is hydrophilic or hydrophobic. In other words, it depends on the contact angle of the material of the pattern 11. For example, when the conductor 12 is formed using a composition in which silver (Ag) is dissolved or dispersed in a tetradecane solvent, a laminate of tantalum nitride (TaN) and tungsten (W) (TaN \ W), amorphous When four materials of a crystalline semiconductor (a-Si), a polycrystalline semiconductor (p-Si), and silicon oxynitride (SiON) are used for the lower layer pattern 11, TaN \ W>a-Si> p-Si The height during deposition can be increased in the order of> SiON.
Therefore, in order to form the conductor 12 having a more suitable shape with a small diameter and a high height on the upper and lower surfaces of the cylindrical conductor 12, the ejection speed of the composition is changed by changing the ejection conditions. It is good to slow down or to change the viscosity of the composition.
Moreover, you may adjust the height of the conductor 12 by repeating discharge of 1 drop or multiple drops of a composition, and the heat processing after discharge.

The droplet discharge means 14 for drawing a pattern is a general term for a means having a means for discharging a droplet, and specifically, a nozzle having a discharge port for a composition or a head having one or a plurality of nozzles. It is equivalent.
The nozzle diameter of the droplet discharge means 14 is set to 0.02 to 100 μm (preferably 30 μm or less), and the discharge amount of the composition discharged from the nozzle is 0.001 pl to 100 pl (preferably 10 pl or less). This discharge amount increases in proportion to the size of the nozzle diameter.
The diameter of the nozzle may be appropriately changed depending on the desired diameter of the conductor 12. In addition, the distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop it at a desired location, preferably about 0.1 to 3 mm (preferably about 1 mm or less). Set.

A composition in which a conductor is dissolved or dispersed in a solvent is used as the composition discharged from the discharge port. Conductors are silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), rhodium (Rh), tungsten (W), aluminum It corresponds to a metal such as (Al), silver halide fine particles, or dispersible nanoparticles. Alternatively, it corresponds to indium tin oxide (ITO), organic indium, organic tin, zinc oxide (ZnO), titanium nitride (TiN), or the like used as a transparent conductive film. However, it is preferable to use a composition in which any one of gold, silver, and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value as the composition discharged from the discharge port. More preferably, low resistance silver or copper is used. However, when copper is used, a barrier film may be provided as a countermeasure against impurities.
The solvent corresponds to esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone.
Further, the viscosity of the composition is preferably 50 cp or less, which is to prevent the drying from occurring or to smoothly discharge the composition from the discharge port. The surface tension of the composition is preferably 40 mN / m or less. Note that the viscosity of the composition and the like may be appropriately adjusted according to the solvent to be used and the application. As an example, the viscosity of a composition in which ITO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 50 mPa · S, the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa · S, The viscosity of the composition in which gold is dissolved or dispersed in a solvent is 10 to 20 mPa · S.

Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductor particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.5 to 10 μm. However, when formed by a gas evaporation method, the nanomolecules protected by the dispersant are as fine as about 7 nm, and these nanoparticles are aggregated in the solvent when the surface of each particle is covered with a coating agent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

When the step of discharging the composition is performed under reduced pressure, the solvent of the composition is volatilized between the time of discharging the composition and landing on the object to be processed, and the subsequent drying and baking steps are omitted. be able to. Further, it is preferable to perform under reduced pressure because an oxide film or the like is not formed on the surface of the conductor.

After discharging the composition, one or both steps of drying and baking are performed. The drying and baking steps are both heat treatment steps. For example, drying is performed at 100 degrees for 3 minutes, and baking is performed at 200 to 350 degrees for 15 minutes to 30 minutes. Time is different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that this heat treatment may be performed after the conductor 12 is formed, or may be performed after an insulator is formed in an upper layer of the conductor 12, and the timing is not particularly limited.
In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is generally 100 to 800 degrees (preferably 200). ~ 350 degrees). By this step, the solvent in the composition is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and contracted to bring the nanoparticles into contact with each other, thereby accelerating fusion and fusion.

For the laser light irradiation, a continuous wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and a YAG laser, and examples of the latter solid-state laser include a laser using a crystal such as YAG or YVO ₄ doped with Cr, Nd, or the like. Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. In addition, a so-called hybrid laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate 10, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds so that the substrate 10 is not destroyed.
Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature for several minutes to several microseconds. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, only the outermost thin film can be heated substantially without affecting the lower layer film. The substrate 10 having low heat resistance does not affect the substrate 10.

Next, an insulator 15 is formed so as to cover the conductor 12 functioning as a pillar (FIG. 1B). More specifically, a known method such as a plasma CVD method, a sputtering method, an SOG (Spin On Glass) method, a spin coating method, or a droplet discharge method is applied to the entire surface of the substrate 10 so as to cover the conductor 12. The insulator 15 is formed with a thickness of 5 μm (preferably 100 nm to 2 μm).
As a material of the insulator 15, an insulating film containing silicon such as a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, and a silicon oxynitride film is used to form a single layer or a stacked layer. However, from the viewpoint of wiring capacitance, it is preferable to use a material having a low dielectric constant (preferably a material having a relative dielectric constant of 4 or less), for example, acrylic, benzocyclobutene, parylene, flare, and transparency. An organic material such as polyimide may be used. When an organic material is used as the insulator 15, the flatness thereof is excellent, so that even when a conductor is formed later, the film thickness does not become extremely thin or disconnection does not occur at the step portion. Therefore, it is preferable. In addition, when a low dielectric constant material is used for the interlayer insulating film, wiring capacitance is reduced, so that multilayer wiring can be formed, and a semiconductor device with high performance and high functionality can be provided. . However, when an organic material is used as the insulator 15, a silicide film such as titanium (Ti), titanium nitride (TiN), titanium silicide (TiSix), molybdenum silicide (MoSix), or polysilicon is used to prevent outgassing. A barrier film is formed using a material such as a film, niobium (Nb), titanium oxynitride (TiON), tungsten (W), tungsten nitride (WN), titanium tungsten nitride (TiWN), and tantalum (Ta). Also good. The barrier film may be either a single layer or a laminated structure. This barrier film enhances adhesion, imparts embedding properties, and further reduces and stabilizes contact resistance.

Next, the insulator 15 is etched so that the conductor 12 functioning as a pillar is exposed. (FIG. 1C). More specifically, the insulator 15 is etched by either the etch back method or the CMP method (chemical mechanical polishing) so that the tip of the conductor 12 is exposed.
This step is a step of flattening the surface by removing the convex portions generated by forming the insulator 15 on the conductor 12. At this time, not only the protrusion is removed, but the insulator 15 is etched until the tip of the conductor 12 is exposed.

In addition, although the insulator 12 is etched through the above steps to expose the conductor 12, the portion where the conductor 12 is exposed is not particularly limited. That is, it is only necessary to expose a part of the conductor 12 through the above-described process, and the exposed part of the conductor 12 may be only the frontmost part of the conductor 12 or the conductor 12. Only the upper surface portion may be used.

Next, a pattern 17 made of a conductor or a semiconductor is formed by a known method so as to be in contact with the exposed conductor 12 (FIG. 1D).
Through the above steps, the pattern 11 and the pattern 17 can be connected by providing the conductor 12 functioning as a pillar for connection with the pattern 17 on the pattern 11.

From the viewpoint of tact time, it is preferable to form one or both of the patterns 11 and 17 by a droplet discharge method. This can be achieved by replacing the nozzle filled with the composition or replacing the composition filling the nozzle. In addition, when the droplet discharge method is used, a photolithography process using a mask is not necessary, so that the yield is improved.

In the present invention in which the conductor 12 functioning as a pillar is formed by a droplet discharge method, upper and lower patterns can be connected without forming a contact hole. Accordingly, steps necessary for forming the contact hole, such as resist coating, exposure, development, post-bake, and etching steps, can be omitted, thereby improving the yield. Further, according to the present invention using the droplet discharge method, the utilization efficiency of the material is greatly improved and the amount of waste liquid processing is reduced, so that it is possible to provide a process that contributes to solving environmental problems. Furthermore, since a mask is unnecessary, the manufacturing process is simplified and the yield is improved. In addition, it is possible to easily cope with a substrate having a side of 1 meter or more from the fifth generation onwards, and if it is under normal pressure, there is no need for a vacuum mechanism or the like, which brings about an effect of suppressing an increase in footprint in the clean room. .

(Embodiment 2)
A method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

First, a method for manufacturing a semiconductor device in which a bottom-gate thin film transistor using an amorphous semiconductor (a-Si) is manufactured and the present invention is applied to a wiring connected to the thin film transistor is described with reference to FIGS. A) will be described.

Conductors 101 and 102 are formed over the substrate 100 by a droplet discharge method, and then an N-type amorphous semiconductor 103, an amorphous semiconductor 104, and an insulator 105 are stacked so as to cover the conductors 101 and 102. It forms (FIG. 2 (A)). Next, the conductor 106 is formed over the insulator 105 by a droplet discharge method. At this time, a concave portion is formed in the insulator 105, and by using the concave portion as a bank, the landing accuracy can be improved and the conductor 106 can be formed at a desired location. Next, a mask 107 made of an organic insulator such as resist or polyimide is formed, and the N-type amorphous semiconductor 103, the amorphous semiconductor 104, and the insulator 105 are simultaneously patterned using the mask 107 to form an N-type. An amorphous semiconductor 108, an amorphous semiconductor 109, and an insulator 110 are formed (FIG. 2B).

Next, conductors 111 and 112 that function as pillars are formed by a droplet discharge method so as to be in contact with the conductors 101 and 102. At this time, the conductors 111 and 112 are preferably formed in a columnar shape. Next, an insulator 113 is formed so as to cover the conductors 111 and 112 (FIG. 2C). Subsequently, the insulator 113 is etched so that the conductors 111 and 112 are exposed (FIG. 2D). At this time, the insulator 113 is etched so that the tips of the conductors 111 and 112 are exposed. Next, the conductors 114 and 115 are formed so as to be in contact with the exposed conductors 111 and 112 (FIG. 2E). Here, the conductors 114 and 115 are formed by a droplet discharge method.
By providing the conductors 111 and 112 for connection to the conductors 114 and 115 on the conductors 101 and 102 through the above steps, the upper and lower patterns can be connected. The present invention having the above steps can connect the upper and lower patterns without forming a contact hole.

Next, the conductor 116 is formed so as to be in contact with the conductor 115. This conductor 116 functions as a pixel electrode later. Next, an alignment film 117 is formed over the conductor 116 (FIG. 4A). Then, a substrate 122 on which the color filter 121, the counter electrode 120, and the alignment film 119 are formed is prepared, the substrates 100 and 122 are bonded together by heat curing of a seal portion (not shown), and then the liquid crystal 118 is injected. Then, a semiconductor device having a display function using a liquid crystal element is completed. Polarizing plates 123 and 124 are attached to the substrates 100 and 122, respectively.

Next, a top gate thin film transistor using a polycrystalline semiconductor (p-Si) is manufactured, and a method for manufacturing a semiconductor device in which the present invention is applied to manufacturing a wiring connected to the thin film transistor is described with reference to FIGS. A description will be given using B).

After a semiconductor is formed over the substrate 200 and the insulator 204 is formed over the semiconductor, a conductor 205 is formed over the insulator 204 by a droplet discharge method (FIG. 3A). Next, using the conductor 205 as a mask, an impurity is added to the semiconductor, and impurity regions 202 and 203 to which the impurity is added and a channel formation region 201 are formed. Next, conductors 206 to 208 functioning as pillars are formed by a droplet discharge method so as to be in contact with the impurity regions 202 and 203 and the conductor 205 (FIG. 3B). At this time, the conductors 206 to 208 are preferably formed in a columnar shape. Next, an insulator 209 is formed so as to cover the conductors 206 to 208 (FIG. 3C).

Subsequently, the insulator 209 is etched so that the conductors 206 to 208 are exposed (FIG. 3D). At this time, the insulator 209 is etched so that the tips of the conductors 206 to 208 are exposed. Next, the conductors 210 to 212 are formed so as to be in contact with the exposed conductors 206 to 208 (FIG. 3E). Here, the conductors 210 to 212 are formed by a droplet discharge method.
Through the above steps, upper and lower patterns can be connected by providing conductors 206 to 208 functioning as pillars for connecting the conductors 210 to 212 on the impurity regions 202 and 203 and the conductor 205. The present invention having the above steps can connect the upper and lower patterns without forming a contact hole.

Next, the conductor 213 is formed so as to be in contact with the conductor 212. This conductor 213 functions as a pixel electrode later. Next, an insulator 214 functioning as a bank is formed, an electroluminescent layer 215 is formed over the insulator 214, and a conductor 216 is formed over the electroluminescent layer 215. A stacked body of the conductor 213, the electroluminescent layer 215, and the conductor 216 corresponds to a light-emitting element. The light emitted from the light-emitting element is emitted from the top surface where light is emitted to the substrate side, and from the bottom surface where light is emitted oppositely, by forming a pair of electrodes with a transparent material or a thickness capable of transmitting light. There are two-sided emission in which light is emitted on both of them, and either of them may be applied. Through the above steps, a semiconductor device having a display function using a light emitting element is completed.

Next, a method for manufacturing a semiconductor device in which a channel protective thin film transistor using an amorphous semiconductor is formed and the present invention is applied to manufacturing a wiring connected to the thin film transistor will be described with reference to FIGS.

A conductor 311 is formed over the substrate 300, and an insulator 312 is formed so as to cover the conductor 311 (FIG. 11A). Subsequently, an amorphous semiconductor is formed over the entire surface, and an insulator is formed over the entire surface so as to cover the amorphous semiconductor. Next, only the insulator is patterned using a mask to form an insulator layer 314 serving as an etching stopper. Next, after forming an N-type amorphous semiconductor over the entire surface so as to cover the insulator layer 314, the amorphous semiconductor and the N-type amorphous semiconductor are simultaneously patterned using a mask to form an amorphous A semiconductor layer 313 and N-type amorphous semiconductor layers 315 and 316 are formed. Subsequently, conductors 317 and 318 connected to the N-type amorphous semiconductor layers 315 and 316 are formed.

Next, a conductor 319 functioning as a pillar is formed by a droplet discharge method so as to be in contact with the conductor 318. At this time, the conductor 319 is formed in a cylindrical shape. Next, an insulator 320 is formed so as to cover the conductor 319 (FIG. 11B).

Subsequently, the insulator 320 is etched so that the conductor 319 is exposed (FIG. 11C). At this time, the insulator 320 is etched so that the tip of the conductor 319 is exposed. Next, conductors 321 and 322 are formed so as to be in contact with the exposed conductor 319. Note that the conductor 322 corresponds to a pixel electrode and can be formed over the insulator 320 to increase the aperture ratio.
By providing the conductor 319 functioning as a connection pillar with the conductor 321 over the conductor 318 through the above steps, the upper and lower patterns can be connected. The present invention having the above steps can connect the upper and lower patterns without forming a contact hole.

Note that in the above description, an N-type semiconductor is exemplified as a semiconductor including one conductivity type impurity. However, the present invention is not limited to a mode in which an N-type semiconductor is used as a semiconductor containing an impurity of one conductivity type, and other conductivity-type semiconductors may be used.

This embodiment can be applied to Embodiment 1 described above.

(Embodiment 3)
As an embodiment of the present invention, a method for manufacturing a semiconductor device in which the present invention is applied to manufacturing a multilayer wiring will be described with reference to FIGS.

FIG. 5 is a cross-sectional view of a semiconductor device in which five layers are stacked on a substrate 200. Thin film transistors 220 to 222 are formed as the first layer, and wirings are formed from the second layer to the fifth layer. Indicates the case. The present invention is applied to the production of a conductor that functions as a connecting pillar for a pattern of a lower layer and an upper layer in all layers.

A semiconductor device including such a multilayer wiring is preferably used for a functional circuit that needs to incorporate a large number of semiconductor elements such as a CPU. If a multilayer wiring is not formed, it is necessary to fabricate the wiring in the same layer as the gate electrode and the source / drain wiring of the semiconductor element (herein referred to as a thin film transistor) formed in the first layer. If it does so, it will be necessary to route wiring, and the yield will become worse by that much and an arrangement area will become large. In this case, the semiconductor device cannot be downsized except for reducing the size of the semiconductor element.
On the other hand, if a multilayer wiring is manufactured using the wiring manufacturing method of the present invention, the upper and lower patterns can be connected without forming a contact hole, so that the yield is improved. Further, the width between elements can be narrowed in the first layer for high integration, and wiring can be formed in the upper layer. Therefore, a significant reduction in size is realized, and further, there is no need to route the wiring, leading to a reduction in resistance and an increase in speed.

In addition, when an organic material having a low dielectric constant is used as the insulator between the upper layer and the lower layer, the flatness is excellent, so that the film thickness is extremely thin at the step portion even when the conductor is formed later. This is preferable because it does not occur or disconnection occurs. In addition, since the wiring capacitance is reduced, a semiconductor device with high performance and high functionality can be provided.

An example of a droplet discharge device used for manufacturing the wiring and the semiconductor device of the present invention will be described with reference to FIGS. First, the structure of the droplet discharge device will be briefly described with reference to FIG. As essential components of the apparatus, droplet discharge means (shown in FIG. 6B) having a head in which a plurality of nozzles are arranged in a uniaxial direction, a controller for controlling the droplet discharge means, and a CPU ( 6B), a stage 6403 that fixes the substrate 6401 and can move in the XYθ direction, and the like can be given. A frame 6402 for installing the droplet discharge means is provided for fitting the droplet discharge means illustrated in FIG. The stage 6403 also has a function of fixing the substrate 6401 by a technique such as a vacuum chuck. Then, the composition is discharged in the direction of the substrate 6401 from the discharge port of each nozzle included in the droplet discharge means, and a pattern is formed.

The stage 6403 and the droplet discharge means are controlled by the CPU via the controller. In addition, image pickup means such as a CCD camera (shown in FIG. 6B) is also controlled by the CPU. The imaging means captures the position of the marker and supplies the captured information to the CPU. Note that when producing a pattern, the droplet discharge unit may be moved, or the stage 6403 may be moved while the droplet discharge unit is fixed. However, when moving the droplet discharge means, it is necessary to consider the acceleration of the composition, the distance between the nozzle provided in the droplet discharge means and the object to be processed, and the environment.

In addition, as an accompanying component, in order to improve the landing accuracy of the discharged composition, a moving mechanism in which the droplet discharging means moves up and down, its control means, and the like may be provided. Then, the distance between the head and the substrate 6401 can be changed according to the characteristics of the composition to be discharged. Furthermore, you may provide the clean unit etc. which supply clean air and reduce the dust of a working area. In addition, means for heating the substrate, as well as means for measuring various physical properties such as temperature and pressure, may be installed as necessary. These means are also controlled by control means installed outside the housing. Collective control is possible. Furthermore, if the control means is connected to a production management system or the like with a LAN cable, wireless LAN, optical fiber, or the like, the process can be uniformly managed from the outside, leading to an improvement in productivity. In order to expedite the drying of the deposited composition and to remove the solvent component of the composition, the droplet discharge means may be operated under reduced pressure by performing vacuum evacuation.

FIG. 6B illustrates a droplet discharge unit, which includes a piezoelectric element 6404 and frames 6405 and 6406. The composition is discharged from the discharge port 6407 of the droplet discharge means. Note that FIG. 6B illustrates a piezo method using the piezoelectric element 6404; however, depending on the material of the solution, a method of extruding the solution by generating heat in the heating element to generate bubbles may be used. In this case, the piezoelectric element is replaced with a heating element. For droplet discharge, wettability between the solution and the liquid chamber flow path, the spare liquid chamber, the fluid resistance portion, the pressurizing chamber, and the solution discharge port is important. Therefore, a carbon film, a resin film, or the like for adjusting wettability with the composition may be formed in each flow path. Further, wiring, supply pipes, and the like are provided inside the frames 6405 and 6406, and when the droplet discharge means shown in FIG. 6B is attached to the apparatus shown in FIG. Is connected to a drive circuit for controlling the piezoelectric element, and the supply pipe is connected to a tank filled with the composition.

In this embodiment, the appearance of a panel which is one embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. FIG. 7A is a top view of a panel in which a pixel portion 4002 and a scan line driver circuit 4004 formed over a first substrate 4001 are sealed with a sealant 4005 between a second substrate 4006 and FIG. 7B is a cross-sectional view taken along the line AA ′ in FIG. 7A, and FIG. 7C is a cross-sectional view taken along the line A′-A ″.

7A and 7B, a sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Accordingly, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the liquid crystal 4007 by the first substrate 4001, the sealant 4005, and the second substrate 4006. In addition, a signal line driver circuit 4003 formed of a polycrystalline semiconductor is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001.

In this embodiment, an example in which the signal line driver circuit 4003 including a transistor using a polycrystalline semiconductor is attached to the first substrate 4001 is described; however, a signal line driver circuit is formed using a transistor including a single crystal semiconductor. , You may stick together. FIG. 7B illustrates a transistor 4009 that is included in the signal line driver circuit 4003 and is formed using a polycrystalline semiconductor.
In this embodiment, the signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001, but this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of transistors, and FIG. 7B illustrates the transistor 4010 included in the pixel portion 4002. This transistor 4010 is a transistor using an amorphous semiconductor as a channel portion. A portion where the pixel electrode 4030 electrically connected to the transistor 4010, the counter electrode 4031 formed over the second substrate 4006, and the liquid crystal 4007 overlap corresponds to a liquid crystal element. The spherical spacer 4035 is provided to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031.
In addition, as illustrated in FIG. 7C, a signal line driver circuit 4003 which is separately formed, and various signals and potentials supplied to the scan line driver circuit 4004 or the pixel portion 4002 function as lead wirings 4014 and 4015 and pillars. It is supplied from the connection terminal 4016 through the conductor 4017. The connection terminal 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

The present invention is applied to manufacturing a wiring included in the transistor 4010, a conductor 4017 functioning as a pillar, and the like. Although not shown, the panel may include an alignment film, a polarizing plate, a color filter, and a shielding film. Further, although the case where a liquid crystal element is included as a display element is illustrated, other display elements such as a self-luminous element may be applied.

In this embodiment, the appearance of a panel which is one mode of a semiconductor device to which the present invention is applied will be described with reference to FIGS. Specifically, a pixel portion, a driver circuit for controlling the pixel portion on the same surface, a panel on which a memory and a CPU are mounted will be described with reference to FIGS. FIG. 8A is a top view of the panel, and FIG. 8B is a cross-sectional view taken along line A-A ′ of FIG.

FIG. 8A shows an appearance of a panel. The panel includes a pixel portion 5401 in which a plurality of pixels are arranged in a matrix over a glass substrate 5400, a signal line driver circuit 5402 and a scan around the pixel portion 5401. A line driver circuit 5403 is provided. In addition, a VRAM (screen display dedicated memory), a memory 5406 corresponding to a RAM, and a ROM, and a CPU 5405 are provided over a substrate 5400. Further, an input terminal portion 5411 for supplying a signal for controlling the signal line driver circuit 5402, the scan line driver circuit 5403, the memory 5406, and the CPU 5405 is provided over the substrate 5400. A signal such as a video signal is supplied to the input terminal portion 5411 from an external circuit through the FPC 5412.
A sealant (not shown) is provided so as to surround the pixel portion 5401, the signal line driver circuit 5402, and the scan line driver circuit 5403, and the substrate 5400 and the counter substrate 5409 are attached to each other with the sealant. The counter substrate 5409 may be provided only over the pixel portion 5401, the signal line driver circuit 5402, and the scan line driver circuit 5403, or may be provided over the entire surface. However, it is preferable to provide a heat sink so as to be in contact with the CPU 5405 that may generate heat.

FIG. 8B is a cross-sectional view of a panel. A pixel portion 5401, a signal line driver circuit 5402, and a CPU 5405 are provided over a substrate 5400. The pixel portion 5401 includes a transistor 5430 and a capacitor 5429, the signal line driver circuit 5402 includes an element group 5431 including a CMOS circuit and the like, and the CPU 5405 includes an element group 5440 and a wiring group 5441. A spacer 5435b is provided between the substrate 5400 and the counter substrate 5409. Over the pixel portion 5401, a rubbing alignment film 5435a, a liquid crystal layer 5423, an alignment film 5424, a counter electrode 5425, and a color filter 5426 are provided. Polarizer plates 5428 and 5427 are attached to the substrate 5400 and the counter substrate 5409.
The present invention is applied to manufacturing a wiring that forms the transistor 5430, the capacitor 5429, and the element groups 5431 and 5440, manufacturing a wiring that forms the wiring group 5441, and the like.

The elements constituting the circuit on the substrate 5400 are formed by elements using a polycrystalline semiconductor (polysilicon) having better mobility and other characteristics than an amorphous semiconductor as a channel portion, and are therefore monolithic on the same surface. Is realized. In this manner, a panel in which functional circuits such as a CPU and a memory are integrally formed on the same substrate 5400 in addition to the pixel portion and the driver circuit is called a system-on-panel, and the system can be multifunctional. it can. Since the number of external ICs to be connected is reduced, the panel having the above configuration can be made small, light, and thin. This is very effective when applied to portable terminals that have been rapidly spread recently. Although not shown, the panel may have a light shielding film or the like. Further, although the case where a liquid crystal element is included as a display element is illustrated, other display elements such as a self-luminous element may be applied.

As an example of an electronic device manufactured by applying the present invention, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproducing device such as a car audio, a computer, a game device, a portable information terminal (mobile computer, cellular phone) , Portable game machines, electronic books, etc.), image reproduction apparatuses equipped with recording media such as home game machines (specifically, apparatuses equipped with a display capable of reproducing a recording medium such as a DVD and displaying the images) ) And the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 9A illustrates a 40-inch large liquid crystal television including a housing 9501, a display portion 9502, and the like. FIG. 9B illustrates a monitor used by being attached to a computer, which includes a housing 9601, a display portion 9602, and the like. FIG. 9C illustrates a monitor-integrated computer, which includes a housing 9801, a display portion 9802, and the like.
The present invention is applied to manufacturing each panel including the display portions 9502, 9602, and 9802, and particularly to manufacturing a wiring connected to a semiconductor element typified by a thin film transistor.
However, like the electronic devices shown in FIGS. 9A to 9C, each panel including the display portions 9502, 9602, and 9802 having a size of 10 inches or more is an amorphous semiconductor from the viewpoint of price and process. It is preferable to use a thin film transistor (a-Si TFT) that forms a channel portion. Since an amorphous semiconductor can omit a crystallization process in a manufacturing process, an inexpensive electronic device can be provided. Moreover, when a display part is comprised by a-SiTFT, it is preferable to apply a liquid crystal element as a display element from the response speed. In addition, since the panel which comprised the display part by a-SiTFT is as showing in FIG. 7, it is good to refer to the said drawing.

FIG. 10A illustrates a portable terminal, which includes a main body 9101, a display portion 9102, and the like. FIG. 10C illustrates a PDA, which includes a main body 9201, a display portion 9202, and the like. FIG. 10D illustrates a goggle type display including a main body 9301, a display portion 9302, and the like. FIG. 10E illustrates a portable game machine, which includes a main body 9401, a display portion 9402, and the like. FIG. 10F illustrates a digital video camera, which includes display portions 9701 and 9702 and the like. FIG. 10B illustrates an example of a panel including a display portion 9102, in which a driver circuit 9104 and a functional circuit 9103 such as a CPU and a memory are formed integrally with the display portion 9102. In this manner, an electronic device having a panel in which not only a drive circuit but also a functional circuit are integrally formed can reduce the number of external ICs to be connected, so that a small size, a light weight, and a thin shape are realized. This is because it is an effective configuration. Therefore, it is preferable to integrally form a driver circuit and a functional circuit not only in the panel including the display portion 9102 but also in each panel including the display portions 9202, 9302, 9402, 9701, and 9702.

The present invention is applied to manufacture of each panel included in the display portions 9102, 9202, 9302, 9402, 9701, and 9702, and particularly applicable to manufacture of wiring connected to a semiconductor element typified by a thin film transistor. Further, the present invention is applied to manufacture of a driver circuit and a functional circuit integrally formed on each panel described above, and particularly applied to manufacture of a wiring connected to a semiconductor element and manufacture of a multilayer wiring. Note that the driving circuit and the functional circuit are integrally formed and the panel is as shown in FIG.
In order to realize monolithic integration in which the functional circuit 9103 and the driver circuit 9104 are integrally formed, a channel portion is formed using a polycrystalline semiconductor (polysilicon) which has better characteristics such as mobility than an amorphous semiconductor. A thin film transistor is used.

Among the electronic devices listed above, a portable terminal such as a cellular phone preferably uses a self-luminous light emitting element as a display element provided in the display portion. This is because the self-luminous element does not require a backlight or the like, and thus is thinner, smaller, and lighter than when a liquid crystal element is used.

8A and 8B illustrate a method for manufacturing a wiring according to the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. FIGS. 7A to 7C illustrate a method for manufacturing a semiconductor device of the present invention, and specifically illustrate a method for manufacturing a semiconductor device having a display function. FIGS. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention, specifically, a method for manufacturing a semiconductor device having a multilayer wiring. 4A and 4B illustrate an example of a droplet discharge device used when manufacturing a wiring and a semiconductor device of the present invention. 1A and 1B are a top view and a cross-sectional view of a panel which is one embodiment of a semiconductor device to which the present invention is applied. 1A and 1B are a top view and a cross-sectional view of a panel which is one embodiment of a semiconductor device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Board | substrate 11 Pattern 12 Conductor 14 Droplet discharge means 15 Insulator 17 Pattern

Claims (3)

A first conductive layer is formed on the substrate by discharging the first composition,
A first semiconductor layer containing one conductivity type impurity, a second semiconductor layer, and a first insulator layer are stacked over the first conductor layer;
Forming a second conductor layer by discharging a second composition over the recesses of the first insulator layer;
Forming a mask on the second conductor layer;
Using the mask, the first semiconductor layer containing the one conductivity type impurity, the second semiconductor layer, and the first insulator so that a part of the first conductor layer is exposed. Pattern the layers simultaneously,
Removing the mask,
A third composition is locally ejected so as to be in contact with the exposed first conductor layer to form a third conductor layer functioning as a pillar,
Forming a second insulator layer by discharging a resin-containing composition so as to cover the third conductor layer;
Etching the second insulator layer such that the tip of the third conductor layer is exposed;
A method for manufacturing a semiconductor device, wherein a fourth conductor layer is formed by discharging a fourth composition so as to be in contact with a tip of the exposed third conductor layer. In claim 1,
The method for manufacturing a semiconductor device, wherein the third composition contains silver, gold, copper, or indium tin oxide. Oite to claim 1,
A method for manufacturing a semiconductor device, wherein the second insulator layer is etched by an etch back method or a CMP method.

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