JP2005101552A5 - - Google Patents

Claims (11)

On the first pattern, a composition containing a conductive material is locally ejected to form a conductor layer that functions as a pillar,
Forming an insulator layer so that the conductor layer is covered;
Etching the insulator layer so that a portion of the conductor layer is exposed;
A method of manufacturing a wiring, wherein a second pattern is formed on the exposed conductor layer . On the first pattern, a composition containing a conductive material is locally ejected to form a conductor layer that functions as a pillar,
A composition containing a resin is discharged so that the conductor layer is covered to form an insulator layer,
Etch the insulator layer by an etch back method or a CMP method so that a part of the conductor layer is exposed,
A method of manufacturing a wiring, wherein a second pattern is formed on the exposed conductor layer. According to claim 1 or claim 2,
The composition containing the conductive material contains silver, gold, copper, or indium tin oxide. According to claim 1 or claim 2,
One or both of the first pattern and the second pattern are formed by discharging a second composition containing a conductive material. According to claim 1 or claim 2,
One or both of the first pattern and the second pattern are formed by using a photolithography process. In claim 1 or claim 2,
The first pattern is a semiconductor layer;
The method for manufacturing a wiring , wherein the conductor layer is formed on an impurity region of the semiconductor layer . On the first pattern, a semiconductor layer containing an impurity of one conductivity type, a semiconductor layer, and a first insulator layer are stacked,
A second pattern is formed by discharging a composition on the first insulator layer ,
Using the second pattern as a mask, patterning the semiconductor layer containing the impurity of one conductivity type, the semiconductor layer, and the first insulator layer simultaneously so that the first pattern is exposed,
Removing the second pattern;
On the first pattern, a composition containing a conductive material is locally ejected to form a conductor layer functioning as a pillar,
Forming a second insulator layer so that the conductor layer is covered;
Etching the second insulator layer such that a portion of the conductor layer is exposed;
A method for manufacturing a semiconductor device, wherein a third pattern is formed on the exposed conductor layer . Forming a first pattern on the first insulator layer formed on the semiconductor layer ;
Using the first pattern as a mask, an impurity region is formed by adding an impurity to the semiconductor layer ,
A composition containing a conductive material is locally discharged on the impurity region to form a conductor layer functioning as a pillar,
Forming a second insulator layer so that the conductor layer is covered;
Etching the second insulator layer such that a portion of the conductor layer is exposed;
A method for manufacturing a semiconductor device, comprising forming a second pattern on the exposed conductor layer . In claim 7 or claim 8 ,
The composition containing the conductive material contains silver, gold, copper, or indium tin oxide. Or claim 7 according to claim 8,
A method for manufacturing a semiconductor device, wherein the second insulator layer is etched by an etch back method or a CMP method. Or claim 7 according to claim 8,
Said second insulator layer, a method for manufacturing a semiconductor device, characterized by that form by discharging a composition containing a resin.