JP2005165305A - Display device and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which can be manufactured by increasing utilization efficiency through simplified manufacturing steps, and to provide a manufacturing method therefor. <P>SOLUTION: At least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring layer or an electrode and a mask layer forming a prescribed pattern, are formed by a method with which the patterns can be selectively formed. At that time, the manufacturing method has a step in which a portion of the gate insulating film located other than under the semiconductor layer 212 is removed in the process of manufacturing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device including active elements such as transistors formed on a large area glass substrate and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, an active matrix driving type liquid crystal display device composed of thin film transistors (hereinafter also referred to as TFTs) formed on a glass substrate has various thin films by a light exposure process using a photomask, as in the semiconductor integrated circuit manufacturing technology. Has been manufactured by patterning.

  However, as the size of the glass substrate used for manufacturing increases, it has become difficult to manufacture a display panel with high productivity and low cost by the conventional patterning method. In other words, even if a large-size substrate is supported by, for example, continuous exposure, the processing time increases by performing a large number of exposure processes, and the development of an exposure apparatus corresponding to an increase in the size of the substrate requires a great investment. I came.

  In addition, as the substrate size increases, the manufacturing method in which various thin films are formed on the entire surface of the substrate and then etched while leaving only the necessary regions, as in the conventional light exposure process technology using a photomask, wastes material costs. However, it is required to process a large amount of waste such as waste liquid.

  An object of the present invention is to solve such problems, and to provide a liquid crystal display device that can be manufactured by improving the material utilization efficiency and simplifying the manufacturing process, and a manufacturing technique thereof. It is aimed.

  The present invention selectively selects at least one or more of patterns necessary for manufacturing a liquid crystal display device, such as a conductive layer for forming a wiring layer or an electrode, or a mask layer for forming a predetermined pattern. It is characterized by having a step of forming a pattern by a method capable of forming a pattern, and simultaneously removing a gate insulating film existing other than under the semiconductor layer in the course of preparation. Examples of the pattern forming method include a droplet discharge method, a screen printing method, and the like that can form a predetermined pattern by discharging droplets containing a predetermined composition such as a conductive layer, an insulating layer, and a mask layer from the pores. An offset printing method or the like can be used.

  A method for manufacturing a liquid crystal display device according to the present invention includes a first step of selectively forming a gate electrode layer on a substrate having an insulating surface or a substrate having a pretreated base surface by a droplet discharge method. A second step of forming a gate insulating layer on the gate electrode layer and forming the first semiconductor layer on the gate insulating layer; and a channel protective layer at a position overlapping with the gate electrode layer on the first semiconductor layer And a second step of forming a second semiconductor layer containing an impurity having one conductivity over the gate insulating layer, the first semiconductor layer, and the channel protective layer. A fourth step, a fifth step of selectively forming a first mask layer on the second semiconductor layer, and a first semiconductor layer and a second semiconductor layer positioned below the second semiconductor layer by the first mask layer. A sixth stage of etching the semiconductor layer of 1 and the gate insulating layer; A seventh step of selectively forming a first insulating layer by a droplet discharge method over the gate electrode layer, particularly at a portion intersecting with the source wiring layer or the drain wiring layer; An eighth stage in which the wiring layer is selectively formed by a droplet discharge method, a ninth stage in which the second semiconductor layer on the channel protective layer is etched, and a tenth stage in which a passivation film is formed on the entire surface of the substrate. A second insulating layer is selectively formed on the passivation film by a droplet discharge method; an eleventh step; a twelfth step of etching the passivation film on the drain wiring layer; and a second insulating layer. Each step of the thirteenth step of forming a transparent conductive film on the layer so as to be connected to the drain wiring layer is included. In the eleventh stage, the second insulating layer is selectively formed on the entire surface of the substrate except for an arbitrary region where a drain wiring layer and a transparent conductive film layer described later are connected by a droplet discharge method.

  The liquid crystal display device manufacturing method of the present invention includes a first step of selectively forming a gate electrode layer by a droplet discharge method on a substrate having an insulating surface or a substrate on which a base layer is formed as a pretreatment, Forming a gate insulating layer on the gate electrode layer, forming a first semiconductor layer on the gate insulating layer, and forming a channel protective layer at a position overlapping the gate electrode layer on the first semiconductor layer. A third step of selectively forming by a droplet discharge method; and a second step of forming a second semiconductor layer containing an impurity having one conductivity over the gate insulating layer, the first semiconductor layer, and the channel protective layer. 4, a fifth step of selectively forming a first mask layer on the second semiconductor layer, and the second mask layer by means of the first mask layer. And a sixth step of etching the gate insulating layer; A seventh step of selectively forming a first insulating layer by a droplet discharge method on the upper electrode layer, particularly at a portion intersecting with the source wiring layer or the drain wiring layer; and a source and drain wiring layer An eighth stage of selective formation by a droplet discharge method; a ninth stage of etching the second semiconductor layer on the channel protective layer using the source and drain wiring layers as a mask; and a passivation film on the entire surface of the substrate. A tenth step of forming a second insulating layer on the passivation film, an eleventh step of selectively forming a second insulating layer on the passivation film by a droplet discharge method, and a drain wiring layer using the second insulating layer as a mask The method includes a twelfth step of etching the upper passivation film and a thirteenth step of forming a transparent conductive film on the second insulating layer so as to be connected to the drain wiring layer. In the eleventh stage, the second insulating layer is selectively formed on the entire surface of the substrate except for an arbitrary region where a drain wiring layer and a transparent conductive film layer described later are connected by a droplet discharge method.

  In the second stage, it is preferable that the gate insulating layer and the semiconductor layer are continuously formed without being exposed to the air by a vapor phase growth method (plasma CVD method) or sputtering method using plasma.

  The gate insulating layer is formed by sequentially laminating the first silicon nitride film, the silicon oxide film, and the second silicon nitride film, so that the gate electrode can be prevented from being oxidized and formed on the upper layer side of the gate insulating film. It is possible to form a favorable interface with the semiconductor layer.

  As described above, the present invention is characterized in that it is performed by a method capable of selectively forming a pattern when forming a gate electrode layer, a wiring layer, and a mask used for patterning. A liquid crystal display device is manufactured by forming at least one or more patterns necessary for manufacturing a liquid crystal display device by a method capable of selectively forming a pattern such as a droplet discharge method. The purpose is achieved.

  A liquid crystal display device of the present invention includes at least a gate electrode layer provided on one of a pair of substrates holding a liquid crystal, and a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer. A thin film transistor including an island-shaped gate insulating film and a semiconductor layer is included, and the thin film transistor further includes a source wiring layer and a drain wiring layer formed of a conductive material connected to the semiconductor film. In addition, a pixel electrode connected to such a thin film transistor is included. Further, the semiconductor layer is provided so that the end of the semiconductor layer does not exceed the end of the gate insulating layer. Note that the thin film transistor can have a structure in which a gate electrode layer, an island-shaped gate insulating film, a semiconductor film, a source wiring layer, and a drain wiring layer are provided in this order from the substrate side.

  The liquid crystal display device of the present invention includes a gate electrode layer provided on one of a pair of substrates holding a liquid crystal, and a gate including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer An insulating film; a semiconductor layer; a thin film transistor having a source wiring layer and a drain wiring layer made of a conductive material and connected to the semiconductor layer; a pixel electrode connected to the thin film transistor; It may be provided so as to coincide with the edge of the layer.

  A liquid crystal display device of the present invention includes a gate electrode layer provided on one of a pair of substrates holding a liquid crystal, and a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer An island-shaped gate insulating film; a semiconductor layer; a source wiring layer and a drain wiring layer made of a conductive material connected to the semiconductor layer; a thin film transistor having a silicon nitride layer or a silicon nitride oxide layer in contact with the wiring layer; The end of the semiconductor layer may be provided so as not to exceed the end of the gate insulating layer.

  A liquid crystal display device of the present invention includes a gate electrode layer provided on one of a pair of substrates holding a liquid crystal, and a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer An island-shaped gate insulating film, a semiconductor layer, a source wiring layer and a drain wiring layer made of a conductive material connected to the semiconductor layer, and a thin film transistor having a silicon nitride layer or a silicon nitride oxide layer in contact with the wiring layer; A pixel electrode connected to the thin film transistor may be provided, and the end of the semiconductor layer may be provided so as to coincide with the end of the gate insulating layer.

  The liquid crystal display device of the present invention can have a driving circuit including a thin film transistor formed with the same layer structure as the above thin film transistor. That is, an island-shaped gate insulating film including a gate electrode layer provided on one of a pair of substrates holding a liquid crystal and a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer A semiconductor layer, a first thin film transistor having a source wiring layer and a drain wiring layer made of a conductive material and connected to the semiconductor layer, a pixel electrode connected to the first thin film transistor, and the same layer as the first thin film transistor The driving circuit includes a second thin film transistor formed with a structure, and a wiring layer extending from the driving circuit and connected to the gate electrode layer of the first thin film transistor. At this time, the end of the semiconductor layer of the thin film transistor included in the pixel portion or the driver circuit portion can be provided so as not to exceed the end of the gate insulating layer.

  A liquid crystal display device of the present invention includes a gate electrode layer provided on one of a pair of substrates holding a liquid crystal, and a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer An island-shaped gate insulating film; a semiconductor layer; a first thin film transistor connected to the semiconductor layer and having a source wiring layer and a drain wiring layer made of a conductive material; a pixel electrode connected to the first thin film transistor; A driving circuit including a second thin film transistor formed in the same layer structure as the first thin film transistor; a wiring layer extending from the driving circuit and connected to the gate electrode layer of the first thin film transistor; The end of the gate insulating layer may be provided so as to coincide with the end of the gate insulating layer.

  A liquid crystal display device of the present invention includes a gate electrode layer provided on one of a pair of substrates holding a liquid crystal, and a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer An island-shaped gate insulating film, a semiconductor layer, a source and drain wiring layer connected to the semiconductor layer and formed of a conductive material, and a silicon nitride layer or a silicon nitride oxide layer in contact with the source wiring layer and the drain wiring layer A first thin film transistor having a pixel electrode connected to the first thin film transistor, a second thin film transistor formed in the same layer structure as the first thin film transistor, and a drive circuit extending from the drive circuit, A wiring layer connected to the gate electrode layer of the first thin film transistor may be provided, and an end of the semiconductor layer may be provided so as not to exceed an end of the gate insulating layer.

  A liquid crystal display device of the present invention includes a gate electrode layer provided on one of a pair of substrates holding a liquid crystal, and a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer An island-shaped gate insulating film, a semiconductor layer, a source and drain wiring layer connected to the semiconductor layer and formed of a conductive material, and a silicon nitride layer or a silicon nitride oxide layer in contact with the source wiring layer and the drain wiring layer A first thin film transistor having a pixel electrode connected to the first thin film transistor, a second thin film transistor formed in the same layer structure as the first thin film transistor, and a drive circuit extending from the drive circuit, A wiring layer connected to the gate electrode layer of the first thin film transistor may be provided, and an end of the semiconductor layer may be provided so as to coincide with an end of the gate insulating layer.

  In the present invention, a gate electrode layer or a wiring layer is formed by a method capable of selectively forming a pattern. The conductive material is Ag or an alloy containing Ag, and Ni and NiB around Cu. It can be formed of Ag or particles coated with these laminated films. In addition, deterioration due to oxidation can be prevented by providing a silicon nitride film or a silicon nitride oxide film in contact with the gate electrode layer or the wiring layer.

  In the present invention, a semiconductor layer which is a main part of a thin film transistor is formed by using an amorphous semiconductor (hereinafter also referred to as “AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane, or A semi-amorphous (also referred to as microcrystal or microcrystal, hereinafter referred to as “SAS”) semiconductor or the like can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. At least 1 atomic% or more of hydrogen or halogen is contained as a neutralizing agent for dangling bonds. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silicide gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times. The pressure is generally in the range of 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300 ° C. or less. As an impurity element in the film, impurities of atmospheric components such as oxygen, nitrogen, and carbon are desirably 1 × 10 ²⁰ atoms / cm ³ or less, and in particular, the oxygen concentration is preferably 5 × 10 ¹⁹ atoms / cm ³ or less. Is 1 × 10 ¹⁹ atoms / cm ³ or less.

By using SAS, a driver circuit including only n-channel thin film transistors can be provided. That is, a driver circuit can be realized over the same substrate with a thin film transistor that can operate with a field effect mobility of 1 to 15 cm ² / V · sec.

  According to the present invention, the patterning of the wiring layer and the mask can be directly performed by a droplet discharge method or the like, so that the use efficiency of the material can be expected and the manufacturing process can be simplified because the etching process can be reduced. Thus, a thin film transistor and a liquid crystal display device using the thin film transistor can be obtained.

  In addition, since there is no gate insulating layer other than the portion located below the semiconductor layer, it is easy to connect the TFTs by wiring, and a polycrystalline semiconductor or microcrystalline silicon that can obtain high field effect mobility. If a TFT is formed using a semiconductor, various circuits such as a scanning line side driving circuit can be easily mounted on the substrate in the same process as the pixel TFT.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings. In addition, in the following description, in the equivalent site | part common between each drawing, it shall attach and show the same code | symbol, and it abbreviate | omits about the overlapping description. Further, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. The present invention is not construed as being limited to the following embodiments.

  FIG. 1 is a top view illustrating a configuration of a liquid crystal display device according to the present invention. A pixel portion 101 in which pixels 102 are arranged in a matrix on a substrate 100 having an insulating surface, a scanning line side input terminal 103, and a signal line side. An input terminal 104 is formed. The number of pixels may be provided in accordance with various standards. For XGA, 1024 × 768 × 3 (RGB), for UXGA, 1600 × 1200 × 3 (RGB), and for full specification high vision, 1920 × 1080. X3 (RGB) may be used.

The pixels 102 are arranged in a matrix by crossing a scanning line extending from the scanning line side input terminal 103 in the driving circuit and a signal line extending from the signal line side input terminal 104. The extending scanning line transmits a signal to the gate electrode of the thin film transistor provided in the pixel 102, and the extending signal line is electrically connected to transmit a signal to the source electrode or the drain electrode of the thin film transistor. Each of the pixels 102 includes a switching element and a pixel electrode connected to the switching element. A typical example of the switching element is a TFT. By connecting the gate electrode side of the TFT to a scanning line and the source or drain side to a signal line, each pixel can be controlled independently by a signal input from the outside. Yes.
In addition, a switching element, a TFT as a typical example, can be provided in the driver circuit. The TFT in the driver circuit can have the same structure as the TFT of the pixel 102 and can be manufactured at the same time.

  A TFT includes a semiconductor layer, a gate insulating layer, and a gate electrode layer as main components, and a wiring layer connected to a source region and a drain region formed in the semiconductor layer is attached to the TFT. Structurally, the top gate type in which the semiconductor layer, the gate insulating layer and the gate electrode layer are arranged from the substrate side, and the bottom gate type in which the gate electrode layer, the gate insulating layer and the semiconductor layer are arranged from the substrate side are representative. In the present invention, any of those structures may be used.

  A material for forming a semiconductor is an amorphous semiconductor (hereinafter also referred to as “AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane. A polycrystalline semiconductor crystallized using thermal energy, a semi-amorphous (also referred to as microcrystal or microcrystal, hereinafter referred to as “SAS”) semiconductor, or the like can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. At least 1 atomic% or more of hydrogen or halogen is contained as a neutralizing agent for dangling bonds. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silicide gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times. The pressure is generally in the range of 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300 ° C. or less. As an impurity element in the film, impurities of atmospheric components such as oxygen, nitrogen, and carbon are desirably 1 × 10 ²⁰ atoms / cm ³ or less, and in particular, the oxygen concentration is preferably 5 × 10 ¹⁹ atoms / cm ³ or less. Is 1 × 10 ¹⁹ atoms / cm ³ or less.

  As a conductive material for forming a wiring layer with a droplet discharge device, Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum), and Cu are coated with Ag. A composition mainly composed of metal particles such as particles can be used. Alternatively, light-transmitting indium tin oxide (ITO) and indium tin oxide containing silicon oxide (ITSO) may be combined. In particular, it is not preferable to reduce the resistance of the gate wiring layer, and it is preferable to use a material in which any one of gold, silver, and copper is dissolved or dispersed in consideration of the specific resistance value. More preferably, low resistance silver or copper may be used.

  When silver is used as the conductive material for forming the wiring layer, it is expensive in cost, so if a line with a width of several microns is used in the droplet discharge device in the future, a plating process such as copper plating will be combined. The required line width is sufficient. When plating, not only a method of immersing a large substrate in a liquid tank such as a pool, but also a method of performing plating while flowing a plating solution to the large substrate may be adopted.

  In order to improve the adhesion between the substrate, the organic and inorganic interlayer insulating films, the conductive film and the conductive material for forming the wiring layer, Ti (titanium), W (tungsten) is formed by a method such as sputtering or vapor deposition. Cr (chromium), Al (aluminum), Ta (tantalum), Ni (nickel), Zr (zirconium), Hf (hafnium), V (vanadium), Ir (iridium), Nb (niobium), Pd (palladium) , Pt (platinum), Mo (molybdenum), Co (cobalt), or Rh (rhodium) metal material may be used to form an 0.01-10 nm adhesion improving layer. It is preferable to pre-treat the surface. . It is also possible to form a TiOx photocatalytic layer instead of the metal material. These adhesion improving layers are not only formed under the conductive material layer, but also have improved conductivity with organic and inorganic interlayer insulating films and conductive films formed over the conductive material layer. You may form in the material layer upper layer.

  FIG. 1 shows a configuration of a liquid crystal display device in which signals input to scanning lines and signal lines are controlled by an external driving circuit. As shown in FIG. 2, a driver IC 105 is formed by COG (Chip on Glass). , 106 may be mounted on the substrate 100. The driver IC may be formed on a single crystal semiconductor substrate or may be a circuit in which a TFT is formed on a glass substrate.

  In the case where a TFT provided for a pixel is formed using SAS, a scanning line side driver circuit 107 can be formed over the substrate 100 and integrated as shown in FIG. Reference numeral 108 denotes a protection diode.

  One mode of a droplet discharge device used for forming a pattern is shown in FIG. The individual heads 1405 of the droplet discharge means 1403 are connected to the control means 1407, which can draw a pre-programmed pattern under the control of the computer 1410. When the interlayer insulating film is discharged over a wide range, multiple thin lines may be drawn using the same material in order to improve throughput. The drawing timing may be performed with reference to a marker 1411 formed on the substrate 1400, for example. Alternatively, the reference point may be determined based on the edge of the substrate 1400. This is detected by an imaging means 1404 such as a CCD, and converted into a digital signal by the image processing means 1409 is recognized by the computer 1410 to generate a control signal and sent to the control means 1407. Of course, the information on the pattern to be formed on the substrate 1400 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and each head 1405 of the droplet discharge means 1403 is sent. Can be controlled individually.

  In the case of accommodating a large substrate, the size of the droplet discharge means 1403 may be the same as the maximum width of the liquid crystal display device to be created. If the size of the droplet discharge means 1403 is the same as the maximum width of the liquid crystal display device that creates the liquid crystal display device, the liquid crystal display device can be efficiently produced.

  Next, details of the pixel 102 will be described in accordance with a manufacturing process using a droplet discharge method.

(First embodiment)
As a first embodiment, a method for manufacturing a channel protective thin film transistor will be described.

  4 to 6 show a process of forming a gate electrode layer and a gate wiring layer connected to the gate electrode layer on the substrate 100 by a droplet discharge method.

  The substrate 100 has a heat resistance capable of withstanding the processing temperature of this manufacturing process in addition to a non-alkali glass substrate manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, or a ceramic substrate. A plastic substrate or the like can be used. Alternatively, a substrate in which an insulating layer is provided on the surface of a semiconductor substrate such as single crystal silicon or a metal substrate such as stainless steel may be used.

  On the substrate 100, Ti (titanium), W (tungsten), Cr (chromium), Al (aluminum), Ta (tantalum), Ni (nickel), Zr (zirconium) are formed by a method such as sputtering or vapor deposition. , Hf (hafnium), V (vanadium), Ir (iridium), Nb (niobium), Pd (palladium), Pt (platinum), Mo (molybdenum), Co (cobalt) or Rh (rhodium) metal materials and TiOx It is preferable to form the adhesion improving layer 201 formed of a metal oxide material such as (see FIG. 4A). The adhesion improving layer 201 may be formed with a thickness of 0.01 to 10 nm, but may be formed extremely thin, and thus does not necessarily have a layer structure. That is, it is preferable to perform pretreatment on a formation surface such as a gate electrode layer. Note that if sufficient adhesion can be obtained, the gate electrode layer may be directly formed over the substrate 100 by omitting this.

  The above-mentioned adhesion improving layer 201 is used not only for the purpose of improving the adhesion between the substrate 100 and the gate wiring layer 202 but also appropriately used for improving the adhesion of all the formation layers formed below. Also good.

  A composition containing a conductive material is selectively discharged over the adhesion improving layer 201 by a droplet discharge method, so that the gate wiring layer 202 and the gate electrode layer 203 are formed (see FIG. 4B). As the conductive material for forming these layers, a composition mainly composed of metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum) is used. be able to. Alternatively, light-transmitting indium tin oxide (ITO) and indium tin oxide containing silicon oxide (ITSO) may be combined. In particular, it is not preferable to reduce the resistance of the gate wiring layer, and it is preferable to use a material in which any one of gold, silver, and copper is dissolved or dispersed in consideration of the specific resistance value. More preferably, low resistance silver or copper may be used. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. The solvent corresponds to esters such as butyl acetate, alcohols such as isopropyl alcohol, organic solvents such as acetone, and the like. The surface tension and the viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  The diameter of the nozzle used in the droplet discharge method is set to 0.02 to 100 μm (preferably 30 μm or less), and the discharge amount of the composition discharged from the nozzle is 0.001 pl to 100 pl (preferably 10 pl or less). ) Is preferable. There are two types of droplet discharge methods, an on-demand type and a continuous type, and either method may be used. Furthermore, the nozzle used in the droplet discharge method includes a piezoelectric method that utilizes the property of being deformed by voltage application of a piezoelectric body, and a heating method that discharges the composition by boiling the composition with a heater provided in the nozzle. Either of these methods may be used. The distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop it at a desired location, and is preferably set to about 0.1 to 3 mm (preferably 1 mm or less). . While maintaining the relative distance between the nozzle and the object to be processed, one of the nozzle and the object to be processed moves to draw a desired pattern. In addition, plasma treatment may be performed on the surface of the object to be processed before the composition is discharged. This is to take advantage of the fact that the surface of the workpiece becomes hydrophilic or lyophobic when the plasma treatment is performed. For example, it becomes hydrophilic with respect to pure water and becomes lyophobic with respect to a paste using an alcohol as a solvent.

  The step of discharging the composition may be performed under reduced pressure. This is because the solvent of the composition volatilizes before the composition is discharged and landed on the object to be processed, and the subsequent drying and firing steps can be omitted or shortened. After discharge of the composition, one or both of drying and baking steps are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. The drying and firing steps are both heat treatment steps. For example, the drying is performed at 100 degrees for 3 minutes, and the firing is performed at 200 to 350 degrees for 15 minutes to 120 minutes. Time is different. In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is 100 to 800 degrees (preferably 200 to 350 degrees). And By this step, the solvent in the composition is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and shrunk to accelerate fusion and fusion. The atmosphere is an oxygen atmosphere, a nitrogen atmosphere or air. However, it is preferable to perform in an oxygen atmosphere in which the solvent in which the metal element is decomposed or dispersed is easily removed.

For the laser light irradiation, a continuous wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and a YAG laser, and examples of the latter solid-state laser include a laser using a crystal such as YAG or YVO ₄ doped with Cr, Nd, or the like. Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. In addition, a so-called hybrid laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds. Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature, from several microseconds to several minutes. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, there is an advantage that only the outermost thin film can be heated substantially without affecting the lower layer film.

  After forming the gate wiring layer 202 and the gate electrode layer 203, it is desirable to perform one of the following two processes as the treatment of the adhesion improving layer 201 exposed on the surface.

  The first method is a step of insulating the adhesion improving layer 201 that does not overlap with the gate wiring layer 202 and the gate electrode layer 203 to form the insulator layer 204 (see FIG. 4C). Here, the adhesion improving layer 201 which does not overlap with the gate wiring layer 202 and the gate electrode layer 203 is oxidized and insulated. As described above, when the adhesion improving layer 201 is insulated, it is preferable to form the adhesion improving layer 201 with a thickness of 0.01 to 10 nm. Cheap. As a method of oxidizing, a method of exposing to an oxygen atmosphere or a method of performing heat treatment may be used.

  The second method is a step of etching and removing the adhesion improving layer 201 using the gate wiring layer 202 and the gate electrode layer 203 as a mask. When this step is used, there is no restriction on the thickness of the adhesion improving layer 201.

  Next, a gate insulating layer is formed with a single layer or a stacked structure over the gate electrode layer and the gate wiring layer by a plasma CVD method or a sputtering method (see FIG. 4D). In a particularly preferable mode, a three-layered structure including an insulator layer 205 made of silicon nitride, an insulator layer 206 made of silicon oxide, and an insulator layer 207 made of silicon nitride corresponds to the gate insulating film. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film. By forming the first layer in contact with the gate wiring layer 202 and the gate electrode layer 203 with silicon nitride or silicon nitride oxide, deterioration due to oxidation can be prevented.

  Next, the semiconductor layer 208 is formed over the gate insulating layer (see FIG. 4D). The semiconductor layer 208 is formed by AS or SAS manufactured by a vapor deposition method using a semiconductor material gas typified by silane or germane, or a sputtering method using a Si target.

When the plasma CVD method is used, AS is formed using SiH ₄ which is a semiconductor material gas or a mixed gas of SiH ₄ and H ₂ . SAS is a SiH ₄ mixture was diluted 3-fold to 1000-fold with H ₂ gas, or the gas flow rate ratio of Si ₂ H ₆ and GeF ₄ Si ₂ H ₆ pairs GeF ₄ in the 20-40 versus 0.9 When diluted, a SAS having a Si composition ratio of 80% or more can be obtained. In particular, the latter is preferable because the semiconductor layer 208 can have crystallinity from the interface with the base.

  In the steps so far, the insulator layer 205 to the semiconductor layer 208 can be continuously formed without being exposed to the air. In other words, each stacked interface can be formed without being contaminated by atmospheric components or contaminating impurity elements floating in the atmosphere, so that variations in TFT characteristics can be reduced.

  Next, a composition is selectively discharged over the semiconductor layer 208 to a position facing the gate electrode layer 203, that is, overlapping with the gate electrode layer 203, so that a channel protective film 209 is formed (see FIG. 4E). The channel protective film 209 uses a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. And formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  Subsequently, an n-type semiconductor layer 210 is formed over the semiconductor layer 208 and the channel protective film 209 (see FIG. 5A). The n-type semiconductor layer 210 may be formed using silane gas and phosphine gas, and may be formed using AS or SAS.

  Next, a mask 211 is formed over the semiconductor layer 210 by a droplet discharge method. Using this mask 211, the n-type semiconductor layer 210, the semiconductor layer 208, the insulator layer 205, the insulator layer 206 made of silicon oxide, and the insulator layer 207 made of silicon nitride are etched, and the semiconductor layer 212 is etched. A semiconductor layer 213 having one conductivity is formed (see FIGS. 5B and 5C). At this time, the end of the semiconductor layer is etched so as to coincide with the end of the gate insulating layer. In other words, the end of the semiconductor layer is etched so as not to exceed the end of the gate insulating layer. The etched semiconductor layer is called an island-shaped semiconductor layer, and the etched gate insulating film is called an island-shaped gate insulating film.

  Subsequently, after the mask 211 is removed, the composition is such that the gate wiring layer 202 and the source wiring layer 215 to be discharged in the subsequent process are opposed to each other, that is, the gate wiring layer and the source wiring layer are not short-circuited. A material is selectively discharged to form an interlayer insulating film 214 (see FIG. 5D). For the interlayer insulating film 214, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. And formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like. The surface can be planarized by the interlayer insulating film.

  Next, a composition containing a conductive material is selectively discharged, so that source and drain wiring layers 215 and 216 are formed by a droplet discharge method (see FIG. 5E).

  Subsequently, using the source and drain wiring layers 215 and 216 as a mask, the n-type semiconductor layer 210 on the channel protective film 209 is etched to form n-type semiconductor layers 217 and 218 that form source and drain regions. (See FIG. 6A). Wiring resistance can be reduced by the n-type semiconductor layers 217 and 218 forming the source and drain regions. Although the source and drain wiring layers are used as masks in this embodiment mode, the present invention is not limited to this, and a new mask may be provided.

  Next, an insulating layer 219 functioning as a passivation film is formed over the entire surface for the purpose of protecting the channel formation region (see FIG. 6B). Preferably, a silicon nitride film using a plasma CVD method or a sputtering method is used. This film is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and is required to be a dense film. For this purpose, when a silicon nitride film is formed by high-frequency sputtering using a sputtering gas in which nitrogen and a rare gas element such as argon are mixed with silicon as a target, densification is promoted by including the rare gas element in the film. This is preferable.

  Subsequently, an insulator layer 220 is formed over the entire surface of the substrate (see FIG. 6C). This insulator layer 220 is made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, amonium oxynitride or other inorganic insulating materials, or acrylic acid, methacrylic acid and derivatives thereof, or polyimide. Inorganic siloxanes containing Si—O—Si bonds among silicon, oxygen, and hydrogen compounds formed from aromatic polyamides, heat-resistant polymers such as polybenzimidazole, or siloxane-based materials as starting materials The upper hydrogen can be formed of an organic siloxane-based insulating material substituted with an organic group such as methyl or phenyl. When a photosensitive or non-photosensitive material such as acrylic or polyimide is used, the side surface has a shape in which the curvature radius changes continuously, and the upper thin film is formed without being cut off.

  The insulator layer 220 is formed on the entire surface by a droplet discharge method, a spin coating method, or a dip method. Thereafter, an opening is formed at a predetermined location by etching or the like. At this time, the protective layer 219 under the insulator layer 220 is etched at the same time, so that the gate wiring layer 202 and the source and drain wiring layers 215 and 216 are processed to be exposed. In addition, it is preferable that the insulator layer 220 be selectively formed by a droplet discharge method because etching of the insulator layer 220 is not necessarily required.

The following process may be used as a method for forming the opening in the insulator layer 220. First, before the insulator layer 220 is formed, a liquid repellent treatment is performed by coating the entire surface of the substrate with a fluorine-based coupling agent such as fluoroalkylsilane or a liquid repellent treatment agent such as an organic material containing fluorine such as CHF ₃ . Subsequently, a mask material is applied to a place where an opening is to be formed, and treatment such as O ₂ ashing is performed to remove the liquid repellent other than the place where the mask is formed. Next, the mask is removed, and the insulator layer 220 is applied to the entire surface of the substrate by a spin coating method, a dip method, or a droplet discharge method. Since the insulator layer 220 is not formed in the portion subjected to the liquid repellent treatment, an opening is formed. When coating the liquid repellent agent, if the liquid repellent agent is selectively applied only to the opening using a droplet discharge device, the steps of mask formation, liquid repellent removal, and mask removal are as follows. It becomes unnecessary.

Next, a composition containing a conductive material is selectively discharged so as to be electrically connected to the drain wiring layer 216 to form a pixel electrode layer 221 corresponding to the pixel electrode (see FIG. 6D). ). In the case of manufacturing a transmissive liquid crystal display device, the pixel electrode layer 221 includes indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), and tin oxide (SnO ₂ ). The pixel electrode may be formed by baking a predetermined pattern with a composition including In the case of manufacturing a reflective liquid crystal display device, the composition is mainly composed of particles of metal such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum). Can be used. As another method, a pixel electrode layer may be formed by forming a transparent conductive film or a light reflective conductive film by a sputtering method, forming a mask pattern by a droplet discharge method, and combining etching processes. 14A shows a planar structure of the same structure, FIG. 14B shows a longitudinal sectional structure corresponding to AB, and FIG. 14C shows a longitudinal sectional structure corresponding to CD. So you can refer to them at the same time.

  Through the above steps, a TFT substrate 200 for a liquid crystal display device in which a bottom gate type (also referred to as an inverted stagger type) TFT and a pixel electrode are connected to the substrate 100 is completed.

  Next, an insulator layer 222 called an alignment film is formed by a printing method or a spin coating method so as to cover the pixel electrode layer 221. Note that the insulator layer 222 can be selectively formed as shown in the figure by using a screen printing method or an offset printing method. Then, rubbing is performed. Subsequently, a sealant 223 is formed in a peripheral region where pixels are formed by a droplet discharge method (see FIG. 13).

  Thereafter, the counter substrate 229 provided with the insulator layer 224 functioning as an alignment film and the conductor layer 225 functioning as a counter electrode and the TFT substrate 200 are bonded to each other through a spacer (not shown), and a liquid crystal is formed in the gap. By providing the layer, a liquid crystal display device can be manufactured (see FIG. 13). The sealant 223 may be mixed with a filler, and the counter substrate 229 may be formed with a color filter, a shielding film (black matrix), or the like. Note that as a method for forming the liquid crystal layer, a dispenser type (dropping type) or a dip type (pumping type) in which liquid crystal is injected using a capillary phenomenon after the counter substrate 229 is attached can be used.

  As described above, in this embodiment mode, the process can be omitted by not using a light exposure process using a photomask. In addition, by forming various patterns directly on the substrate using a droplet discharge method, a liquid crystal display device can be easily manufactured even if a glass substrate of 5th generation or later with one side exceeding 1 m is used. be able to.

(Second Embodiment)
In the first embodiment, a configuration as a channel protection type is shown, but as another mode, a configuration as a channel etch type in which a channel protection layer is not formed is shown.

  A composition containing a conductive material is discharged over the substrate 100 by a droplet discharge method, so that the gate wiring layer 202 and the gate electrode layer 203 are formed. Next, a gate insulating layer is formed with a single layer or a stacked structure by a plasma CVD method or a sputtering method. In a particularly preferable mode, a three-layered structure including an insulator layer 205 made of silicon nitride, an insulator layer 206 made of silicon oxide, and an insulator layer 207 made of silicon nitride corresponds to the gate insulating film. Further, a semiconductor layer 208 that functions as an active layer is formed. The process up to the step of FIG. 4D is the same as that of the first embodiment.

  Next, an n-type semiconductor layer 301 is formed over the semiconductor layer 208 (see FIG. 7A). The n-type semiconductor layer 301 may be formed using silane gas and phosphine gas, and may be formed using AS or SAS.

  In the steps so far, the insulator layer 205 to the semiconductor layer 301 can be continuously formed without being exposed to the air. In other words, each stacked interface can be formed without being contaminated by atmospheric components or contaminating impurity elements floating in the atmosphere, so that variations in TFT characteristics can be reduced.

  Next, a composition 302 is selectively discharged over the semiconductor layer 301 by a droplet discharge method to form a mask 302 (see FIG. 7B). Using this mask 302, the semiconductor layer 208, the n-type semiconductor layer 301, and the gate insulating layers 205, 206, and 207 are simultaneously etched to form the semiconductor layer 303 and the n-type semiconductor layer 304. (See FIG. 7C).

  Subsequently, after removing the mask 302, the composition is selectively discharged to a position opposite to the gate wiring layer 202 and the source wiring layer 306 to be discharged in a subsequent process, whereby an interlayer film 305 is formed ( (See FIG. 7D). For the interlayer film 305, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. And formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  Next, a composition containing a conductive material is discharged over the semiconductor layer 304 to form source and drain wiring layers 306 and 307 (see FIG. 7E).

  Subsequently, the n-type semiconductor layer 304 is etched using the source and drain wiring layers 306 and 307 as masks to form semiconductor layers 308 and 309. At this time, the semiconductor layer 303 is also slightly etched to form the semiconductor layer 310 (see FIG. 8A). The subsequent steps are the same as those in the first embodiment. (See FIGS. 8B to 8D)

  Through the above steps, a TFT substrate 300 for a liquid crystal display device in which a bottom gate type (also referred to as an inverted stagger type) channel etch type TFT and a pixel electrode layer 221 are connected to the substrate 100 is completed. 15A shows a planar structure of the same structure, FIG. 15B shows a longitudinal sectional structure corresponding to AB, and FIG. 15C shows a longitudinal sectional structure corresponding to CD. So you can refer to them at the same time.

(Third embodiment)
In the first and second embodiments, the entire surface of the substrate is covered with the protective layer 219 and the insulator layer 220. However, as the third embodiment, only the TFT and the wiring layer are protected and insulated. The form covered with the body layer 701 is shown.

  The process up to forming the insulator layer 219 for the purpose of protecting the channel formation region after forming the semiconductor layer over the substrate 100 is the same as that in the first embodiment. At this time, in the case where a semiconductor layer is formed by a channel etch type, the second embodiment may be used.

  Next, the insulator layer 701 is selectively formed only over the semiconductor layer of the substrate, the gate wiring layer 202, and the source and drain wiring layers 215 and 216 by a droplet discharge method (see FIG. 9A). The insulator layer 701 includes a portion electrically connected to the pixel electrode layer 221 formed in a later step on the drain wiring layer 216, and an external wiring (not shown) on the gate wiring layer 202 and the source wiring layer 215. It is not formed on the part that is electrically connected to the). The insulator layer 701 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, amonium oxynitride, other inorganic insulating materials, acrylic acid, methacrylic acid, and derivatives thereof, or polyimide (polyimide), Inorganic siloxanes containing Si—O—Si bonds among silicon, oxygen, and hydrogen compounds formed from aromatic polyamides, heat-resistant polymers such as polybenzimidazole, or siloxane-based materials as starting materials The upper hydrogen can be formed of an organic siloxane-based insulating material substituted with an organic group such as methyl or phenyl. When a photosensitive or non-photosensitive material such as acrylic or polyimide is used, the side surface has a shape in which the curvature radius changes continuously, and the upper thin film is formed without being cut off.

  Subsequently, using the insulator layer 701 as a mask, the protective layer 219 is etched with the insulating layer by dry etching or wet etching to form an opening (see FIG. 9B). At this time, predetermined portions of the gate wiring layer 202 and the source and drain wiring layers 215 and 216 under the protective layer 219 are exposed.

Next, a composition containing a conductive material is selectively discharged so as to be electrically connected to the drain wiring layer 216, so that a pixel electrode layer 702 corresponding to the pixel electrode is formed (see FIG. 9C). ). In the case of manufacturing a transmissive liquid crystal display device, the pixel electrode layer 702 includes indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), and tin oxide (SnO ₂ ). The pixel electrode may be formed by baking a predetermined pattern with a composition including In the case of manufacturing a reflective liquid crystal display device, particles of metal such as Ag (silver), Au (gold), Cu (copper)), W (tungsten), and Al (aluminum) are mainly used. Compositions can be used. As another method, a pixel electrode layer may be formed by forming a transparent conductive film or a light reflective conductive film by a sputtering method, forming a mask pattern by a droplet discharge method, and combining etching processes.

  Through the above steps, a TFT substrate 700 for a liquid crystal display device in which a bottom gate type (also referred to as an inverted stagger type) TFT and a pixel electrode are connected to the substrate 100 is completed. Note that FIG. 16A shows a planar structure of the same structure, FIG. 16B shows a longitudinal sectional structure corresponding to AB, and FIG. 16C shows a longitudinal sectional structure corresponding to CD. So you can refer to them at the same time.

(Fourth embodiment)
As a fourth embodiment, a mode in which the pixel electrode layer 501 is below the drain wiring 516 is shown. As an example of the embodiment, a channel protection type having an insulator layer (hereinafter also referred to as a channel protection layer) for the purpose of protecting the channel formation region is shown. However, as in the third embodiment, a channel is used. It is also possible to form a channel etch type without a channel protective layer in the formation region.

  10 to 12 show a process of forming a gate electrode layer and a gate wiring layer connected to the gate electrode layer on the substrate 100 by a droplet discharge method.

  An adhesion improving layer 201 is formed over the substrate 100 by a sputtering method, an evaporation method, or the like (see FIG. 10A). Note that if sufficient adhesion can be obtained, the gate electrode layer may be directly formed over the substrate 100 by omitting this.

A composition containing a conductive material is selectively discharged over the adhesion improving layer 201 to form a pixel electrode layer 501 corresponding to a pixel electrode (see FIG. 10B). In the case of manufacturing a transmissive liquid crystal display device, the pixel electrode layer 501 includes indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), and tin oxide (SnO ₂ ). The pixel electrode may be formed by baking a predetermined pattern with a composition containing the above. In the case of manufacturing a reflective liquid crystal display device, particles of metal such as Ag (silver), Au (gold), Cu (copper)), W (tungsten), and Al (aluminum) are used as the main component. Compositions can be used. As another method, a pixel electrode layer may be formed by forming a transparent conductive film or a light reflective conductive film by a sputtering method, forming a mask pattern by a droplet discharge method, and combining etching processes. In addition, the pixel electrode layer 501 can be formed below the adhesion improving layer 201 before the adhesion improving layer 201 is formed.

  A composition containing a conductive material is discharged over the adhesion improving layer 201 by a droplet discharge method, so that the gate wiring layer 502 and the gate electrode layer 503 are formed (see FIG. 10C). As a conductive material for forming these layers, a composition mainly composed of metal particles such as Ag (silver), Au (gold), Cu (copper)), W (tungsten), and Al (aluminum) is used. Can be used. Alternatively, light-transmitting indium tin oxide (ITO) and indium tin oxide containing silicon oxide (ITSO) may be combined. In particular, it is not preferable to reduce the resistance of the gate wiring layer, and it is preferable to use a material in which any one of gold, silver, and copper is dissolved or dispersed in consideration of the specific resistance value. More preferably, low resistance silver or copper may be used. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. The solvent corresponds to esters such as butyl acetate, alcohols such as isopropyl alcohol, organic solvents such as acetone, and the like. The surface tension and the viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  After forming the gate wiring layer 502 and the gate electrode layer 503, it is desirable to perform one of the following two processes as the treatment of the adhesion improving layer 201 exposed on the surface.

  The first method is a step of insulating the adhesion improving layer 201 which does not overlap with the gate wiring layer 502, the gate electrode layer 503, and the pixel electrode layer 501 to form the insulator layer 504 (FIG. 10D )reference). Here, the adhesion improving layer 201 which does not overlap with the gate wiring layer 502 and the gate electrode layer 503 is oxidized and insulated. As described above, when the adhesion improving layer 201 is insulated, it is preferable to form the adhesion improving layer 201 with a thickness of 0.01 to 10 nm. Cheap. As a method of oxidizing, a method of exposing to an oxygen atmosphere or a method of performing heat treatment may be used.

  As a second method, the adhesion improving layer 201 is removed by etching using the gate wiring layer 502, the gate electrode layer 503, and the pixel electrode layer 501 as a mask. When this step is used, there is no restriction on the thickness of the adhesion improving layer 201.

  Next, a gate insulating layer is formed with a single layer or a stacked structure over the gate electrode layer and the gate wiring layer by a plasma CVD method or a sputtering method (see FIG. 10E). In a particularly preferable mode, a three-layered structure including an insulator layer 505 made of silicon nitride, an insulator layer 506 made of silicon oxide, and an insulator layer 507 made of silicon nitride corresponds to the gate insulating film. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film. By forming the first layer in contact with the gate wiring layer 502 and the gate electrode layer 503 with silicon nitride or silicon nitride oxide, deterioration due to oxidation can be prevented.

  Next, a semiconductor layer 508 is formed over the gate insulating layer (see FIG. 10E). The semiconductor layer 508 is formed by AS or SAS manufactured by a vapor deposition method using a semiconductor material gas typified by silane or germane, or a sputtering method using a Si target.

When the plasma CVD method is used, AS is formed using SiH ₄ which is a semiconductor material gas or a mixed gas of SiH ₄ and H ₂ . SAS is a SiH ₄ mixture was diluted 3-fold to 1000-fold with H ₂ gas, or the gas flow rate ratio of Si ₂ H ₆ and GeF ₄ Si ₂ H ₆ pairs GeF ₄ in the 20-40 versus 0.9 When diluted, a SAS having a Si composition ratio of 80% or more can be obtained. In particular, the latter is preferable because the semiconductor layer 208 can have crystallinity from the interface with the base.

  In the steps so far, the insulator layer 505 to the semiconductor layer 508 can be continuously formed without being exposed to the air. In other words, each stacked interface can be formed without being contaminated by atmospheric components or contaminating impurity elements floating in the atmosphere, so that variations in TFT characteristics can be reduced.

  Next, the composition is selectively discharged over the semiconductor layer 508 to a position facing the gate electrode layer 503, that is, a position overlapping with the gate electrode layer 503, so that a channel protective film 509 is formed (see FIG. 11A). For the channel protective film 509, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. And formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  Subsequently, an n-type semiconductor layer 510 is formed over the semiconductor layer 508 and the channel protective film 509 (see FIG. 11B). The n-type semiconductor layer 510 may be formed using silane gas and phosphine gas, and may be formed using AS or SAS.

  Next, a mask 511 is formed over the semiconductor layer 510 by a droplet discharge method (see FIG. 11C). Using this mask 511, the n-type semiconductor layer 510, the semiconductor layer 508, the insulator layer 505, the insulator layer 506 made of silicon oxide, and the insulator layer 507 made of silicon nitride are etched, and the semiconductor layer 512 is etched. A semiconductor layer 513 having one conductivity is formed (see FIG. 11D). At this time, the end of the semiconductor layer is etched so as to coincide with the end of the gate insulating layer. In other words, the end of the semiconductor layer is etched so as not to exceed the end of the gate insulating layer. The etched semiconductor layer is also called an island-shaped semiconductor layer, and the etched gate insulating film is also called an island-shaped gate insulating film.

  Subsequently, after removing the mask 511, the composition is placed at a position facing the gate wiring layer 502 and the source wiring layer 515 to be discharged in the subsequent process, that is, a position where the gate wiring layer and the source wiring layer are not short-circuited. By selectively discharging, an interlayer insulating film 514 is formed (see FIG. 11E). For the interlayer insulating film 514, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. And formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  Next, a composition containing a conductive material is selectively discharged, so that source and drain wiring layers 515 and 516 are formed by a droplet discharge method (see FIG. 12A). As a conductive material for forming the wiring layer, a composition mainly composed of metal particles such as Ag (silver), Au (gold), Cu (copper)), W (tungsten), and Al (aluminum) is used. Can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined.

  Subsequently, using the source and drain wiring layers 515 and 516 as masks, the semiconductor layer 513 having one conductivity on the channel protective film 509 is etched to form n-type semiconductor layers 517 and 518 forming source and drain regions. It is formed (see FIG. 12B). Wiring resistance can be reduced by the n-type semiconductor layers 516 and 517 forming the source and drain regions. Although the source and drain wiring layers are used as masks in this embodiment mode, the present invention is not limited to this, and a new mask may be provided.

  Next, an insulator layer 519 functioning as a passivation film is formed for the purpose of protecting the channel formation region (see FIG. 12C). Preferably, a silicon nitride film using a plasma CVD method or a sputtering method is used. This film is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and is required to be a dense film. For this purpose, a silicon nitride film is formed by high-frequency sputtering using a sputtering gas in which nitrogen and a rare gas element such as argon are mixed with silicon as a target, and densification is promoted by including the rare gas element in the film. This is preferable.

  Subsequently, an insulating layer 520 is selectively formed only over the semiconductor layer, the gate wiring layer 502, and the source and drain wiring layers 515 and 516 of the substrate by a droplet discharge method (see FIG. 12D). The insulator layer 520 is electrically connected to a portion electrically connected to the pixel electrode layer 521 on the drain wiring layer 516, and to an external wiring (not shown) on the gate wiring layer 502 and the source wiring layer 515. Do not form on the part. The insulator layer 520 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, amonium oxynitride, other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, or polyimide (polyimide), Inorganic siloxanes containing Si—O—Si bonds among silicon, oxygen, and hydrogen compounds formed from aromatic polyamides, heat-resistant polymers such as polybenzimidazole, or siloxane-based materials as starting materials The upper hydrogen can be formed of an organic siloxane-based insulating material substituted with an organic group such as methyl or phenyl.

  Subsequently, using the insulator layer 520 as a mask, the insulator layer 519 is etched by dry etching or wet etching to form an opening (see FIG. 12E). At this time, predetermined portions of the gate wiring layer 502, the source and drain wiring layers 515 and 516, and the pixel electrode layer 501 under the insulator layer 519 are exposed.

  Through the above steps, a TFT substrate 500 for a liquid crystal display device in which a bottom gate type (also referred to as an inverted stagger type) TFT and a pixel electrode are connected to the substrate 100 is completed. Note that FIG. 17A shows a planar structure of the same structure, FIG. 17B shows a longitudinal sectional structure corresponding to AB, and FIG. 17C shows a longitudinal sectional structure corresponding to CD. So you can refer to them at the same time.

  In the liquid crystal display device manufactured according to the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, by forming the semiconductor layer with SAS, FIG. As described, a driving circuit on the scanning line side can be formed over the substrate 100.

FIG. 22 shows a block diagram of a scanning line side driving circuit constituted by an n-channel TFT using SAS capable of obtaining a field effect mobility of 1 to 15 cm ² / V · sec.

  In FIG. 22, a block denoted by 1500 corresponds to a pulse output circuit that outputs a sampling pulse for one stage, and the shift register includes n pulse output circuits. Reference numeral 1501 denotes a buffer circuit to which a pixel 1502 (corresponding to the pixel 102 in FIG. 3) is connected.

  FIG. 23 shows a specific configuration of the pulse output circuit 1500, and the circuit is configured by n-channel TFTs 601 to 613. At this time, the size of the TFT may be determined in consideration of the operating characteristics of the n-channel TFT using SAS. For example, if the channel length is 8 μm, the channel width can be set in the range of 10 to 80 μm.

  A specific structure of the buffer circuit 1501 is shown in FIG. Similarly, the buffer circuit is composed of n-channel TFTs 620 to 635. At this time, the size of the TFT may be determined in consideration of the operating characteristics of the n-channel TFT using SAS. For example, if the channel length is 10 μm, the channel width is set in the range of 10 to 1800 μm.

  In order to realize such a circuit, the TFTs need to be connected to each other by wiring, and a configuration example of the wiring in that case is shown in FIG. In FIG. 18, as in the first embodiment, the gate electrode layer 203, the gate insulating layer (the insulator layer 205 made of silicon nitride, the insulator layer 206 made of silicon oxide, and the insulator layer 207 made of silicon nitride are shown. 3 layers), a semiconductor layer 212 formed of SAS, an insulator layer 209 that forms a channel protective layer, n-type semiconductor layers 217 and 218 that form a source and a drain, and source and drain wiring layers 215 and 216 The state where is formed is shown. In this case, connection wiring layers 232, 233, and 234 are formed on the substrate 100 in the same process as the gate electrode layer 203. Then, a part of the gate insulating layer is etched so that the connection wiring layers 232, 233, and 234 are exposed, and a TFT is appropriately formed by the source and drain wiring layers 215 and 216 and the connection wiring layer 235 formed in the same process. Various circuits can be realized by connection.

  One mode in which protective diodes are provided in the scanning line side input terminal portion and the signal line side input terminal portion will be described with reference to FIG. In FIG. 28, the pixel 102 is provided with a TFT 260 and a capacitor 265. This TFT has the same configuration as that of the first embodiment. Reference numeral 1224 denotes a pixel electrode, and 1204 denotes a capacitor line.

  Protection diodes 261 and 262 are provided at the signal line side input terminal portion. This protection diode is manufactured in the same process as the TFT 260, and is operated as a diode by connecting the gate and one of the drain and the source. An equivalent circuit diagram of the top view shown in FIG. 28 is shown in FIG.

  The protection diode 261 includes a gate electrode layer 250, a semiconductor layer 251, a channel protection insulating layer 252, and wiring layers 249 and 253. The protective diode 262 has a similar structure. Common potential lines 254 and 255 connected to the protection diode are formed in the same layer as the gate electrode layer. Therefore, in order to be electrically connected to the wiring layer 253, it is necessary to form a contact hole in the gate insulating layer.

  The contact hole for the gate insulating layer may be etched by forming a mask layer by a droplet discharge method. In this case, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

  The protection diode 261 or 262 is formed in the same layer as the source and drain wiring layers 215 and 216 in the TFT 260 and has a structure in which the signal wiring layer 256 connected to the source and drain wiring layers 256 is connected to the source or drain side.

  The input terminal portion on the scanning signal line side has a similar structure, and is provided with protective diodes 263 and 264 and a wiring layer 256. Thus, according to the present invention, the protection diode provided in the input stage can be formed simultaneously. Note that the position where the protective diode is inserted is not limited to this embodiment mode, and can be provided between the driver circuit and the pixel as described in FIG.

  Next, an aspect in which a driver circuit for driving is mounted on the liquid crystal display device manufactured according to the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment. This will be described with reference to FIGS.

  First, a display device employing a COG method is described with reference to FIG. Over the substrate 1001, a pixel region 1002 for displaying information such as characters and images, and driving circuits 1003 and 1004 on the scanning side are provided. The substrates 1005 and 1008 provided with a plurality of drive circuits are divided into rectangular shapes, and the divided drive circuits (hereinafter referred to as driver ICs) are mounted on the substrate 1001. FIG. 19A shows a form in which a plurality of driver ICs 1007 and a tape 1006 are mounted on the ends of the driver ICs 1007. FIG. 19B shows a driver IC 1010 and a form in which a tape 1009 is mounted on the tip of the driver IC 1010.

  Next, a display device employing a TAB method is described with reference to FIG. Over the substrate 1001, a pixel region 1002 and driving circuits 1003 and 1004 on the scanning side are provided. FIG. 20A shows a mode in which a plurality of tapes 1006 are attached to a substrate 1001 and a driver IC 1007 is mounted on the tapes 1006. FIG. 20B illustrates a mode in which a tape 1009 is attached to a substrate 1001 and a driver IC 1010 is mounted on the tape 1009. When the latter is adopted, a metal piece or the like for fixing the driver IC 1010 may be attached together due to strength problems.

  A plurality of driver ICs mounted on these liquid crystal display devices are preferably formed on rectangular substrates 1005 and 1008 each having a side of 300 mm to 1000 mm or more from the viewpoint of improving productivity.

  That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit are formed on the substrates 1005 and 1008, and finally divided and taken out. In consideration of the length of one side of the pixel portion and the pixel pitch, the long side of the driver IC has a long side of 15 to 80 mm and a short side of 15 to 80 mm as shown in FIGS. It may be formed in a rectangular shape of 1 to 6 mm, and as shown in FIGS. 19B and 20B, one side of the pixel region 1002 or one side of the pixel region 1002 and each of the driver circuits 1003 and 1004 You may form in the length which added one side.

  The advantage of the external dimensions of the driver IC over the IC chip is the length of the long side. When a driver IC having a long side of 15 to 80 mm is used, the number necessary for mounting corresponding to the pixel region 1002 is used. However, the manufacturing yield can be improved as compared with the case where the IC chip is used. Further, when a driver IC is formed over a glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is not impaired. This is a great advantage compared with the case where the IC chip is taken out from the circular silicon wafer.

  19A and 19B, and FIGS. 20A and 20B, a driver IC 1007 or 1010 in which a driver circuit is formed is mounted in a region outside the pixel region 1002. These driver ICs 1007 or 1010 are drive circuits on the signal line side. In order to form a pixel region corresponding to RGB full color, the number of signal lines in the XGA class is 3072 and the number in the UXGA class is 4800. The signal lines formed in such a number are divided into several blocks at the end of the pixel region 1002 to form lead lines, and are collected according to the pitch of the output terminals of the driver IC 1007 or 1010.

  The driver IC is preferably formed of a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiating continuous-emitting laser light. Therefore, a continuous light emitting solid state laser or gas laser is used as an oscillator for generating the laser light. When a continuous light emission laser is used, a transistor can be formed using a polycrystalline semiconductor layer having a large grain size with few crystal defects. In addition, since the mobility and response speed are good, high-speed driving is possible, the operating frequency of the element can be improved as compared with the prior art, and there is less variation in characteristics, so that high reliability can be obtained. Note that for the purpose of further improving the operating frequency, the channel length direction of the transistor and the scanning direction of the laser light are preferably matched. This is because, in the laser crystallization process using a continuous emission laser, the highest mobility is obtained when the channel length direction of the transistor and the scanning direction of the laser beam with respect to the substrate are substantially parallel (preferably −30 ° to 30 °). It is because it is obtained. Note that the channel length direction corresponds to the direction in which current flows in the channel formation region, in other words, the direction in which charges move. The transistor thus fabricated has an active layer composed of a polycrystalline semiconductor layer in which crystal grains extend in the channel direction, which means that the crystal grain boundaries are formed substantially along the channel direction. means.

  In order to perform laser crystallization, it is preferable to significantly narrow the laser beam, and the width of the beam spot is preferably about 1 to 3 mm, which is the same width of the short side of the driver IC. In order to ensure a sufficient and efficient energy density for the irradiated object, the laser light irradiation region is preferably linear. However, the line shape here does not mean a line in a strict sense, but means a rectangle or an ellipse having a large aspect ratio. For example, the aspect ratio is 2 or more (preferably 10 to 10,000). In this manner, a method for manufacturing a display device with improved productivity can be provided by setting the width of the beam spot of the laser light to the same length as the short side of the driver IC.

  19 and 20, the scanning line driving circuit is formed integrally with the pixel portion, and a driver IC is mounted as a signal line driving circuit. However, the present invention is not limited to this mode, and a driver IC may be mounted as both the scanning line driving circuit and the signal line driving circuit. In that case, the specifications of the driver ICs used on the scanning line side and the signal line side may be different.

In the pixel region 1002, the signal line and the scanning line intersect to form a matrix, and a transistor is arranged corresponding to each intersection. The present invention is characterized in that a TFT using an amorphous semiconductor or a semi-amorphous semiconductor as a channel portion is used as a transistor arranged in the pixel region 1002. The amorphous semiconductor is formed by a method such as a plasma CVD method or a sputtering method. A semi-amorphous semiconductor can be formed by a plasma CVD method at a temperature of 300 ° C. or lower. For example, even a non-alkali glass substrate having an outer dimension of 550 × 650 mm has a film thickness necessary for forming a transistor. Is formed in a short time. Such a feature of the manufacturing technique is effective in manufacturing a large-screen display device. Further, a field effect mobility of 1 to 15 cm ² / V · sec can be obtained by forming a channel formation region with a semi-amorphous TFT. Therefore, this TFT can be used as a switching element for a pixel or an element constituting a driving circuit on the scanning line side. Accordingly, a liquid crystal display device that realizes system-on-panel can be manufactured.

  In FIGS. 19 and 20, it is assumed that the scanning line side driving circuit is integrally formed on the substrate by using the TFT in which the semiconductor layer is formed of SAS according to the third embodiment. When a TFT having a semiconductor layer formed of AS is used, a driver IC may be mounted on both the scanning line side driver circuit and the signal line side driver circuit.

  In that case, it is preferable that the specifications of the driver ICs used on the scanning line side and the signal line side are different. For example, although a transistor constituting the driver IC on the scanning line side is required to have a withstand voltage of about 30 V, the driving frequency is 100 kHz or less, and a relatively high speed operation is not required. Therefore, it is preferable to set the channel length (L) of the transistors forming the driver on the scanning line side to be sufficiently large. On the other hand, it is sufficient for the transistor of the driver IC on the signal line side to have a withstand voltage of about 12V, but the drive frequency is about 65 MHz at 3V, and high speed operation is required. Therefore, it is preferable to set the channel length and the like of the transistors constituting the driver on the micron rule.

  FIG. 21 shows a configuration in which the driver IC is mounted by COG, and shows a case corresponding to the case of the liquid crystal display device shown in FIG. FIG. 21A shows a structure in which a driver IC 106 is mounted on a TFT substrate 200 using an anisotropic conductive material. A pixel portion 101 and a signal line side input terminal 104 (the same applies to the scanning line input terminal 103) are provided on the TFT substrate 200. The counter substrate 229 is bonded to the TFT substrate 200 with a sealing material 226, and a liquid crystal layer 230 is formed therebetween.

  An FPC 812 is bonded to the signal line side input terminal 104 with an anisotropic conductive material. The anisotropic conductive material is composed of a resin 815 and conductive particles 814 having a diameter of several tens to several hundreds μm with Au or the like plated on the surface, and wiring formed on the signal line side input terminal 104 and the FPC 812 by the conductive particles 814. 813 is electrically connected. The driver IC 106 is also bonded to the TFT substrate 200 with an anisotropic conductive material, and the conductive particles 810 mixed in the resin 811 electrically connect the input / output terminal 809 and the signal line side input terminal 104 provided in the driver IC 106. Connected to.

  Further, as shown in FIG. 21B, the driver IC 106 may be fixed to the TFT substrate 200 with an adhesive 816 and the input / output terminal 809 of the driver IC and the signal input terminal 104 may be connected by the Au wire 817. . Then, sealing is performed with a sealing resin 818. Note that the method for mounting the driver IC is not particularly limited, and a known COG method, wire bonding method, or TAB method can be used.

  By setting the thickness of the driver IC to the same thickness as that of the counter substrate, the height between the two becomes substantially the same, which contributes to a reduction in thickness of the entire display device. In addition, since each substrate is made of the same material, thermal stress is not generated even when a temperature change occurs in the display device, and the characteristics of a circuit made of TFTs are not impaired. In addition, the number of driver ICs to be mounted in one pixel region can be reduced by mounting the drive circuit with a driver IC that is longer than the IC chip as shown in this embodiment.

  As described above, a driver circuit can be incorporated in the liquid crystal display device.

  A liquid crystal television receiver can be completed by the liquid crystal display device manufactured according to the seventh embodiment. FIG. 25 is a block diagram showing a main configuration of the liquid crystal television receiver. In the liquid crystal display device, only the pixel portion 401 is formed as shown in FIG. 1, and the scanning line side driver circuit 403 and the signal line side driver circuit 402 are mounted by the TAB method, and FIG. In the case where the pixel portion 401 and the periphery thereof are mounted with the scanning line side driver circuit 403 and the signal line side driver circuit 402 by the COG method, a TFT is formed by SAS as shown in FIG. 401 and the scanning line side driving circuit 403 are integrally formed on the substrate and the signal line side driving circuit 402 is separately mounted as a driver IC. However, any form may be employed.

  As other external circuit configurations, on the video signal input side, among the signals received by the tuner 404, the video signal amplification circuit 405 that amplifies the video signal, and the signal output therefrom is each of red, green, and blue colors. And a control circuit 407 for converting the video signal into an input specification of the driver IC. The control circuit 407 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 408 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 404, the audio signal is sent to the audio signal amplification circuit 409, and the output is supplied to the speaker 413 through the audio signal processing circuit 410. The control circuit 411 receives control information on the receiving station (reception frequency) and volume from the input unit 412, and sends a signal to the tuner 404 and the audio signal processing circuit 410.

  FIG. 26 shows an example of a liquid crystal display module. A TFT substrate 200 and a counter substrate 229 are fixed by a sealant 226, and a pixel portion 101 and a liquid crystal layer 230 are provided therebetween to form a display region. The colored layer 270 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Polarizing plates 271 and 272 are disposed outside the TFT substrate 200 and the counter substrate 229. The light source is constituted by a cold cathode tube 258 and a light guide plate 259, and the circuit board 257 is connected to the TFT substrate 200 by a flexible wiring board 273 and a terminal 231, and external circuits such as a control circuit and a power supply circuit are incorporated.

  FIG. 27 shows a state in which this liquid crystal display module is assembled in a housing 2301 to complete a television receiver. A display screen 2303 is formed by the liquid crystal display module, and other accessories such as a speaker 2304 and an operation switch 2305 are provided. As described above, a television receiver can be completed according to the present invention.

  Of course, the liquid crystal display device of the present invention is not limited to a television receiver, and is a display medium such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, a display of a mobile phone, etc. It can be applied to various uses.

FIG. 1 is a top view illustrating the configuration of the liquid crystal display device of the present invention. FIG. 2 is a top view illustrating the configuration of the liquid crystal display device of the present invention. FIG. 3 is a top view illustrating the configuration of the liquid crystal display device of the present invention. FIG. 4 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 7 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 8 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 9 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 12 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 13 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. 14A to 14C are a top view and cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. 15A to 15C are a top view and cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. 16A to 16C are a top view and cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. 17A to 17C are a top view and cross-sectional views illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 18 is a cross-sectional view illustrating a method for manufacturing a liquid crystal display device of the present invention. FIG. 19 is a diagram for explaining a mounting method (COG method) of the driving circuit of the liquid crystal display device of the present invention. FIG. 20 is a diagram for explaining a mounting method (TAB method) of the driving circuit of the liquid crystal display device of the present invention. FIG. 21 is a diagram for explaining a mounting method (COG method) of the driving circuit of the liquid crystal display device of the present invention. FIG. 22 is a diagram illustrating a circuit configuration in the case where the scanning line side driving circuit is formed of TFTs in the liquid crystal display device of the present invention. FIG. 23 is a diagram illustrating a circuit configuration in the case where the scanning line side driving circuit is formed of TFTs in the liquid crystal display device of the present invention (shift register circuit). FIG. 24 is a diagram for explaining a circuit configuration when the scanning line side driving circuit is formed of TFTs in the liquid crystal display device of the present invention (buffer circuit). FIG. 25 is a block diagram showing the main configuration of the liquid crystal television receiver of the present invention. FIG. 26 is a diagram illustrating the configuration of the liquid crystal display module of the present invention. FIG. 27 is a diagram illustrating the configuration of a television receiver completed according to the present invention. FIG. 28 is a top view illustrating a liquid crystal display device of the present invention. FIG. 29 is an equivalent circuit diagram of the liquid crystal display device described in FIG. FIG. 30 is a diagram illustrating a configuration of a droplet discharge apparatus that can be applied to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Substrate 101 Pixel part 102 Pixel 103 Scan line side input terminal 104 Signal line side input terminal 105 Driver IC
106 Driver IC
107 scanning line side driving circuit 108 protection diode 200 TFT substrate 201 adhesion improving layer 202 gate wiring layer 203 gate electrode layer 204 insulator layer 205 insulator layer 206 insulator layer 207 insulator layer 208 semiconductor layer 209 channel protection film 210 semiconductor Layer 211 mask 212 semiconductor layer 213 semiconductor layer 214 interlayer insulating film 215 source wiring layer 216 drain wiring layer 217 semiconductor layer 218 semiconductor layer 219 protective layer 220 insulating layer 221 pixel electrode layer 222 insulating layer 223 sealing material 224 insulating layer 225 Conductor layer 226 Sealing material 229 Counter substrate 230 Liquid crystal layer 231 Terminal 232 Connection wiring layer 233 Connection wiring layer 234 Connection wiring layer 235 Connection wiring layer 249 Wiring layer 250 Gate electrode layer 251 Semiconductor layer 252 Insulating layer 253 Wiring layer 254 Common potential line 25 Common potential line 256 interconnect layers 257 circuit board 258 CCFL 259 light guide plate 260 TFT
261 Protection diode 262 Protection diode 270 Colored layer 271 Polarizing plate 272 Polarizing plate 273 Flexible wiring substrate 300 TFT substrate 301 Semiconductor layer 302 Mask 303 Semiconductor layer 304 Semiconductor layer 305 Interlayer film 306 Source wiring layer 307 Drain wiring layer 308 Semiconductor layer 309 Semiconductor layer 310 Semiconductor layer 401 Pixel unit 402 Signal line side drive circuit 403 Scan line side drive circuit 404 Tuner 405 Video signal amplification circuit 406 Video signal processing circuit 407 Control circuit 408 Signal division circuit 409 Audio signal amplification circuit 410 Audio signal processing circuit 411 Control circuit 412 Input unit 413 Speaker 500 TFT substrate 501 Pixel electrode layer 502 Gate wiring layer 503 Gate electrode layer 504 Insulator layer 505 Insulator layer 506 Insulator layer 507 Insulator layer 508 Semiconductor layer 09 channel protection film 510 semiconductor layer 511 mask 512 semiconductor layer 513 semiconductor layer 514 interlayer insulating film 515 source wiring layer 516 drain wiring layer 517 semiconductor layer 518 semiconductor layer 519 insulating layer 520 insulating layer 521 pixel electrode layer 601 TFT
602 TFT
603 TFT
604 TFT
605 TFT
606 TFT
607 TFT
608 TFT
609 TFT
610 TFT
611 TFT
612 TFT
613 TFT
620 TFT
621 TFT
622 TFT
623 TFT
624 TFT
625 TFT
626 TFT
627 TFT
628 TFT
629 TFT
630 TFT
631 TFT
632 TFT
633 TFT
634 TFT
635 TFT
700 TFT substrate 701 Insulator layer 702 Pixel electrode layer 809 Input / output terminal 810 Conductive particle 811 Resin 812 FPC
813 Wiring 814 Conductive particles 815 Resin 816 Adhesive 817 Au wire 818 Sealing resin 1001 Substrate 1002 Pixel region 1003 Drive circuit 1004 Drive circuit 1005 Substrate 1006 Tape 1007 Driver IC
1008 Substrate 1009 Tape 1010 Driver IC
1204 Capacitor line 1224 Pixel electrode 1400 Substrate 1403 Droplet ejection means 1404 Imaging means 1405 Head 1407 Control means 1408 Storage medium 1409 Image processing means 1410 Computer 1411 Marker 1500 Pulse output circuit 1501 Buffer circuit 1502 Pixel 2301 Housing 2303 Display screen 2304 Speaker 2305 Operation switch

Claims (19)

A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
An island-shaped gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A thin film transistor having a source wiring layer and a drain wiring layer connected to the semiconductor layer and formed of a conductive material;
A pixel electrode connected to the thin film transistor;
The liquid crystal display device, wherein an end of the semiconductor layer is provided so as not to exceed an end of the gate insulating layer. A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
A gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A thin film transistor connected on the semiconductor layer and having a source wiring layer and a drain wiring layer made of a conductive material;
A pixel electrode connected to the thin film transistor;
The liquid crystal display device is characterized in that an end of the semiconductor layer is provided so as to coincide with an end of the gate insulating layer. A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
An island-shaped gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A source wiring layer and a drain wiring layer connected to the semiconductor layer and made of a conductive material;
A thin film transistor having a silicon nitride layer or a silicon nitride oxide layer in contact with the wiring layer;
A pixel electrode connected to the thin film transistor;
The liquid crystal display device, wherein an end of the semiconductor layer is provided so as not to exceed an end of the gate insulating layer. A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
An island-shaped gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A source wiring layer and a drain wiring layer made of a conductive material connected on the semiconductor layer;
A thin film transistor having a silicon nitride layer or a silicon nitride oxide layer in contact with the wiring layer;
A pixel electrode connected to the thin film transistor;
The liquid crystal display device is characterized in that an end of the semiconductor layer is provided so as to coincide with an end of the gate insulating layer. A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
An island-shaped gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A first thin film transistor connected to the semiconductor layer and having a source wiring layer and a drain wiring layer made of a conductive material;
A pixel electrode connected to the first thin film transistor;
A drive circuit composed of a second thin film transistor formed in the same layer structure as the first thin film transistor;
A wiring layer extending from the drive circuit and connected to the gate electrode layer of the first thin film transistor;
An end of the semiconductor layer is provided so as not to exceed an end of the gate insulating layer. A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
An island-shaped gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A first thin film transistor connected to the semiconductor layer and having a source wiring layer and a drain wiring layer made of a conductive material;
A pixel electrode connected to the first thin film transistor;
A drive circuit composed of a second thin film transistor formed in the same layer structure as the first thin film transistor;
A wiring layer extending from the drive circuit and connected to the gate electrode layer of the first thin film transistor;
The liquid crystal display device is characterized in that an end of the semiconductor layer is provided so as to coincide with an end of the gate insulating layer. A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
An island-shaped gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A source and drain wiring layer connected to the semiconductor layer and formed of a conductive material;
A first thin film transistor having a silicon nitride layer or a silicon nitride oxide layer in contact with the source wiring layer and the drain wiring layer;
A pixel electrode connected to the first thin film transistor;
A drive circuit composed of a second thin film transistor formed in the same layer structure as the first thin film transistor;
A wiring layer extending from the driving circuit and connected to the gate electrode layer of the first thin film transistor;
The liquid crystal display device, wherein an end of the semiconductor layer is provided so as not to exceed an end of the gate insulating layer. A gate electrode layer formed of a conductive material on one of the pair of substrates holding the liquid crystal;
An island-shaped gate insulating film including a silicon nitride layer, a silicon nitride oxide layer, or a silicon oxide layer in contact with the gate electrode layer;
A semiconductor layer;
A source and drain wiring layer connected to the semiconductor layer and formed of a conductive material;
A first thin film transistor having a silicon nitride layer or a silicon nitride oxide layer in contact with the source wiring layer and the drain wiring layer;
A pixel electrode connected to the first thin film transistor;
A drive circuit composed of a second thin film transistor formed in the same layer structure as the first thin film transistor;
A wiring layer extending from the driving circuit and connected to the gate electrode layer of the first thin film transistor;
The liquid crystal display device is characterized in that an end of the semiconductor layer is provided so as to coincide with an end of the gate insulating layer.   In any 1 item | term of the Claims 1 thru | or 8, It has the adhesive improvement layer by a metal material or a metal oxide material as a pre-formation process of one or all the layers formed, It is characterized by the above-mentioned. Liquid crystal display device. In any one of Claims 1 thru | or 9,
A liquid crystal display device comprising a protective film on the semiconductor layer. In any one of Claims 1 to 10,
The liquid crystal display device, wherein the conductive material contains Ag, Au, Cu, W, or Al as a main component. In any one of Claims 1 to 11,
The liquid crystal display device, wherein the semiconductor layer includes a semiconductor including a crystal structure including hydrogen and a halogen element, and includes a thin film transistor operable with a field effect mobility of 1 to 15 cm ² / V · sec. In any one of Claims 1 to 12,
The liquid crystal display device is incorporated in a television receiver, a personal computer, a mobile phone, an information display board, or an advertisement display board. A gate electrode layer is selectively formed by a droplet discharge method on a substrate having an insulating surface or a substrate on which a base layer is formed as a pretreatment,
Forming a gate insulating layer on the gate electrode layer;
Forming a first semiconductor layer on the gate insulating layer;
A channel protective layer is selectively formed by a droplet discharge method at a position overlapping the gate electrode layer on the first semiconductor layer;
Forming a second semiconductor layer containing an impurity having one conductivity over the gate insulating layer, the first semiconductor layer, and the channel protective layer;
Selectively forming a first mask layer on the second semiconductor layer;
Etching the second semiconductor layer, the first semiconductor layer, and the gate insulating layer with the first mask layer;
A first insulating layer is selectively formed on the gate electrode layer by a droplet discharge method;
Source and drain wiring layers are selectively formed by a droplet discharge method,
Etching the second semiconductor layer on the channel protective layer;
A passivation film is formed on the entire surface of the substrate,
A second insulating layer is selectively formed on the passivation film by a droplet discharge method,
Etching the passivation film on the drain wiring layer;
A method for manufacturing a liquid crystal display device, comprising forming a transparent conductive film on the second insulating layer so as to be connected to the drain wiring layer. In claim 14,
A method for manufacturing a liquid crystal display device, wherein the step of forming the gate insulating layer and the first semiconductor layer over the gate electrode layer is continuously performed without being exposed to the atmosphere. A gate electrode layer is selectively formed by a droplet discharge method on a substrate having an insulating surface or a substrate on which a base layer is formed as a pretreatment,
Forming a gate insulating layer on the gate electrode layer;
Forming a first semiconductor layer on the gate insulating layer;
A channel protective layer is selectively formed by a droplet discharge method at a position overlapping the gate electrode layer on the first semiconductor layer;
Forming a second semiconductor layer containing an impurity having one conductivity over the gate insulating layer, the first semiconductor layer, and the channel protective layer;
Selectively forming a first mask layer on the second semiconductor layer;
Etching the second semiconductor layer, the first semiconductor layer, and the gate insulating layer with the first mask layer;
A first insulating layer is selectively formed on the gate electrode layer by a droplet discharge method;
Source and drain wiring layers are selectively formed by a droplet discharge method,
Etching the second semiconductor layer on the channel protective layer using the source and drain wiring layers as a mask,
A passivation film is formed on the entire surface of the substrate,
A second insulating layer is selectively formed on the passivation film by a droplet discharge method,
Etching the passivation film on the drain wiring layer using the second insulating layer as a mask,
A method for manufacturing a liquid crystal display device, comprising forming a transparent conductive film on the second insulating layer so as to be connected to the drain wiring layer. In claim 16,
A method for manufacturing a liquid crystal display device, wherein the step of forming the gate insulating layer and the first semiconductor layer on the base layer is continuously performed without being exposed to the air. In any one of Claims 14 thru / or Claim 17,
The method for manufacturing a liquid crystal display device, wherein the gate insulating layer is formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. In any one of Claim 14 thru / or Claim 17,
By etching the second semiconductor layer, the first semiconductor layer, and the gate insulating layer with the first mask layer, the end of the first semiconductor layer is changed to the end of the gate insulating layer. A method for manufacturing a liquid crystal display device, wherein the liquid crystal display device is formed so as not to exceed.

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