JP4599224B2 - 通信装置 - Google Patents
通信装置 Download PDFInfo
- Publication number
- JP4599224B2 JP4599224B2 JP2005143334A JP2005143334A JP4599224B2 JP 4599224 B2 JP4599224 B2 JP 4599224B2 JP 2005143334 A JP2005143334 A JP 2005143334A JP 2005143334 A JP2005143334 A JP 2005143334A JP 4599224 B2 JP4599224 B2 JP 4599224B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- reception quality
- order
- pll circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Description
PLL位相雑音=PLLのC/N比+10×log(比較周波数)+20×log(N分周器の分周値) ・・・(1)
比較周波数=(周波数変換用信号の周波数)/(N分周器の分周値) ・・・(2)
Claims (2)
- ΣΔ変調回路を含むPLL回路を用いて受信信号の周波数変換を行う通信装置において、
前記ΣΔ変調回路によるΣΔ変調の次数を変更する次数変更手段と、
前記周波数変換後の受信信号の品質を示す品質情報を取得する品質情報取得手段と、
を含み、
前記次数変更手段は、前記品質情報により示される品質が所定条件を満たすように、前記次数を変更する、
ことを特徴とする通信装置。 - 前記次数変更手段は、前記品質が前記所定条件を満たし、かつ最もよくなる次数を前記次数として決定する、
ことを特徴とする請求項1に記載の通信装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005143334A JP4599224B2 (ja) | 2005-05-16 | 2005-05-16 | 通信装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005143334A JP4599224B2 (ja) | 2005-05-16 | 2005-05-16 | 通信装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006319926A JP2006319926A (ja) | 2006-11-24 |
JP4599224B2 true JP4599224B2 (ja) | 2010-12-15 |
Family
ID=37540126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005143334A Expired - Fee Related JP4599224B2 (ja) | 2005-05-16 | 2005-05-16 | 通信装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4599224B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008187556A (ja) * | 2007-01-31 | 2008-08-14 | Nec Electronics Corp | 受信装置 |
US9287886B2 (en) * | 2008-02-29 | 2016-03-15 | Qualcomm Incorporated | Dynamic reference frequency for fractional-N Phase-Locked Loop |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000244421A (ja) * | 1999-02-23 | 2000-09-08 | Matsushita Electric Ind Co Ltd | 無線通信装置、無線通信装置の受信方法および記録媒体 |
JP2005045770A (ja) * | 2003-07-09 | 2005-02-17 | Renesas Technology Corp | スプレッドスペクトラムクロック発生器及びそれを用いた集積回路装置 |
-
2005
- 2005-05-16 JP JP2005143334A patent/JP4599224B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000244421A (ja) * | 1999-02-23 | 2000-09-08 | Matsushita Electric Ind Co Ltd | 無線通信装置、無線通信装置の受信方法および記録媒体 |
JP2005045770A (ja) * | 2003-07-09 | 2005-02-17 | Renesas Technology Corp | スプレッドスペクトラムクロック発生器及びそれを用いた集積回路装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2006319926A (ja) | 2006-11-24 |
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