WO2014078311A2

WO2014078311A2 - Frequency synthesis using a phase locked loop

Info

Publication number: WO2014078311A2
Application number: PCT/US2013/069691
Authority: WO
Inventors: Ismail Lakkis
Original assignee: Adeptence, Llc
Priority date: 2012-11-14
Filing date: 2013-11-12
Publication date: 2014-05-22
Also published as: WO2014078311A3; WO2014078311A4; TWI650948B; TW201444296A

Abstract

A phase locked loop circuit comprises a phase/frequency detector, a voltage-controlled oscillator (VCO), and a divider chain in a feedback path coupling the VCO output to the phase/frequency detector. The divider chain comprises a plurality of sequentially connected divider circuits and a plurality of local oscillator outputs interspersed at different locations within the divider chain, which enables the circuit to simultaneously output multiple oscillator signals having different frequencies.

Description

Frequency Synthesis using a Phase Locked Loop

RELATED APPLICATIONS

[0001] This application claims the priority benefit of U.S. Application Ser. No. 61/726,166 filed November 14, 2012.

BACKGROUND

Field of the Invention

[0002] The disclosed embodiments relate to Phase-Locked Loops (PLLs), and more particularly, to PLLs usable in local oscillators within radio receivers and transmitters.

Introduction

[0003] A PLL is a control system that generates an oscillator signal having a constant phase relationship with an input reference signal. PLLs are widely used in various applications, such as radios, telecommunications, computers, and other electronic applications. A PLL includes a voltage-controlled oscillator (VCO) for generating the oscillator signal based on a control voltage, and a phase detector for comparing the phase of the oscillator signal with that of the input reference signal and for generating an error signal based on the detected phase difference.

[0004] The PLL also includes a loop filter for filtering the error signal and generating the control voltage used by the VCO. The loop filter of the phase-locked loop, which attenuates frequencies outside of its passband, is chosen to attenuate the high-frequency components output from the phase detector

[0005] A PLL may be used to output an oscillating signal to drive a frequency mixer used in a transmitter or a receiver in a radio communication system. The frequency mixer may be used, for example, to up-convert a signal in a transmit chain and/or to down-convert a signal in a receive chain. In radio communications, it is often advantageous to operate in different frequency bands. Since it can be impractical to employ a different radio front end for each required band, programmable oscillators are often employed in transceivers.

[0006] The frequency of the signal output by the PLL can be changed by varying the frequency of the reference signal. However, since the reference signal is typically generated by a very stable oscillator whose frequency cannot be varied, at least one divider may be provided in the feedback loop so that the output frequency of the PLL can be varied without having to change the frequency of the reference signal.

[0007] In other systems, the loop filter is a programmable digital filter whose coefficients can be changed under software control. A first set of filter coefficients produces a local oscillator signal in a first radio frequency communication band, and a second set of filter coefficients is used if a local oscillator signal in a second radio frequency communication band is required.

[0008] In addition to the requirement that radio transceivers be frequency agile, transceivers typically require multiple timing signals at different frequencies to be provided

simultaneously. For example, analog-to-digital conversion typically requires a different clock frequency than the oscillator frequency used for down-conversion. Furthermore, these other clock frequencies may change depending on the frequency band being employed by the transceiver. These and other needs in the field are addressed by aspects of the present invention.

SUMMARY

[0009] The foregoing is a summary and thus, contains simplifications, generalizations and omissions of detail. Consequently, those skilled in the art will appreciate that the summary is illustrative only and does not purport to be limiting in any way. Other aspects, inventive features, and advantages of the devices and/or processes described herein, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth herein.

[0010] In accordance with aspects of the invention, systems and methods are provided for employing a PLL for simultaneously outputting a plurality of oscillating signals, each having a different frequency.

[0011] In one aspect of the invention, a PLL circuit comprises a phase/frequency detector, a charge pump, a loop filter, a VCO, a sequentially connected divider chain in a feedback path coupling the VCO output to the phase/frequency detector, and a plurality of local oscillator outputs interspersed at different locations within the divider chain. The divider chain comprises at least a first divider circuit and a second divider circuit. A first local oscillator output is coupled before the first divider circuit, and a second local oscillator output is coupled before the second divider circuit. The divider circuits may comprise a combination of fixed dividers and variable dividers.

[0012] In another aspect of the invention, a method is provided for simultaneously generating a plurality of reference frequencies from a PLL. The method comprises inserting a reference signal into the PLL, generating a VCO signal in the PLL, outputting a first local oscillator signal having a first frequency, frequency dividing the first local oscillator signal in a feedback path of the PLL to produce a second local oscillator signal having a second frequency that is different from the first frequency, and outputting the second local oscillator signal from the feedback path. Dividing the local oscillator signals may comprise employing a combination of fixed dividers and selectable, or variable, dividers. One or more of the local oscillator signals may be used for mixing in an up-conversion and/or down-conversion process. One or more of the local oscillator signals may be used for other transceiver operations, such as a clock signal used in an analog-to-digital converter. It should be understood that features described in one aspect or embodiment may be employed in the other described aspects and embodiments.

[0013] Additional features and advantages of the invention will be set forth in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to describe the manner in which the above -recited and other advantages and features of the invention can be obtained, a more particular description of the invention briefly described above will be rendered by reference to specific aspects thereof, which are illustrated in the appended drawings. These drawings depict only typical aspects of the invention and are not therefore to be considered to be limiting of its scope. Aspects of the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings.

[0015] Figure 1 is a block diagram of an RF transceiver in which aspects of the invention may be employed.

[0016] Figure 2 is a block diagram of a local oscillator circuit in accordance with an aspect of the invention.

[0017] Figure 3 is a table of operating values corresponding to the function of a PLL configured to function in accordance with aspects of the invention.

[0018] Figure 4 is a block diagram of a local oscillator circuit in accordance with an aspect of the invention.

[0019] Figure 5 is a flow diagram depicting a method in accordance with an aspect of the invention.

DETAILED DESCRIPTION

[0020] Various aspects of the disclosure are described below. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein are merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. Any feature described with respect to one aspect may be employed in any of the other described aspects herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein.

[0021] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It should be understood, however, that the particular aspects shown and described herein are not intended to limit the invention to any particular form, but rather, the invention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the claims.

[0022] The present disclosure is directed to techniques for synthesizing the frequencies required for wireless communication devices. As will be described in greater detail below, the synthesizer circuit provides a flexible programmable oscillator that provides a broad range of frequencies required by a typical wireless communication device.

[0023] Figure 1 is a block diagram of an RF transceiver in which aspects of the invention may be employed. The transceiver includes a receive chain 105, a first local oscillator 114, a transmit chain 116, and a second local oscillator 119. In alternative aspects of the invention, a single local oscillator (not shown) may serve both the receive chain 105 and the transmit chain 116.

[0024] In receiving mode, a radio signal is received by an antenna 102. The received signal passes through a duplexer 108, a matching network 109, and the receive chain 105. In the receive chain 105, the received signal is amplified by a low noise amplifier (LNA) 110 and is down-converted in frequency by a mixer 111. The resulting down-converted signal is filtered by a baseband filter 112 and is passed to a baseband processor 104, such as a digital baseband integrated circuit. An analog-to-digital converter 113 in the baseband processor 104 converts the signal into digital form, and the resulting digital information is processed by digital circuitry (not shown) in the baseband processor 104. The baseband processor 104 may tune the receiver by controlling the frequency of the local oscillator 114 signal supplied to the mixer 111.

[0025] In transmitting mode, digital information to be transmitted is converted into analog form by a Digital-to-Analog Converter (DAC) 115 in the baseband processor 104 and supplied to the transmit chain 116. A baseband filter 117 filters out noise originating from the digital-to-analog conversion process. A mixer block 118 coupled to the local oscillator 119 up-converts the filtered signal into a high-frequency signal. Driver amplifier (DA) 120 and an external power amplifier (PA) 121 amplify the high-frequency signal to drive antenna 102 so that a radio signal is transmitted from antenna 102. The baseband processor 104 may also control the frequency of a local oscillator signal supplied by the local oscillator 1 19 to the mixer 1 18. For example, the baseband processor 104 may control the local oscillators 1 14 and 1 19 by sending control signals through a bus interface 125 coupled to the local oscillators 1 14 and 1 19.

[0026] Figure 2 is a block diagram of a local oscillator circuit in accordance with an aspect of the invention as may be employed in the local oscillators 1 14 and 1 19. The local oscillator circuit may comprise a reference signal generator 200 (such as a crystal oscillator circuit) and a Phase-Locked Loop (PLL) circuit. The PLL comprises a phase/frequency detector 201 , a charge pump 202, a loop filter 203, a voltage-controlled oscillator (VCO) 204 and a feedback path comprising a sequentially connected divider chain coupling the VCO's 204 output to the phase/frequency detector (PFD) 201.

[0027] In one aspect of the invention, the divider chain comprises divide -by-two divider circuits 205, 206, and 207, each of which provides a fixed divisor of two. The divider chain also comprises a variable divider circuit 208, which provides a selectable divisor of 21 , 25, or 29 based on a control signal from a control interface 218. Divider chains in other aspects of the invention may comprise alternative combinations of divider circuits.

[0028] The crystal oscillator circuit 200 outputs a stable and fixed reference clock signal S_REF, which is coupled to a first input of the phase/frequency detector 201. Additionally, a feedback signal S_FB from the PLL's feedback loop is coupled to a second input of the phase/frequency detector 201.

[0029] The phase/frequency detector 201 outputs a signal that is representative of the phase and/or frequency difference between the reference signal S_REF and the feedback signal S_FB- The PFD's 201 output signal passes through the charge pump 202 and is filtered by the loop filter 203 before it is coupled into the VCO 204 as a control signal. The control signal is used by the VCO 204 to modify the frequency of the VCO's 204 output signal.

[0030] In one aspect, a first local oscillator signal S_Loi output by the VCO 204 may be supplied to a mixer, such as mixer 1 1 1 or 1 18. The first local oscillator signal S_LO_I is coupled to the divider chain of the feedback loop where it is first divided by fixed divider circuit 205. Divider circuit 205 produces an output signal, which may comprise a second local oscillator signal S_LO₂- The signal S_L0₂ niay optionally be supplied to a mixer, such as mixer 111 or 118. The fixed divider circuit 206 frequency divides the signal output by the divider circuit 205 to produce a timing signal that may be used in either or both an ADC and a DAC, such as an ADC/DAC circuit 209. For example, the timing signal, denoted by SA_DC, may be used in a baseband sampling process, such as an analog-to-digital conversion in the ADC/DAC 209. The ADC/DAC 209 may be the ADC 113 and DAC 115 in the baseband processor 104 shown in Figure 1.

[0031] By providing a divider chain in the feedback loop of a PLL, and providing multiple outputs interspersed at different locations in the divider chain (such as preceding and following divider circuit 205 and/or divider circuit 206), different timing signals used by the radio transceiver can be generated simultaneously by a single PLL. Furthermore, a signal output from the feedback loop may be passed through a divider outside of the divider chain to produce another timing signal. For example, signal SA_DC is divided by fixed divider circuit 210 to produce a clock signal SC_LK that may be used in other digital signal processing operations in the transceiver.

[0032] The signal SA_DC output by divider 206 is frequency divided by fixed divider 207 before it is divided by variable divider circuit 208. The control interface 218 selects from a plurality of integer divider values (e.g., values 21, 25, and 29) for selecting the frequency of the feedback signal S_FB- AS a result, the frequency of the signal S_LO_I output by the VCO is changed by selecting a different integer divider for the variable divider circuit 208. Similarly, the frequencies of the other signal outputs S_L0₂ and SA_DC of the feedback loop and SC_LK are selectable by selecting the integer value employed by divider 208. It should be appreciated that other aspects of the invention may employ alternative divider values, and in some aspects, the divider chain may comprise a plurality of variable divider circuits.

[0033] In one aspect of the invention, the divider chain in the feedback loop may be configured to enable a transceiver to operate at different frequency bands (e.g., at different carrier frequencies, f_c) wherein part of the spectrum is divided into frequency channels of equal bandwidth. For example, the variable divider circuit 208 may comprise divider values and/or selectable locations for the local oscillator outputs in the divider chain to produce a set of first local oscillator signals S_LO_I having different frequencies, each paired with a substantially identical set of second local oscillator signals S_LO₂, SC_LK, and/or SA_DC- [0034] Figure 3 is a table of operating values corresponding to the function of the apparatus shown in Figure 2. All of the values in the table are based on a reference signal S_REF frequency of 40 MHz, and fixed divider 205-207 values equal to 2. The first column (denoted as "BW") displays bandwidth values in MHz, which correspond to half the frequency value of signal SA_DC- The second column (denoted as "CLK") displays clock frequency values in MHz for the frequency of the signal SC_LK- The fourth column (denoted as "f_c") displays the center frequency of a radio signal processed in the transceiver. The values of the first three rows of the fourth column are the VCO's 204 output signal S_LO_I frequency, whereas the fourth row of the fourth column is the frequency of the signal S_L0₂ following fixed divider 205. The second column (denoted as "fmi_n") and fourth column (denoted as "f_max") are the minimum and maximum frequencies, respectively, of the signal processed in the transceiver. The minimum and maximum frequencies are related to the bandwidth and the center frequency. The sixth column (denoted as "N") is the total integer divider value of the divider chain in the feedback loop, which is the product of the dividers 205-208 in the divider chain. This value can differ as a result of the variable divider 208 providing different divider values. The seventh column (denoted as "M") is the total integer divider of a sequence of dividers 205, 206, and 210 between the VCO's 204 output and the output of the clock signal SC_LK- Since the dividers 205, 206, and 210 are fixed dividers with integer values of 2, 2, and 8, respectively, all the values in the seventh column are 32.

[0035] In accordance with one aspect of the invention, a reference signal S_REF frequency of 40 MHz is supplied by the reference generator 200 to the phase/frequency detector 201. The variable frequency divider 208 provides a divider value of 21. Thus, the total divider value N of the divider chain is 168, and the frequency of S_LO_I at the VCO's 204 output is the center frequency f_c = 6720 MHz. The frequency of SA_DC supplied to the ADC/DAC 209 is 1680 MHz. The ADC/DAC 209 has an over-sampling rate of two, so the bandwidth BW = 840 MHz. Thus, fmin = 6300 MHz and f_max = 7140 MHz. The clock signal SC_LK has a frequency CLK = 210 MHz.

[0036] As shown in the second row, changing the variable frequency divider's 208 divider value to 25, the total divider value becomes N = 200, the center frequency is f_c = 8000 MHz, the bandwidth BW = 1000 MHz, the clock frequency CLK = 250 MHz, and f_min = 7500 MHz and f_max = 8500 MHz. Thus, changing the total divider value of the divider chain not only changes the frequency of the VCO 204 output used for frequency mixing, it also changes the other loop frequency values, such as the frequency of SA_DC- AS a result, the bandwidth BW and the clock frequencies CLK are different as well.

[0037] The third row depicts associated values pertaining to when the variable frequency divider 208 selects a divider value of 29. In this case, N = 232, the center frequency is f_c = 9280 MHz, the bandwidth BW = 1 160 MHz, the clock frequency CLK = 290 MHz, and f_min = 8700 MHz and f_max = 9860 MHz.

[0038] In accordance with an aspect of the invention, which is described with reference to the fourth row, the VCO 204 output used for mixing is taken from a different part of the divider chain for processing a different center frequency f_c. Specifically, the signal S_LO₂ output after the first fixed divider circuit 205 of the divider chain is used to provide the center frequency is f_c = 4000 MHz. Since the variable frequency divider's 208 selected divider value is 25 (thus, N = 200), the bandwidth BW and clock signal CLK are the same as in the case depicted by the second row. Only the center frequency f_c, the minimum frequency fmi_n, and the maximum frequency f_max differ.

[0039] In accordance with an aspect of the invention, the table shown in Figure 3 is a frequency-band plan for an ultra-wideband (UWB) transmitter and/or receiver. UWB is a general term for a type of radio communication in which emitted RF energy is spread over 500 MHz of spectrum within the frequency range of 3.1 GHz to 10.6 GHz, as defined by the FCC ruling issued for UWB in Feb. 2002. For example, two sections of spectrum that may be employed in UWB comprise 3.1 -5.15 GHz and 5.8- 10.6 GHz.

[0040] Specifically, the local oscillator circuit shown in Figure 2 may be used to generate local oscillator signals having center frequencies shown in the table of Figure 3. These local oscillator signals are subsequently used in the receive chain 105 to down-convert a received RF signal and/or in the transmit chain 1 16 to up-convert a signal to be transmitted. Thus, the local oscillator circuit 1 14 and/or 1 19 may generate and/or receive signals in one or more of the four frequency bands depicted by the table shown in Figure 3.

[0041 ] In some aspects of the invention, different reference frequencies may be supplied to the PLL. For example, as depicted in Figure 4, a crystal oscillator (XTAL) 401 generates a stable reference frequency that is divided by a programmable divider circuit 402 coupled to the control interface 218. The divider circuit 402 selects different divider values based on instructions received from the control interface 218. Thus, a combination of selectable reference frequencies and selectable divider values N may be employed for selecting the center frequency f_c, the bandwidth BW, the clock frequency CLK, and/or frequencies of other signals output by the PLL. In one aspect of the invention, multiple combinations of the reference signal S_REF frequency and the total divider value N may be generating for providing substantially identical ADC frequencies (thus, bandwidths BW) to different center frequencies f_c.

[0042] Figure 5 is a flow diagram depicting a method in accordance with an aspect of the invention. In order to simultaneously generate a plurality of reference frequencies from a PLL, a reference signal, such as a stable and fixed reference clock signal, is inserted into the PLL 501. For example, the reference signal may be generated by a crystal oscillator and coupled into a phase/frequency detector in the PLL.

[0043] The PLL includes a VCO for generating an oscillator signal 502 based on a control voltage, and a phase/frequency detector for comparing the phase of the oscillator signal with that of the input reference signal and for generating an error signal based on the detected phase difference. The PLL includes a loop filter for filtering the error signal and generating the control voltage used by the VCO. Thus, the frequency of the VCO signal can be changed by varying the frequency of the reference signal, and/or a variable divider in the feedback path coupling the VCO output to the phase/frequency detector may be used to change the VCO signal frequency.

[0044] In an aspect of the invention, the feedback path comprises a sequentially connected divider chain. A first local oscillator signal is output from the feedback path 503. The first local oscillator signal may comprise the output of the VCO, or it may comprise an output from one of the divider circuits in the sequentially connected divider chain.

[0045] In the feedback path, the first local oscillator signal is frequency divided 504 by at least one divider circuit in the sequentially connected divider chain. A second local oscillator signal having a different frequency from the first local oscillator signal is output 505 from the sequentially connected divider chain in the feedback path. [0046] In one aspect of the invention, the sequentially connected divider chain comprises at least a first divider circuit and a second divider circuit. The divider chain includes a first local oscillator output coupled before the first divider circuit for outputting a first local oscillator signal having a first frequency. The divider chain also includes a second local oscillator output coupled before the second divider circuit for outputting a second local oscillator signal having a second frequency that is different from the first frequency. Typically, the second frequency is less than the first frequency. The first local oscillator signal may be used in a mixer to up-convert and/or down-convert signals in a transceiver, while the second local oscillator signal may be used as part of a different transceiver function, such as a clock signal for an ADC.

[0047] The PLL circuits and methods depicted in this disclosure may operate in an integer-N mode or in a fractional-N mode. The local oscillator signal generated by an integer-N PLL can exhibit a relatively large amount of phase noise. As the PLL operates, the frequency of the signal varies and is controlled within a frequency band determined by the loop filter bandwidth. In a fractional-N PLL, the frequency of the comparison reference clock signal can be higher. Thus, the loop filter can have a higher bandwidth, which suppresses phase noise. The fractional-N PLL topology therefore can be used to generate local oscillator signals that have less phase noise as compared to local oscillator signals that would be generated using the integer-N PLL topology.

[0048] The methods and systems described herein merely illustrate particular aspects of the invention. It should be appreciated that those skilled in the art will be able to devise various arrangements, which, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples and conditional language recited herein are intended to be only for pedagogical purposes to aid the reader in understanding the principles of the invention. This disclosure and its associated references are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles and aspects of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

Claims

1. A phase locked loop circuit comprising:

a phase/frequency detector;

a voltage-controlled oscillator (VCO);

a sequentially connected divider chain in a feedback path coupling the VCO output to the phase/frequency detector; and

a plurality of local oscillator outputs interspersed at different locations within the divider chain for providing at least a first local oscillator signal having a first frequency and a second local oscillator signal having a second frequency, the second frequency being different from the first frequency.

2. The circuit recited in Claim 1, wherein the divider chain comprises at least one variable divider circuit for enabling selectable values of at least one of the first frequency and the second frequency.

3. The circuit recited in Claim 2, wherein the at least one variable divider circuit and the local oscillator outputs are configured for generating multiple differing values of the first frequency, each paired with substantially identical values of the second frequency.

4. The circuit recited in Claim 1, further comprising a reference signal generator configured for providing selectable reference frequencies to the phase/frequency detector.

5. The circuit recited in Claim 1, configured to operate in at least one of an integer-N mode and a fractional-N mode.

6. A phase locked loop circuit comprising:

a phase/frequency detector;

a voltage-controlled oscillator (VCO);

a sequentially connected divider chain in a feedback path coupling the VCO output to the phase/frequency detector, the divider chain comprising a first divider circuit, a first local oscillator output coupled before the first divider circuit for providing a first local oscillator signal having a first frequency, a second divider circuit, and a second local oscillator output coupled before the second divider circuit for providing a second local oscillator signal having a second frequency that is different from the first frequency.

7. The circuit recited in Claim 6, wherein the divider chain comprises at least one variable divider circuit for enabling selectable values of at least one of the first frequency and the second frequency.

8. The circuit recited in Claim 7, wherein at least one of the variable divider circuit, the first local oscillator output, and the second local oscillator output is configured for generating multiple differing values of the first frequency and substantially identical values of the second frequency.

9. The circuit recited in Claim 6, further comprising a reference signal generator configured for providing selectable reference frequencies to the phase/frequency detector.

10. The circuit recited in Claim 6, configured to operate in at least one of an integer-N mode and a fractional-N mode.

11. A method for simultaneously generating a plurality of reference frequencies from a

phase-locked loop (PLL), comprising:

inserting a reference signal into the PLL;

generating a VCO signal in the PLL;

generating a first local oscillator signal in a feedback path of the PLL, the local oscillator signal having a first frequency;

frequency dividing at least the first local oscillator signal in the feedback path of the PLL to produce a second local oscillator signal having a second frequency that is different from the first frequency; and

simultaneously outputting the first local oscillator signal and the second local oscillator signal.

12. The method recited in Claim 11, wherein frequency dividing is performed by at least one fixed divider circuit and at least one variable divider circuit.

13. The method recited in Claim 11, wherein the PLL is configured to operate in at least one of an integer-N mode and a fractional-N mode.

14. The method recited in Claim 11, further comprising employing at least one of selectable reference frequencies and selectable divider values for selecting at least one of the first frequency and the second frequency.

15. The method recited in Claim 11, further comprising generating multiple differing values of the first frequency paired with substantially identical values of the second frequency.