TW201444296A - Frequency synthesis using a phase locked loop - Google Patents

Abstract

A phase locked loop circuit comprises a phase/frequency detector, a voltage-controlled oscillator (VCO), and a divider chain in a feedback path coupling the VCO output to the phase/frequency detector. The divider chain comprises a plurality of sequentially connected divider circuits and a plurality of local oscillator outputs interspersed at different locations within the divider chain, which enables the circuit to simultaneously output multiple oscillator signals having different frequencies.

Description

Frequency synthesis using phase-locked loops

Embodiments of the present invention are related to phase-locked loops (PLLs), particularly phase-locked loops that can be used in local oscillators for radio receivers and transmitters.

The present application claims priority to U.S. Patent Application Serial No. 61/726,166, filed on Nov. 14, 2012.

A phase locked loop is a control system that produces an oscillator signal having a fixed phase associated with an input reference signal. Phase-locked loops are widely used in a variety of applications, such as radio, telecommunications, computers, and other electronic applications. A phase locked loop includes a voltage controlled oscillator that generates the oscillator signal based on a control voltage, and a phase detector for comparing phases of the oscillator signal and the input reference signal, and based on the detected phase difference An error signal is generated.

The phase locked loop also includes a loop filter for filtering the error signal and generating a control voltage for use by the voltage controlled oscillator. A loop filter of the phase locked loop that attenuates frequencies outside the outband and is selected to attenuate the output of the high frequency components from the phase detector.

A phase locked loop can be used to output an oscillating signal to drive a frequency mixer used in a transmitter or receiver in a radio communication system. For example, the frequency mix The device can be used to upconvert the signals in a transmission chain and/or downconvert the signals in a receive chain. In radio communications, it is often advantageous to operate in different frequency bands. Because it does not require the actual use of a different radio front end for each of the required frequency bands, a programmable oscillator is typically employed in the transmitter.

The signal frequency output by the phase locked loop can be changed by changing the frequency of the reference signal. However, since the reference signal is usually generated by a very stable oscillator and its frequency may not be changed, at least one frequency divider may be provided in the feedback loop, so the frequency of the reference signal may not be changed. Next, the frequency of the output of the phase locked loop is changed.

In other systems, the loop filter is a programmable digital filter whose filter coefficients can be changed by software control. In a first RF communication band, a first set of filter coefficients will produce a local oscillator signal, and if a local oscillator signal is required in a second RF communication band, then a second set The filter coefficients will be used.

In addition to being sensitive to frequency, the transceiver typically also needs to provide several timing signals with different frequencies. For example, an analog-to-digital conversion typically requires a clock frequency different from the oscillator frequency for down conversion. Additionally, the other clock frequencies may vary depending on the frequency band used by the transmitter. These and other needs in the art can be solved by the various aspects of the present invention.

The foregoing is a summary, so includes simplifications, generalizations, and omit details. Therefore, it will be understood by those skilled in the art that the summary is merely illustrative and is not intended to be limiting in any way. Other aspects, features of the invention, and advantages of the device and/or method described herein, as defined in the scope of the claims, are hereby incorporated by reference. Obvious.

In accordance with various aspects of the present invention, systems and methods are provided for a phase locked loop that can simultaneously output a plurality of oscillating signals, each having a different frequency.

In one aspect of the invention, a phase locked loop circuit includes a phase/frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and an output of the voltage controlled oscillator and the phase/ A sequence-connected divider chain in the feedback path coupled to the frequency detector. The frequency divider chain includes a plurality of frequency divider circuits, and a plurality of output terminals of the local oscillator distributed in different positions of the frequency divider chain. The frequency divider chain includes at least a first frequency divider circuit and a second frequency divider circuit. An output of a first local oscillator is coupled in front of the first frequency divider circuit, and an output of a second local oscillator is coupled in front of the second frequency divider circuit. The frequency divider circuit can include a combination of a fixed frequency divider and a variable frequency divider.

In another aspect of the invention, a method is provided for simultaneously generating a plurality of reference frequencies from a phase locked loop. The method includes inserting a reference signal into the phase locked loop, generating a voltage controlled oscillating signal in the phase locked loop, outputting a first local oscillator signal having a first frequency, and feeding back one of the phase locked loops In the path, the frequency of the first local oscillator signal is divided to generate a second local oscillator signal having a second frequency different from the first frequency and output by the feedback path The second local oscillator signal. Dividing the local oscillator signal can include using a combination of a fixed frequency divider and a selectable or variable frequency divider. One or more of the local oscillator signals can be used in a mix of up-conversion and/or down-conversion processes. One or more of the local oscillator signals can be used for operation of other transmitters, such as a clock signal for use in a analog to digital conversion. It should be understood, however, that features described in one aspect or embodiment may be employed in other described aspects and embodiments.

Other features and advantages of the invention will be set forth in the description and in the description which The features and advantages of the invention are realized and attained by the <RTIgt; These and other features of the present invention will become more apparent from the following description and appended claims.

102‧‧‧Antenna

103‧‧‧RF Transceiver

104‧‧‧Baseband processor

105‧‧‧Receiving chain

108‧‧‧Duplexer

109‧‧‧matching network

110‧‧‧Low noise amplifier

111, 118‧‧‧ Mixer

112‧‧‧ fundamental frequency filter

113‧‧‧ Analog/Digital Converter

114‧‧‧Local Oscillator

115‧‧‧Digital/Analog Converter

116‧‧‧Transport chain

117‧‧‧ fundamental frequency filter

119‧‧‧Local Oscillator

120‧‧‧Drive Amplifier

121‧‧‧External Power Amplifier

125‧‧‧ bus interface

200‧‧‧Reference signal generator/crystal oscillator circuit

201‧‧‧ phase/frequency detector

202‧‧‧Charge pump

203‧‧‧ Loop Filter

204‧‧‧Voltage Controlled Oscillator

205, 206, 207‧‧‧ except 2 frequency divider circuit

208‧‧‧Variable frequency divider circuit

209‧‧‧Digital/analog converters, analog/digital converters

210‧‧‧Densor circuit

218‧‧‧Control interface

401‧‧‧ crystal oscillator

402‧‧‧Deleber circuit

The description of the above summary of the present invention is set forth with particular reference The drawings merely depict typical aspects of the invention, but are not to be construed as limiting the scope thereof. The various aspects of the present invention will be described in detail and by way of the drawings.

1 is a block diagram of a radio frequency transceiver employing the perspective of the present invention.

2 is a block diagram of a local oscillator circuit in accordance with an aspect of the present invention.

3 is an operational value table corresponding to a configuration of a phase locked loop function in accordance with the teachings of the present invention.

4 is a block diagram of a local oscillator circuit in accordance with an aspect of the present invention.

Figure 5 is a flow diagram of a method in accordance with one aspect of the present invention.

The various aspects of the invention are described below. It is apparent that the teachings herein may be embodied in a wide variety of different forms, and any particular structure, function, or both disclosed herein are merely representative embodiments. Based on the teachings herein, those skilled in the art will appreciate that one aspect of the disclosure herein can be implemented separately and in any other context. Points are irrelevant, and two or more of these views can be combined in various ways. For example, a device may be implemented or a method may be implemented using any number of the aspects described herein. Any of the features described in relation to one aspect may be employed in any other aspect of the invention. In addition, a device may be implemented or a method may be implemented using other structures, functions, or structural additional functions, or one or more of the aspects set forth herein.

In the following description, numerous specific details are set forth in the It should be understood, however, that the invention is not intended to be limited to the specific scope of the invention. Things.

The present invention is directed to techniques for frequency synthesis required by wireless communication devices. As will be described in more detail below, the synthesizer circuit provides a resilient and programmable oscillator that provides a wide range of frequencies required for a typical wireless communication device.

1 is a block diagram of a radio frequency transceiver employing the perspective of the present invention. The transceiver includes a receive chain 105, a first local oscillator 114, a transmit chain 116, and a second local oscillator 119. In another aspect of the invention, a single local oscillator (not shown) can simultaneously supply both the receive chain 105 and the transmit chain 116.

In the receive mode, a radio signal is received by an antenna 102. The received signal passes through a duplexer 108, a matching network 109, and the receive chain 105. In the receive chain 105, the received signal is amplified by a low noise amplifier (LNA) 110 and the frequency is downconverted by a mixer 111. The resulting downconverted signal is filtered by a baseband filter 112 and passed to a baseband processor 104, such as a digital baseband integrated circuit. In the baseband processor 104, an analog-to-digital converter 113 converts the signal into a digital form and the resulting The digital message is processed by a digital circuit (not shown) in the baseband processor 104. The baseband processor 104 can adjust the receiver by controlling the frequency of the signal provided to the local oscillator 114 of the mixer 111.

In the transmit mode, the transmitted digital message will be converted to an analog form by a digital-to-analog converter (DAC) 115 in the baseband processor 104 and provided to the transport chain 116. A fundamental frequency filter 117 will filter out the noise from the digital-to-analog conversion process. A mixer block 118 coupled to the local oscillator 119 converts the filtered signal into a high frequency signal. A driver amplifier (DA) 120 and an external power amplifier (PA) 121 amplify the high frequency signal to drive the antenna 102, thereby causing a radio signal to be transmitted by the antenna 102. The baseband processor 104 can also control the frequency of one of the local oscillator signals provided by the local oscillator 119 to the mixer 118. For example, the baseband processor 104 can control the local oscillators 114 and 119 by transmitting control signals that are coupled to one of the busbar interfaces 125 via the local oscillators 114 and 119.

2 is a block diagram of a local oscillator circuit that can be applied to the local oscillators 114 and 119 in accordance with an aspect of the present invention. The local oscillator circuit can include a reference signal generator 200 (such as a crystal oscillator circuit) and a phase locked loop (PLL) circuit. The phase locked loop includes a phase/frequency detector 201, a charge pump 202, a loop filter 203, a voltage controlled oscillator (VCO) 204, and a feedback path including a sequence of connected frequency divider chains. It couples the output of the voltage controlled oscillator 204 to the phase/frequency detector (PFD) 201.

In one aspect of the invention, the frequency divider chain includes divide by two circuit breaker circuits 205, 206, and 207, each of which provides a fixed divisor of two. The frequency divider chain also includes A variable frequency divider circuit 208 provides a selectable divisor 21, 25, or 29 based on control signals from a control interface 218. The frequency divider chain in other aspects of the invention may include a combination of other frequency divider circuits.

The crystal oscillator circuit 200 outputs a stable and fixed reference clock signal S _REF that is coupled to a first input of a phase/frequency detector 201. In addition to this, a feedback signal S _FB from the feedback loop of the phase locked loop is coupled to a second input of the phase/frequency detector 201.

The phase/frequency detector 201 will output a signal representative of the difference between the phase and/or frequency between the reference signal S _REF and the feedback signal S _FB . The output signal of the phase/frequency detector 201 passes through the charge pump 202 and is filtered by the loop filter 203 before it is coupled to the voltage controlled oscillator 204 as a control signal. The control signal is used by the voltage controlled oscillator 204 to modulate the frequency of the output signal of the voltage controlled oscillator 204.

In one aspect, the first local oscillator signal S _LO1 output by the voltage controlled oscillator 204 can be provided to a mixer, such as mixer 111 or 118. The first local oscillator signal S _LO1 is coupled to the divider chain of the feedback loop and is first divided by the fixed frequency divider circuit 205. The frequency divider circuit 205 produces an output signal that can include a second local oscillator signal S _L02 . This signal S _L02 can optionally be supplied to a mixer, such as mixer 111 or 118. The frequency of the fixed frequency divider circuit 206 divides the output signal from the frequency divider circuit 205 to generate a timing signal that can be used for both or an analog converter and a digital analog converter. One, such as an ADC/DAC circuit 209. For example, the timing signal, labeled S _ADC , can be used in the baseband sampling process, such as analog-to-digital conversion in the ADC/DAC 209. The ADC/DAC 209 can be the ADC 113 and the DAC 115 in the baseband processor 104 shown in FIG.

A divider chain is provided in a feedback loop of a phase locked loop and is provided in various locations interspersed in the frequency divider chain (e.g., before or after the frequency divider circuit 205 and/or the frequency divider circuit 206) The plurality of outputs, the different timing signals used by the radio transmitter can be simultaneously generated through a single phase-locked loop. In addition, an output signal from the feedback loop can generate other timing signals through a divider external to the divider chain. For example, the signal S _ADC , which is divided by the fixed frequency divider circuit 210, can generate a clock signal S _CLK that can be used for processing operations of other digital signals in the transceiver.

The frequency of the signal S _ADC output by the frequency divider 206 is first divided by the fixed frequency divider 207 before being divided by the variable frequency divider circuit 208. The control interface 218 is selected by a plurality of integer divide values (e.g., values 21, 25, and 29) for selecting the frequency of the feedback signal S _FB . As a result, the frequency of the signal S _LO1 output by the voltage controlled oscillator will be changed by selecting a different integer divide value to the variable frequency divider circuit 208. Similarly, the frequency of the other output signals S _LO2 and S _ADC and S _{CLK in} the feedback loop can be selected by selecting the integer value used by the frequency divider 208. However, it should be understood that other alternatives of the frequency division values may be employed in other aspects of the invention, and in some aspects the frequency divider chain may include a plurality of variable frequency divider circuits.

In one aspect of the invention, the frequency divider chain in the feedback loop can be configured such that a transceiver operates in a different frequency band (e.g., at a different carrier frequency, f _C ), a portion of which spectrum Channels that are divided into equal bandwidths. For example, the variable frequency divider circuit 208 can include a frequency division value and/or an optional output position of the local oscillator in the frequency divider chain to generate a set of first local oscillation signals S _LO1 having different frequencies. And a second local oscillator signal S _LO2 , S _CLK and/or S _ADC having substantially the same group as its pair.

Figure 3 is a table of operational values corresponding to the function of the apparatus shown in Figure 2. All values in the table are based on a 40 MHz frequency of a reference signal S _REF , and the demultiplexer values of the fixed frequency dividers 205-207 are equal to two. The first column (labeled "BW") uses the MHz display bandwidth value, which corresponds to one-half of the signal S _ADC frequency value. The second column (labeled "CLK") uses MHz to display the clock frequency value, which is the frequency of the signal S _CLK . The fourth column (labeled "f _C ") shows the center frequency of one of the radio signals processed in the transceiver. The values of the first three rows in the fourth column are the output signal S _LO1 frequency of the voltage controlled oscillator 204, and the fourth row of the fourth column is the frequency of the signal S _L02 after the fixed frequency divider 205. The second column (labeled "f _min ") and the fourth column (labeled "f _max ") are the lowest and highest frequencies of the signal being processed in the transmitter. The minimum and maximum frequencies are related to the bandwidth and center frequency. The sixth column (labeled "N") is the total integer divide value of all the divider chains in the feedback loop, which is generated by the frequency dividers 205-208 in the divider chain. This value may be different as a result of the variable frequency divider 208 providing different frequency division values. The seventh column (labeled "M") is the total integer divide value of a sequence of frequency dividers 205, 206, and 210 between the output of the voltage controlled oscillator 204 and the output of the clock signal S _CLK . Since the frequency dividers 205, 206, and 210 are fixed frequency dividers with respect to the divided integer values of 2, 2, and 8, the values in the seventh column are all 32.

In one aspect in accordance with the present invention, a 40 MHz reference signal S _REF frequency is provided by the reference signal generator 200 to the phase/frequency detector 201. The variable frequency divider 208 provides a divide value of 21. Therefore, the total frequency division value N of the frequency divider chain is 168, and the frequency of S _LO1 outputted by the voltage control oscillator 204 is the center frequency f _c = 6720 MHz. The frequency of the S _ADC supplied to the ADC/DAC 209 is 1680 MHz. The ADC/DAC 209 has an oversampling rate of 2, so the bandwidth BW = 840 MHz. Therefore, f _min = 6300 MHz and f _max = 7140 MHz. The clock signal S _CLK has a frequency of CLK = 210 MHz.

As shown in the second row, when the frequency division value of the variable frequency divider 208 is changed to 25, the total frequency division value will become N=200, and the center frequency is f _c = 8000 MHz, and the bandwidth BW= 1000 MHz, clock frequency CLK = 250 MHz, f _min = 7500 MHz and f _max = 8500 MHz. Thus, changing the total divide value of the divider chain not only changes the frequency at which the voltage controlled oscillator 204 is used for frequency mixing, but also changes the frequency values of other loops, such as the frequency of the S _ADC . At the same time, the frequency BW and the frequency of the clock CLK are different.

The third row describes the associated combined value when the variable frequency divider 208 selects a divide value of 29. In this case, N = 232, the center frequency is f _c = 9280 MHz, the bandwidth BW = 1160 MHz, the clock frequency CLK = 290 MHz, f _min = 8700 MHz and f _max = 9860 MHz.

According to one aspect of the present invention, it will be described with reference to the fourth row, from which the output of the voltage controlled oscillator 204 used for mixing is taken to handle a different one. Center frequency f _c . Specifically, the signal S _L02 following the first fixed frequency divider circuit 205 of the frequency divider chain is used to provide the center frequency f _c = 4000 MHz. Since the variable frequency divider 208 is selected to have a divide value of 25 (hence, N = 200), the bandwidth BW and the clock signal CLK are the same as described in the second row. Only the center frequency f _c, the minimum frequency f _min and a maximum frequency f _max different.

According to one aspect of the invention, the table shown in Figure 3 is a frequency-band scheme for a super wideband (UWB) transceiver and/or receiver. UWB is a general term for a type of radio communication. The transmitted RF energy distribution exceeds the 500MHz spectrum, and its frequency. The range is from 3.1 GHz to 10.6 GHz and is defined by the FCC's published UWB in February 2002. For example, the two parts of the spectrum that can be used in UWB include 3.1-5.15 GHz and 5.8-10.6 GHz.

Specifically, the local oscillator circuit shown in Figure 2 can be used to generate a local oscillator signal having a center frequency as shown in the table of Figure 3. The local oscillator signals are then used in the receive chain 105 to downconvert the received RF signals, and/or in the transmit chain 116, a signal is upconverted and transmitted. Thus, the local oscillator circuit 114 and/or 119 can generate and/or receive signals of one or more of the four frequency bands described in the table of FIG.

In some aspects of the invention, different reference frequencies can be provided to the phase locked loop. For example, as depicted in FIG. 4, a crystal oscillator (XTAL) 401 produces a stable reference frequency that is divided by a programmable frequency divider circuit 402 coupled to the control interface 218. The frequency divider circuit 402 selects different frequency division values based on instructions received from the control interface 218. Thus, a combination of an optional reference frequency and a selectable divider value N can be employed to select the center frequency f _c , the bandwidth BW, the clock frequency CLK, and/or other phase locks. The signal frequency of the loop output. In one aspect of the invention, several combinations of the reference signal S _REF frequency and the total divide value N can be generated to provide a substantially identical ADC frequency (eg, frequency bandwidth BW) to a different center. Frequency f _c .

Figure 5 is a flow diagram of a method in accordance with one aspect of the present invention. In order to simultaneously generate a plurality of reference frequencies from a phase locked loop, a reference signal, such as a stable and fixed reference clock signal, is inserted into the phase locked loop 501. For example, the reference signal can be generated by a crystal oscillator and coupled to one of the phase/frequency detectors in the phase locked loop.

The phase locked loop includes a voltage controlled oscillator that is based on a control voltage An oscillating signal 502 is generated, and a phase/frequency detector for comparing the phase of the oscillator signal with the input reference signal and generating an error signal based on the detected phase difference. The phase locked loop includes a loop filter for filtering the error signal and generating a control voltage for use by the voltage controlled oscillator. Thus, the frequency of the voltage controlled oscillator signal can be varied by changing the frequency of the reference signal and/or one of the feedback paths coupling the output of the voltage controlled oscillator to the phase/frequency detector. A variable frequency divider can be used to vary the frequency of the voltage controlled oscillator signal.

In one aspect of the invention, the feedback path includes a sequence of connected divider chains. A first local oscillator signal is output 503 from the feedback path. The first local oscillator signal may comprise an output of the voltage controlled oscillator or it may comprise an output of the frequency divider circuit of one of the frequency divider chains connected by the sequence.

In the feedback path, the first local oscillator signal is divided by frequency 504 by at least one of the frequency divider circuits of the sequentially connected divider chain. A second local oscillator signal having a frequency different from the first local oscillator signal, the divider chain output 505 connected by the sequence in the feedback path.

In one aspect of the invention, the sequence-connected frequency divider chain includes at least a first frequency divider circuit and a second frequency divider circuit. The divider chain includes a first local oscillator output coupled prior to the first frequency divider circuit for outputting a first local oscillator signal having a first frequency. The divider chain further includes a second local oscillator output coupled prior to the second frequency divider circuit for outputting a second local oscillator having a second frequency and different from the first frequency signal. Typically, the second frequency is less than the first frequency. The first local oscillator signal can be used in a mixer for up-conversion and/or down-conversion in transceiving The signal in the machine, while the second local oscillator signal can be used in a different part of the transmitter function, such as a clock signal for an ADC.

The phase-locked loop circuit and method described in the present invention can operate in an integer-N mode or a fractional-N mode. The local oscillation signal generated by an integer phase-locked loop may exhibit a relatively large amount of phase noise. When the phase locked loop operates, the frequency of the signal will change and be controlled in a frequency band determined by the bandwidth of the loop filter. In a fractional phase-locked loop, the frequency of the comparison reference clock signal can be higher. Therefore, the loop filter can have a higher bandwidth to suppress phase noise. The fractional phase-locked loop topology can therefore be used to generate a local oscillator signal with less phase noise than a local oscillator signal generated using an integer phase-locked loop topology.

The methods and systems described herein are merely illustrative of specific aspects of the invention. It will be appreciated that those skilled in the art will be able to devise various configurations that are embodied within the scope of the invention. Moreover, all of the examples and conditional language cited herein are for the purpose of teaching purposes only, and are intended to aid the understanding of the principles of the invention. The present invention and its related references are for explanation and are not limited to the examples and conditions of these specific references. In addition, all of the principles and aspects of the present invention, as well as the specific examples thereof, are intended to include equivalents of the structure and function. In addition, the present invention is intended to be in terms of equivalents, and equivalents of the

200‧‧‧Reference signal generator/crystal oscillator circuit

201‧‧‧ phase/frequency detector

202‧‧‧Charge pump

203‧‧‧ Loop Filter

204‧‧‧Voltage Controlled Oscillator

205, 206, 207‧‧‧ except 2 frequency divider circuit

208‧‧‧Variable frequency divider circuit

209‧‧‧Digital/analog converters, analog/digital converters

210‧‧‧Densor circuit

218‧‧‧Control interface

Claims (15)

A phase-locked loop circuit includes: a phase/frequency detector; a voltage controlled oscillator (VCO); a sequence of connected frequency divider chains located at an output of the voltage controlled oscillator and the phase/frequency detector a coupled feedback path; and a plurality of local oscillator outputs distributed at different locations within the divider chain for providing at least one of the first seismic signals having a first frequency and having a first One of the two frequencies, the second seismic semaphore, the second frequency being different from the first frequency. The circuit of claim 1, wherein the frequency divider chain includes at least one variable frequency divider circuit for enabling a selectable value of at least one of the first frequency and the second frequency. The circuit of claim 2, wherein at least one of the variable frequency divider circuit and the output of the present oscillator are configured to generate a plurality of different values having the first frequency, each of Paired with approximately equal values having the second frequency. The circuit of claim 1, further comprising a reference signal generator configured to provide a selectable reference frequency to the phase/frequency detector. The circuit of claim 1, wherein the circuit is configured to operate in at least one of an integer-N mode or a fractional-N mode. A phase-locked loop circuit includes: a phase/frequency detector; a voltage controlled oscillator (VCO); a sequence of connected frequency divider chains located at an output of the voltage controlled oscillator and the phase In a feedback path coupled to the bit/frequency detector, the divider chain includes a first frequency divider circuit, a first local oscillator output coupled to the first frequency divider circuit for use in Providing a first local oscillator signal having a first frequency, a second frequency divider circuit, and a second local oscillator output coupled to the second frequency divider circuit for providing a A second local oscillation signal of the second frequency, the second frequency being different from the first frequency. The circuit of claim 6 wherein the frequency divider chain comprises at least one variable frequency divider circuit for enabling a selectable value of at least one of the first frequency and the second frequency. The circuit of claim 7, wherein the variable frequency divider circuit, the first current oscillator output, and the second current oscillator output are configured to generate a plurality of There are different values for the first frequency and approximately equal values for the second frequency. The circuit of claim 6 further comprising a reference signal generator configured to provide a selectable reference frequency to the phase/frequency detector. The circuit of claim 6, wherein the circuit is configured to operate in at least one of an integer mode or a fractional mode. A method for simultaneously generating a plurality of reference frequencies from a phase locked loop (PLL), comprising: inserting a reference signal into the phase locked loop; generating a voltage controlled oscillating signal in the phase locked loop; Generating a first local oscillator signal in a feedback path of the loop, the local oscillator signal having a first frequency; and performing frequency on at least the first local oscillator signal in a feedback path of the phase locked loop Frequency division to generate a second local oscillator signal having a different one of the first frequencies Two frequencies; and simultaneously outputting the first local oscillator signal and the second local oscillator signal. The method of claim 11, wherein the frequency division is performed by at least one fixed frequency divider circuit and at least one variable frequency divider circuit. The method of claim 11, wherein the phase locked loop is configured to operate in at least one of an integer mode and a fractional mode. The method of claim 11, further comprising selecting at least one of the selectable reference frequency and the selectable divide value for selecting at least one of the first frequency and the second frequency . The method of claim 11, further comprising generating a plurality of different values having the first frequency paired with substantially equal values having the second frequency.