KR101959789B1 - Frequency synthesizer - Google Patents

Abstract

The present invention relates to a broadband frequency synthesizer having high resolution, low phase noise and excellent spurious signal characteristics. According to an embodiment of the present invention, a frequency synthesizer includes: a fixed local oscillation circuit for a clock signal having a fixed frequency, and outputting a local oscillation signal having a fixed frequency; a variable reference frequency oscillation circuit for receiving a clock signal of the fixed local oscillation circuit and a local oscillation signal to output a variable reference frequency; a variable frequency oscillation circuit for receiving a voltage of a loop filter or a digital-to-analog converter (DAC) to output a variable frequency; a multiplication and phase comparison circuit for multiplying the variable reference frequency and comparing a phase of the multiplied variable reference frequency with a phase of the variable frequency of the variable frequency oscillation circuit by using an analog phase comparator; and a phase lock implementation circuit for adjusting a variable frequency of the variable frequency oscillation circuit by adjusting a voltage of the digital-to-analog converter (DAC) and implementing a phase lock of the variable frequency oscillation circuit based on the voltages of the compared phases.

Description

Frequency synthesizer {FREQUENCY SYNTHESIZER}

The present invention relates to a frequency synthesizer.

A broadband frequency synthesizer is needed to detect and analyze broadband communication and electronic signals in electronic warfare systems. In particular, in order to detect and analyze signals of adjacent bands such as communication signals, a stable frequency synthesizer having excellent phase noise characteristics and frequency high resolution characteristics is needed.

Korean Patent Publication No. 10-2004-0047435 (Published on June 05, 2004)

An object of the present invention is to provide a frequency synthesizer which is superior in phase noise characteristics to a conventional frequency synthesizer and can realize a wideband, frequency high resolution, and low noise signal.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a frequency synthesizer including: a fixed local oscillation circuit for outputting a local oscillation signal having a fixed frequency and a clock signal having a fixed frequency; A variable reference frequency oscillation circuit receiving a clock signal of the fixed local oscillator circuit and a local oscillation signal and outputting a variable reference frequency; A variable frequency oscillation circuit receiving a voltage of a loop filter or a digital to analog converter (DAC) and outputting a variable frequency; A multiplication and phase comparison circuit for multiplying the variable reference frequency by the multiplier and for comparing the phase of the multiplied variable reference frequency with the phase of the variable frequency of the variable frequency oscillation circuit using an analog phase comparator; And a phase lock implementation circuit for adjusting the variable frequency of the variable frequency oscillation circuit by adjusting a voltage of the DAC (Digital Analog Converter) and implementing a phase lock of the variable frequency oscillation circuit based on the voltage of the compared phase .

According to the embodiment of the present invention, the fixed local oscillator circuit includes:

An oven controlled crystal oscillator (OCXO) for outputting a stable frequency;

A frequency multiplier for multiplying the output frequency of the OCXO;

A VCO (Voltage Controlled Oscillator) for outputting a variable frequency according to a voltage;

A power divider dividing an output of the VCO into two paths by power distribution;

An analog phase comparator for phase-comparing a signal output from the frequency multiplier with a signal output from the power divider;

A loop filter for removing a spurious signal of a signal output from the analog phase comparator and transmitting a voltage to the VCO;

And a low-pass filter for removing harmonics of the signal output from the power divider.

According to the embodiment of the present invention, the variable reference oscillation circuit includes:

A direct digital synthesizer receiving a clock signal of the fixed local oscillator and outputting a variable frequency signal;

A filter bank 1 for removing unnecessary signals of a variable frequency signal outputted from the direct digital synthesizer;

A frequency multiplier for multiplying the frequency of the signal output from the filter bank 1;

A filter bank 2 for removing unnecessary signals of the signal output from the frequency multiplier;

A mixer for receiving a signal output from the filter bank 2 and a local oscillation signal of the fixed local oscillation circuit to perform frequency mixing;

A filter bank 3 for removing unwanted signals of signals output from the mixer;

A frequency divider for dividing the frequency of the signal output from the filter bank 3;

And a filter bank 4 for removing a spurious signal of the signal output from the frequency divider and outputting a signal obtained by removing a spurious signal by a frequency divider as a variable reference frequency.

According to an embodiment of the present invention, the multiplication and phase comparison circuit includes: a frequency doubler that multiplies a frequency of a signal output from the variable reference oscillation circuit; And an analog phase comparator for comparing the phase of the signal output from the frequency multiplier with the phase of the signal output from the variable frequency oscillation circuit.

According to an embodiment of the present invention, the phase lock implementation circuit may further include: a loop filter that removes and integrates noise of a phase difference signal of the compared phase output from the multiplication and phase comparison circuit, and outputs a voltage; A DAC for outputting a voltage through control of the control unit; And a switch for selecting a path of the DAC and the loop filter and connecting the path of the DAC to the variable frequency oscillation circuit, and a feedback path connecting the signal output from the variable frequency oscillation circuit to the multiplication and phase comparison circuit.

According to an embodiment of the present invention, the variable frequency oscillation circuit includes: a VCO (Voltage Controlled Oscillator) bank receiving a voltage output from the phase lock implementation circuit and outputting a frequency; A power divider for dividing a signal output from the VCO bank into two paths; And a low-pass filter for removing harmonics of the signal output from the power divider.

According to another embodiment of the present invention, the multiplying and phase comparing circuit comprises: a frequency doubler for multiplying a frequency of a signal output from the variable reference oscillation circuit; A bandpass filter for passing only a specific band of the signal output from the frequency multiplier; And an analog phase comparator for comparing the phase of the signal output from the band pass filter and the phase of the signal output from the variable frequency oscillation circuit.

According to another embodiment of the present invention, the phase lock implementation circuit may further include: a loop filter that removes and integrates noise of a phase difference signal of the compared phase output from the multiplication and phase comparison circuit and outputs a voltage; A DAC for outputting a voltage through control of the control unit; A switch for selecting a path of the DAC and the loop filter and connecting the selected path to the variable frequency oscillation circuit; A power amplifier for amplifying a signal output from the variable frequency oscillation circuit; A frequency multiplier for multiplying a frequency signal output from the power amplifier; A band-pass filter for removing unnecessary signals of a frequency signal output from the frequency multiplier; And a feedback path connecting a signal output from the band pass filter to the multiplication and phase comparison circuit.

According to another embodiment of the present invention, the phase lock implementation circuit may further include: a loop filter that removes noise of the phase difference signal output from the multiplication and phase comparison circuit and integrates and outputs a voltage; A DAC for outputting a voltage through the control of the controller; A switch for selecting a path of the DAC and the loop filter and connecting the selected path to the variable frequency oscillation circuit; A mixer for mixing a signal output from the variable frequency oscillation circuit with a fixed local oscillation signal; And a feedback path for connecting a signal output from the mixer to the multiplication and phase comparison circuit.

According to another embodiment of the present invention, the variable frequency oscillation circuit includes: a VCO that receives a voltage output from the phase lock implementation circuit and outputs a frequency; A power divider for dividing a signal output from the VCO into two paths; And a low-pass filter for removing harmonics of the signal output from the power divider.

According to another embodiment of the present invention, the fixed local oscillator circuit includes: an OCXO outputting a stable frequency; A frequency multiplier for multiplying the output frequency of the OCXO; A VCO for outputting a variable frequency according to a voltage; A power divider dividing an output of the VCO into two paths by power distribution; A power amplifier for amplifying a signal output from the power divider; A frequency multiplier 2 for multiplying a frequency signal output from the power amplifier; A band-pass filter for removing unnecessary signals of the frequency signal outputted from the frequency multiplier 2; An analog phase comparator for phase-comparing a signal output from the frequency multiplier with a signal output from the band pass filter; A loop filter for removing a spurious signal of a signal output from the analog phase comparator and transmitting a voltage to the VCO; And a low-pass filter for removing harmonics of the signal output from the power divider.

The details of other embodiments are included in the detailed description and drawings.

The frequency synthesizer according to the present invention is superior in phase noise characteristics to conventional frequency synthesizers, and has the effect of realizing wideband, high frequency, and low-noise signals. That is, the frequency synthesizer according to the present invention is suitable for an electronic warfare and broadband frequency generating apparatus that requires broadband characteristics and low unnecessary signal and phase noise.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention.
2 is an exemplary diagram showing a configuration of a variable reference oscillation circuit.
3 is an exemplary diagram showing a configuration of a multiplying and phase comparing circuit.
4 is an exemplary diagram showing another embodiment of the multiplying and phase comparing circuit.
5 is an exemplary diagram showing a configuration of a phase lock implementation circuit.
6 is a diagram illustrating another embodiment of a phase lock implementation circuit.
7 is a diagram illustrating another embodiment of a phase lock implementation circuit.
8 is an exemplary diagram showing a configuration of a variable frequency oscillation circuit.
9 is an exemplary diagram showing another embodiment of the variable frequency oscillation circuit.
10 is an exemplary view showing a configuration of a fixed local oscillation circuit.
11 is an exemplary view showing another embodiment of the fixed local oscillation circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals are used to designate identical or similar elements, and redundant description thereof will be omitted. The suffix "module" and " part "for the components used in the following description are given or mixed in consideration of ease of specification, and do not have their own meaning or role. In the following description of the embodiments of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the embodiments disclosed herein may be blurred. In addition, it should be noted that the attached drawings are only for easy understanding of the embodiments disclosed in the present specification, and should not be construed as limiting the technical idea disclosed in the present specification by the attached drawings.

In general, the frequency synthesis method is divided into direct analog synthesis, indirect synthesis, and direct digital synthesis, which are also used in combination. A direct digital synthesizer (DDS), which is a direct digital synthesis method, has excellent phase noise and excellent frequency resolution and synchronization speed characteristics when a clock signal having excellent phase noise is used. However, the direct digital synthesis method has poor spurious signal characteristics and has a low maximum output frequency. Especially, since the spurious signal characteristic determines the dynamic range of the receiver, the dynamic range of the receiver is somewhat limited if a direct digital synthesis method with poor spurious characteristics is used.

The indirect frequency synthesis method includes a PLL (Phase Locked Loop) method using a PFD (Phase Frequence Detector) and an analog phase comparator. The PLL method using PFD can output a variable frequency with a higher frequency resolution than that using an analog phase comparator, but the phase noise characteristic is poor due to the use of the frequency divider in the PFD. On the other hand, in the case of the analog phase comparator, since the phase comparison is performed without the division ratio, the influence of the base low noise generated in the phase comparator is small and the phase noise is excellent. In particular, when used as a fixed local oscillation signal, the use of an analog phase comparator is advantageous in terms of phase noise characteristics. Also, when a variable reference frequency having a high frequency resolution is used, a high frequency resolution can be obtained even by using an analog phase comparator without using PFD.

The direct analog synthesis method is a method of obtaining a desired output frequency by up- and down-frequency by using a frequency multiplier, a frequency divider, and a mixer. This results in good phase noise and spurious signal characteristics, but poor frequency resolution characteristics.

In the present invention, an indirect frequency synthesis method using a direct digital synthesizer and an analog phase comparator is used in a large frame. The reference frequency of this structure is used as a variable reference frequency of the direct digital synthesizer to obtain a high frequency resolution characteristic.

만큼 개선되는 구조를 적용했다. 또한, 주파수 동조속도를 개선하기 위해 DAC(Digital to Analog converter)를 이용하였다. 본 발명에서는 우수한 위상잡음 특성과 불요신호 특성 및 주파수 해상도 특성을 갖는 광대역 주파수합성기의 구현 방법을 제공한다.In a structure in which a variable reference frequency of a direct digital synthesizer is used as a reference frequency of an indirect frequency synthesizing method, excellent phase noise characteristics can be obtained by performing phase comparison using an analog phase comparator without division ratio. In addition, this structure can eliminate the broadband unwanted signal of the digital synthesizer directly through the loop filter. However, it is not easy to remove the narrowband unwanted signal of the direct digital synthesizer with a loop filter. Therefore, the unwanted signals of the direct digital synthesizer are mixed using a mixer, a local oscillator signal, and a direct analog synthesis method using a frequency divider

As shown in Fig. Also, DAC (Digital to Analog Converter) is used to improve the frequency tuning speed. The present invention provides a method for implementing a broadband frequency synthesizer having excellent phase noise characteristics, spurious signal characteristics, and frequency resolution characteristics.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Throughout the examples, the same reference numerals denote members performing the same functions and actions.

1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention.

1, the frequency synthesizer according to the embodiment of the present invention includes:

A fixed local oscillation circuit 10 for outputting a clock signal (F _clock ) having a fixed frequency and a local oscillation signal (F _LO ) having a fixed frequency;

A variable reference oscillation circuit 20 for receiving a clock signal F _clock and a local oscillation signal F _{LO of} the fixed local oscillator 10 and outputting a variable reference frequency;

A variable frequency oscillation circuit 40 for receiving a voltage of a loop filter or a digital to analog converter (DAC) and outputting a variable frequency;

A multiplication and phase comparison circuit (30) for multiplying the phase of the variable reference frequency multiplied by the variable reference frequency and the phase of the variable frequency of the variable frequency oscillation circuit (40) using an analog phase comparator;

A phase adjuster for adjusting the variable frequency of the variable frequency oscillator circuit 40 by adjusting the voltage of the digital analog converter (DAC) and for implementing the phase lock of the variable frequency oscillator circuit 40 based on the voltage of the compared phase, Lock implementation circuit 50, and the phase lock implementation circuit 50 implements phase lock of the variable frequency oscillation circuit 40 using a loop filter.

The frequency synthesizer of the present invention is an indirect frequency synthesis frequency synthesizer using a variable reference frequency generated from a direct digital synthesizer. This structure uses an analog phase comparator to perform phase comparison without divider to obtain good phase noise characteristics.

In addition, direct analog synthesis using a mixer and a divider is used to improve the unwanted signal of the direct digital synthesizer. For good phase noise characteristics of the frequency synthesizer, the two phase lock circuits of the fixed local oscillator circuit 10 implement phase-lock without division using an analog phase comparator. One phase lock circuit is used as the clock signal of the direct digital synthesizer 20 of the variable reference oscillation circuit 20 and the other phase lock circuit is used as the local oscillation signal so that the input to the mixer of the variable reference oscillation circuit 20 do.

The output frequency control of the direct digital synthesizer of the variable reference oscillation circuit 20, the DAC output voltage control of the phase lock implementation circuit 50, and the switch path control of the variable reference oscillation circuit 20 using a control unit (not shown) And controls the output frequency of the VCO by connecting a path to be input to a VCO (Voltage Controlled Oscillator) of the frequency oscillation circuit 40. Since the output frequency of the VCO is positioned near the reference frequency by using the DAC, the phase lock time is shortened.

Mixes and divides the local oscillator signal of the direct digital synthesizer of the variable reference oscillator circuit 20 and the local oscillator signal of the fixed local oscillator circuit 10 to generate a variable reference frequency having excellent phase noise and spurious signal characteristics.

On the other hand, in the multiplying and phase comparing circuit 30, in order to phase-compare the variable reference frequency and the feedback output of the variable frequency oscillating circuit 40 one-by-one without division, the analog phase comparator And phase noise characteristics can be improved.

The phase lock implementing circuit 50 receives the phase difference value obtained after the phase comparison, removes noise from the loop filter, and integrates and converts the phase difference value into a voltage. At this time, the control unit controls the switch to connect the loop filter, thereby realizing the phase lock of the VCO of the variable frequency oscillation circuit (40). The voltage value output from the loop filter is input to the ADC (Analog to Digital Converter) to monitor the phase lock status. If the phase lock is released, the control unit controls the DAC after connecting the switch to the DAC and the VCO of the variable frequency oscillation circuit (40). After that, the switch is controlled again to connect the loop filter and the VCO, and then the phase lock is attempted.

Hereinafter, each configuration of the frequency synthesizer according to the embodiment of the present invention will be described in detail.

2 is an exemplary diagram showing the configuration of the variable reference oscillation circuit 20. That is, FIG. 2 is a diagram illustrating a configuration for variable frequency output having excellent phase noise, spurious signals, and frequency resolution characteristics, in order to use the variable reference oscillation circuit 20 as a reference frequency of the phase lock loop.

As shown in Fig. 2, the variable reference frequency oscillation circuit 20 includes:

A direct digital synthesizer (DDS) 21 for receiving a clock signal of the fixed local oscillator and outputting a variable frequency signal;

A filter bank 1 (22) for removing unnecessary signals of a variable frequency signal outputted from the direct digital synthesizer (21);

A frequency multiplier (23) for multiplying the frequency of the signal output from the filter bank 1 (22);

A filter bank 2 (24) for eliminating unnecessary signals of the signal output from the frequency multiplier (23);

A mixer 25 for mixing the signal output from the filter bank 2 (24) and the local oscillation signal of the fixed local oscillator circuit 10;

A filter bank 3 (26) for canceling a spurious signal of the mixed signal output from the mixer 25;

A frequency divider 27 for dividing the frequency of the signal output from the filter bank 3 (26);

And a filter bank 4 28 for removing unnecessary signals of the signal output from the frequency divider 27 and multiplying the signal from which the unnecessary signal has been removed as a variable reference frequency and outputting it to the phase comparison circuit 30 .

The purpose of the variable reference oscillation circuit 20 is to output a high-resolution variable reference frequency which improves the spurious signal characteristics. The output of the direct digital synthesizer is mixed with the local oscillation signal of the fixed local oscillator circuit 10 to be described later, and the signal is frequency-divided and then divided, whereby the spurious signal characteristic can be improved. Therefore, it is important to design an appropriate frequency plan, such as selecting the frequency range where the output frequency of the direct digital synthesizer is far enough to be filtered out of the unwanted signal, and selecting the local oscillation frequency of the fixed local oscillator circuit.

만큼 나빠진다. 주파수상향을 위해 혼합기(25)에서 국부발진신호와 혼합된 후, 불요신호를 필터뱅크3(26)을 통해 제거한다. The direct digital synthesizer (DDS) 21 receives the clock frequency from the fixed local oscillator 10 and generates a range up to half of the clock frequency at the output frequency. The output frequency of the direct digital synthesizer 21 should be selected so that the unnecessary signal is sufficiently separated from the output frequency so as to be capable of being filtered. The filter bank 1 (22) is then used to remove the unwanted signal to minimize unwanted signals in the desired output frequency range. A multiplier 23 is used to extend the frequency bandwidth of the signal that minimizes the unwanted signal. And passes through filter bank 2 (24) to remove the spurious signal of the multiplied signal. The characteristic of the unnecessary signal after passing through the multiplier 23 is

. After mixing with the local oscillator signal at the mixer 25 for frequency upwards, the unwanted signal is removed through filter bank 3 26.

만큼 좋아지게 된다. 예컨대, 직접디지털합성기의 출력주파수가 500~900 MHz이고 불요신호 특성이 -55 dBc라면 상기 신호가 2체배기를 통과하여 1000~1800MHz로 변환된 후, 5.2 GHz의 국부발진신호와 혼합된 후 8분주기를 통과하면 775~875MHz가 출력된다. 이때의 불요신호 특성은 -67 dBc가 된다. 필터뱅크4(28)를 거친 신호는 후술할 체배 및 위상비교회로(30)로 입력된다.The signal output from the filter bank 3 (26) is divided through the frequency divider 27 and then removed from the filter bank 4 (28). The spurious signal characteristic after passing through the frequency divider 27

. For example, if the output frequency of the direct digital synthesizer is 500 to 900 MHz and the unwanted signal characteristic is -55 dBc, the signal is converted to 1000 to 1800 MHz through a doubler, mixed with a 5.2 GHz local oscillator signal, When the period passes, 775 to 875 MHz is output. At this time, the spurious signal characteristic is -67 dBc. The signal passed through the filter bank 4 (28) is input to the multiplication and phase comparison circuit 30 to be described later.

3 is an exemplary diagram showing a configuration of the multiplying and phase comparing circuit 30. [

As shown in Fig. 3, the multiplication and phase comparison circuit 30 includes:

A frequency doubler (31) for multiplying the frequency of the signal output from the variable reference oscillation circuit (20) by several to several tens;

And an analog phase comparator 32 for comparing the phase of the signal output from the frequency multiplier 31 with the phase of the signal output from the variable frequency oscillation circuit 40.

The multiplication and phase comparison circuit 30 may use components of the frequency multiplier and the analog phase comparator 32, but it may be constituted by one component SPD (sampling phase detector). The SPD generates a plurality of harmonics that are integral multiple of the frequency of the input signal. And performs a phase comparison with the output of the variable frequency oscillation circuit 40 to be described later. Since the reference signal and the feedback signal are compared one by one without dividing ratio when performing the phase comparison using the SPD, the phase noise characteristic is excellent because the fundamental noise is reduced compared with the case of performing the phase comparison using the PFD. The phase difference output after the phase comparison is input to the phase lock implementation circuit 50 to be described later.

4 is an exemplary diagram showing another embodiment of the multiplying and phase comparing circuit 30. In FIG.

As shown in Fig. 4, the multiplying and phase comparing circuit 30 includes:

A frequency doubler (31) for multiplying a frequency of a signal output from the variable reference oscillation circuit (20);

A band pass filter (33) for passing only a specific band of the signal output from the frequency multiplier (31);

And an analog phase comparator 32 for comparing the phase of the signal output from the band pass filter 33 with the phase of the signal output from the variable frequency oscillation circuit 40.

Instead of the SPD shown in FIG. 3, a harmonic generator such as a SRD (Step Recovery Diode) is used to generate harmonic waves of several to several tens of times, and only desired harmonics are selected using the bandpass filter 33 to perform phase comparison. In this case, it is possible to reduce the periodic low noise generated when a plurality of harmonics are mixed.

5 is an exemplary diagram showing the configuration of the phase lock implementation circuit 50. [

As shown in Fig. 5, the phase lock implementation circuit 50 includes:

A loop filter (51) for eliminating and integrating the noise of the phase difference signal of the compared phase output from the multiplying and phase comparing circuit (30) and outputting the voltage after outputting the integrated signal;

A DAC (Digital to Analog Converter) 52 for outputting a voltage through the control of the control unit;

A switch 53 for selecting the paths of the DAC 52 and the loop filter 51 and connecting them to the variable frequency oscillation circuit 40;

And an ADC (54) for monitoring a voltage by outputting a voltage input to the variable frequency oscillation circuit to a control unit, and outputting the signal output from the variable frequency oscillation circuit (40) to the multiplication and phase comparison circuit .

The phase difference output from the multiplication and phase comparison circuit 30 is input to the loop filter 51 of the phase lock implementation circuit 50. The loop filter 51 serves as a low-pass filter and determines the phase noise bandwidth of the phase lock implementation circuit 50. The voltage output from the loop filter 51 is input to the switch 53. The switch 53 selects one of the DAC 52 and the loop filter 51 according to the control command of the control unit, ) VCO (Voltage Controlled Oscillator).

The DAC 52 converts the digital signal into an analog signal. When the DAC 52 receives the voltage value to be output from the control unit, the DAC 52 outputs the corresponding voltage value to the output of the VCO of the variable frequency oscillation circuit 40 The frequency is set. At this time, the DAC 52 quickly adjusts the variable frequency of the variable frequency oscillation circuit 40 to a variable reference frequency, thereby shortening the phase lock time. The voltage passing through the switch 53 is converted by the ADC and the variable Is input to the VCO of the frequency oscillating circuit (40).

The ADC converts the analog signal into a digital signal, converts the voltage value input to the VCO into a digital value, inputs the voltage value to the controller, checks whether a proper voltage value is output, and monitors the phase lock state. The signal output from the variable frequency oscillation circuit 40 is fed back to the phase and phase comparison circuit 30 for phase comparison.

When the power is turned on, the control unit controls the direct digital synthesizer and the filter bank of the variable reference oscillation circuit 20, the DAC and the switch of the phase lock implementation circuit 50, the variable frequency oscillation circuit 40 ) Of the VCO. First, the direct digital synthesizer is controlled to set the output frequency, and the corresponding filter bank band is selected. The output of the variable reference oscillation circuit 20 is multiplied and multiplied by several to several tens in the phase comparison circuit 30 and the output frequency of the VCO of the variable frequency oscillation circuit 40 are adjusted so that the voltage of the DAC Value and the switch controls to select the DAC. The phase lock is then implemented by allowing the switch to select a loop filter. At this time, the control unit monitors the output value of the ADC to check the phase lock state. When changing the output frequency value of the frequency synthesizer, repeat the above procedure.

6 is a diagram illustrating another embodiment of the phase lock implementation circuit 50.

As shown in Fig. 6, the phase lock implementation circuit 50, according to another embodiment,

A loop filter (51) for eliminating and integrating the noise of the phase difference signal of the compared phase outputted from the multiplication and phase comparison circuit and outputting the voltage after outputting the integrated signal;

A DAC 52 for outputting a voltage through the control of the control unit;

A switch 53 for selecting the paths of the DAC 52 and the loop filter 51 and connecting them to the variable frequency oscillation circuit 40;

An ADC 54 for outputting a voltage input to the variable frequency oscillation circuit 40 to a control unit to monitor a voltage;

A power amplifier (61) for amplifying a signal output from the variable frequency oscillation circuit (40);

A frequency multiplier 62 for multiplying a frequency signal output from the power amplifier 61;

A band-pass filter (63) for removing unnecessary signals of the frequency signal outputted from the frequency multiplier (62);

And a feedback path for connecting the signal output from the band-pass filter 63 to the multiplication and phase comparison circuit 30. [

만큼 개선되는 효과를 얻을 수 있다. 하지만 도 5의 주파수합성기의 출력주파수를 동일하게 도 6에서 출력하기 위해서는 가변기준주파수발진회로(20)의 분주비를 추가한 체배수만큼 낮춰줘야한다. 대역통과필터(63)는 주파수체배기(62)를 통과한 신호의 불요신호를 제거하기 위해 사용된다. 예컨대 도 5의 가변기준주파수발진회로(20)에서 8분주기를 사용하였다면, 도 6의 위상잠금구현회로(50)의 궤환회로에 2체배기를 추가할 경우, 가변기준주파수발진회로(20)에서는 8분주기 대신 4분주기를 사용해야 도 5와 같은 주파수합성기의 출력주파수를 얻을 수 있다.The amplifier 61 is used to match the input power of the frequency multiplier 62. When the frequency multiplier 62 is used for a feedback circuit,

Can be obtained. However, in order to output the output frequency of the frequency synthesizer of FIG. 5 in the same manner as in FIG. 6, the frequency division ratio of the variable reference oscillation circuit 20 must be decreased by a multiple of the addition frequency. The band-pass filter 63 is used to remove spurious signals of the signal passed through the frequency multiplier 62. For example, if the 8-cycle period is used in the variable reference oscillation circuit 20 of FIG. 5, when the 2-multiplier is added to the feedback circuit of the phase lock implementation circuit 50 of FIG. 6, the variable reference oscillation circuit 20 The output frequency of the frequency synthesizer shown in FIG. 5 can be obtained by using a 4-minute cycle instead of the 8-minute cycle.

7 is a diagram illustrating another embodiment of the phase lock implementation circuit 50. In FIG.

As shown in Fig. 7, the phase lock implementation circuit 50 according to yet another embodiment includes:

A loop filter 51 for eliminating and integrating the noise of the phase difference signal output from the multiplying and phase comparing circuit 30 and outputting a voltage;

A DAC 52 for outputting a voltage through the control of the controller;

A switch 53 for selecting the paths of the DAC 52 and the loop filter 51 and connecting them to the variable frequency oscillation circuit 40;

An ADC 54 for outputting a voltage input to the variable frequency oscillation circuit 40 to a control unit to monitor a voltage;

A mixer 71 for mixing the signal output from the variable frequency oscillation circuit 40 with a fixed local oscillation signal;

And a feedback path for connecting the signal output from the mixer 71 to the multiplication and phase comparison circuit 30. [

7, the mixer 71 and the local oscillation signal F _LO1 are added to the path through which the output of the variable frequency oscillation circuit 40 is fed back. The local oscillation signal F _LO1 and the frequency fed back are mixed in the mixer 71 to lower the frequency to be input to the analog phase comparator. This is used to lower the comparison frequency in the phase comparator or to increase the output frequency of the frequency synthesizer while fixing the comparison frequency of the phase comparator. An application for lowering the comparison frequency of the phase comparator corresponds to the case where it is necessary to increase the frequency division ratio to further improve the spurious signal characteristic of the variable reference oscillation circuit 20. [

8 is a diagram showing an example of the configuration of the variable frequency oscillation circuit 40. As shown in Fig.

As shown in Fig. 8, the variable frequency oscillation circuit 40 includes:

A VCO (Voltage Controlled Oscillator) 41 for receiving a voltage output from the phase lock implementing circuit 50 and outputting a frequency;

A power divider (42) for dividing the signal output from the VCO (41) into two paths;

And a low pass filter (43) for removing harmonics of the signal output from the power divider (42). That is, the variable frequency oscillation circuit 40 includes a VCO 41 having a function of adjusting an output frequency by using a voltage, a power divider 42 for distributing the power and delivering the power to two paths, And a low-pass filter 43 for attenuating the signal.

The VCO 41 receives the voltage of the DAC or the loop filter of the phase lock implementation circuit 50 and outputs the frequency. This signal is distributed to the two paths via the power divider 42, and one path is used as the output of the frequency synthesizer after harmonic elimination through the low-pass filter 43. One other path is input to the phase lock implementation circuit 50 and used as a feedback signal.

Fig. 9 is an exemplary diagram showing another embodiment of the variable frequency oscillation circuit 40. Fig.

As shown in Fig. 9, the variable frequency oscillation circuit 40 according to another embodiment includes:

A VCO (Voltage Controlled Oscillator) bank 41A receiving a voltage output from the phase lock implementation circuit and outputting a frequency;

A power divider (42) for dividing the signal output from the VCO bank (41A) into two paths;

And a low pass filter (43) for removing harmonics of the signal output from the power divider (42).

For example, when one VCO is used to obtain a desired output frequency band, the VCO bank 41A including a plurality of VCOs is used. The VCO is controlled by controlling the power of the VCO in the control unit, turning on the VCO for the band to be used, and turning off the other VCO.

10 is a diagram showing an example of the configuration of the fixed local oscillator 10.

As shown in Fig. 10, the fixed local oscillator circuit 10 includes:

An OCXO (Oven Controlled Crystal Oscillator) 11 for outputting a stable frequency;

A frequency doubler (12) for multiplying the output frequency of the OCXO (11) by several to several tens;

A VCO 15 for outputting a variable frequency according to a voltage;

A power divider (16) for dividing the output of the VCO into two paths by power distribution;

An analog phase comparator (13) for phase-comparing a signal output from the frequency multiplier (12) and a signal output from the power divider (16);

A loop filter 14 for removing a spurious signal of a signal output from the analog phase comparator and delivering a voltage to the VCO 15;

And a low pass filter (17) for removing harmonics of the signal output from the power divider (16).

The fixed local oscillator circuit 10 is a two phase lock circuit, and the phase lock type is a system using an SPD. In this case, since the reference frequency and the feedback frequency are compared one-to-one in the analog phase comparator, the phase noise is superior to the general phase lock circuit. The reference frequency uses the output of the OCXO multiplied by several tens in the multiplier 12 having excellent phase noise characteristics and the feedback frequency is obtained by the phase comparator 13 using the output of the VCO 15 fed back through the power divider 16. [ . The output of the phase comparator 13 is input to a low-pass filter 17 and a loop filter that determines the bandwidth of the phase lock circuit, and then the output of the loop filter is input to the VCO 15 to implement phase lock. The output of the fixed local oscillator circuit 10 is output by removing harmonics through the low-pass filter 17. [

11 is an exemplary diagram showing another embodiment of the fixed local oscillator 10.

11, in the fixed local oscillator circuit 10 according to another embodiment,

An OCXO 11 for outputting a stable frequency;

A frequency doubler (12) for multiplying the output frequency of the OCXO (11) by several to several tens;

A VCO 15 for outputting a variable frequency according to a voltage;

A power divider (16) for dividing the output of the VCO (15) into two paths by power distribution;

A power amplifier 111 for amplifying a signal output from the power divider 16;

A frequency multiplier 2 112 for multiplying a frequency signal output from the power amplifier 111;

A band pass filter 113 for removing unnecessary signals of the frequency signal output from the frequency multiplier 112;

An analog phase comparator (13) for phase-comparing a signal output from the frequency multiplier (12) and a signal output from the band pass filter (113);

A loop filter 14 for removing a spurious signal of a signal output from the analog phase comparator 13 and delivering a voltage to the VCO 15;

And a low pass filter (17) for removing harmonics of the signal output from the power divider (16). That is, the amplifier 111, the frequency multiplier 112, and the band-pass filter 113 are added to the path through which the output of the VCO 15 of the fixed local oscillation circuit 10 is fed back via the power divider 16.

만큼 개선되는 효과를 얻을 수 있다. 하지만 도 10의 고정국부발진회로(10)의 출력주파수를 동일하게 도 11에서 출력하기 위해서는 OCXO(11)의 체배수를 추가한 체배수만큼 높여줘야한다. 대역통과필터(113)는 주파수체배기(112)를 통과한 신호의 불요신호를 제거하기 위해 사용된다. 예컨대, 도 10의 100 MHz OCXO(11)의 출력이 24 체배된 후 VCO(15)의 2400 MHz와 위상비교기(13)에서 2400 MHz의 비교주파수로 위상비교되는 경우에, 도 11에 궤환경로에 2체배기를 추가할 경우 OCXO(11)의 출력의 24체배는 48체배로 변경해서 4800 MHz 비교주파수로 위상비교해야 도 10의 고정국부발진회로(10)의 출력주파수와 동일해진다. The amplifier 111 is used to match the input power of the frequency multiplier 12. When the frequency multiplier 12 is used for a feedback circuit,

Can be obtained. However, in order to output the output frequency of the fixed local oscillation circuit 10 of FIG. 10 in the same manner as in FIG. 11, the number of sine waves of the OCXO 11 must be increased by a multiple of the sine wave. The bandpass filter 113 is used to remove spurious signals of the signal that have passed through the frequency multiplier 112. For example, when the output of the 100 MHz OCXO 11 of FIG. 10 is multiplied by 24 and then phase-compared with 2400 MHz of the VCO 15 and the comparison frequency of 2400 MHz by the phase comparator 13, When the multiplier is added, the multiplication of 24 times the output of the OCXO 11 is multiplied by 48 times, and the phase comparison is made with the 4800 MHz comparison frequency to become equal to the output frequency of the fixed local oscillator 10 of FIG.

As described above, the frequency synthesizer according to the present invention is superior in phase noise characteristics to a conventional frequency synthesizer, and has the effect of realizing a wideband, frequency high-resolution, and low-noise signal. That is, the frequency synthesizer according to the present invention is suitable for an electronic warfare and broadband frequency generating apparatus that requires broadband characteristics and low unnecessary signal and phase noise.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

Claims (13)

A fixed local oscillation circuit for outputting a local oscillation signal having a fixed frequency and a clock signal having a fixed frequency;
A variable reference frequency oscillation circuit receiving a clock signal of the fixed local oscillator circuit and a local oscillation signal and outputting a variable reference frequency;
A variable frequency oscillation circuit receiving a voltage of a loop filter or a digital to analog converter (DAC) and outputting a variable frequency;
A multiplication and phase comparison circuit for multiplying the variable reference frequency by the multiplier and for comparing the phase of the multiplied variable reference frequency with the phase of the variable frequency of the variable frequency oscillation circuit using an analog phase comparator;
And a phase lock implementation circuit for adjusting a voltage of the DAC to adjust a variable frequency of the variable frequency oscillation circuit and implementing a phase lock of a variable frequency oscillation circuit based on the voltage of the compared phase,
Wherein the variable reference oscillation circuit comprises:
The output of the direct digital synthesizer is multiplied by a multiplier and mixed with the local oscillation signal to increase the frequency and remove unwanted signals through the frequency divider,
The phase lock implementation circuit comprises:
Wherein the phase lock of the frequency variable oscillation circuit is implemented using the loop filter, and the voltage value output from the loop filter is input to an ADC (Analog to Digital Converter) to monitor the phase lock state.
delete 2. The apparatus of claim 1, wherein the fixed local oscillator circuit comprises:
An oven controlled crystal oscillator (OCXO) for outputting a stable frequency;
A frequency multiplier for multiplying the output frequency of the OCXO;
A VCO (Voltage Controlled Oscillator) for outputting a variable frequency according to a voltage;
A power divider dividing an output of the VCO into two paths by power distribution;
An analog phase comparator for phase-comparing a signal output from the frequency multiplier with a signal output from the power divider;
A loop filter for removing a spurious signal of a signal output from the analog phase comparator and transmitting a voltage to the VCO;
And a low-pass filter for removing harmonics of a signal output from the power divider. 2. The variable-frequency oscillation circuit according to claim 1,
A direct digital synthesizer receiving a clock signal of the fixed local oscillator and outputting a variable frequency signal;
A filter bank 1 for removing unnecessary signals of a variable frequency signal outputted from the direct digital synthesizer;
A frequency multiplier for multiplying the frequency of the signal output from the filter bank 1;
A filter bank 2 for removing unnecessary signals of the signal output from the frequency multiplier;
A mixer for receiving a signal output from the filter bank 2 and a local oscillation signal of the fixed local oscillation circuit to perform frequency mixing;
A filter bank 3 for removing unwanted signals of signals output from the mixer;
A frequency divider for dividing the frequency of the signal output from the filter bank 3;
And a filter bank (4) for removing a spurious signal of the signal output from the frequency divider and outputting a signal from which a spurious signal is removed by a frequency divider as a variable reference frequency. The phase comparison circuit according to claim 1,
A frequency multiplier for multiplying a frequency of a signal output from the variable reference oscillation circuit;
And an analog phase comparator for comparing a phase of a signal output from the frequency multiplier with a phase of a signal output from the variable frequency oscillation circuit. 2. The circuit of claim 1,
A loop filter for eliminating and integrating the noise of the phase difference signal of the compared phase output from the multiplication and phase comparison circuit and outputting a voltage;
A DAC for outputting a voltage through control of a control unit;
A switch for selecting a path of the DAC and the loop filter and connecting the selected path to the variable frequency oscillation circuit;
And an ADC for outputting a voltage input to the variable frequency oscillation circuit to a controller to monitor a voltage,
And a feedback path for coupling the signal output from the variable frequency oscillation circuit to the multiplication and phase comparison circuit. The variable frequency oscillation circuit according to claim 1,
A VCO (Voltage Controlled Oscillator) bank receiving a voltage output from the phase lock implementation circuit and outputting a frequency;
A power divider for dividing a signal output from the VCO bank into two paths;
And a low-pass filter for removing harmonics of the signal output from the power divider. The phase comparison circuit according to claim 1,
A frequency multiplier for multiplying a frequency of a signal output from the variable reference oscillation circuit;
A bandpass filter for passing only a specific band of the signal output from the frequency multiplier;
And an analog phase comparator for comparing a phase of a signal output from the band pass filter and a phase of a signal output from the variable frequency oscillation circuit. 2. The circuit of claim 1,
A loop filter for eliminating and integrating the noise of the phase difference signal of the compared phase output from the multiplication and phase comparison circuit and outputting a voltage;
A DAC for outputting a voltage through control of a control unit;
A switch for selecting a path of the DAC and the loop filter and connecting the selected path to the variable frequency oscillation circuit;
An ADC for outputting a voltage input to the variable frequency oscillation circuit to a control unit to monitor a voltage;
A power amplifier for amplifying a signal output from the variable frequency oscillation circuit;
A frequency multiplier for multiplying a frequency signal output from the power amplifier;
A band-pass filter for removing unnecessary signals of a frequency signal output from the frequency multiplier;
And a feedback path for coupling a signal output from the band-pass filter to the multiplication and phase comparison circuit. 2. The circuit of claim 1,
A loop filter for eliminating noise of the phase difference signal output from the multiplication and phase comparison circuit, integrating and outputting a voltage;
A DAC for outputting a voltage through control of a control unit;
A switch for selecting a path of the DAC and the loop filter and connecting the selected path to the variable frequency oscillation circuit;
An ADC for outputting a voltage input to the variable frequency oscillation circuit to a control unit to monitor a voltage;
A mixer for mixing a signal output from the variable frequency oscillation circuit with a fixed local oscillation signal;
And a feedback path for coupling a signal output from the mixer to the multiplication and phase comparison circuit. The variable frequency oscillation circuit according to claim 1,
A VCO for receiving a voltage output from the phase lock implementation circuit and outputting a frequency;
A power divider for dividing a signal output from the VCO into two paths;
And a low-pass filter for removing harmonics of the signal output from the power divider. 2. The apparatus of claim 1, wherein the fixed local oscillator circuit comprises:
OCXO outputting a stable frequency;
A frequency multiplier for multiplying the output frequency of the OCXO;
A VCO for outputting a variable frequency according to a voltage;
A power divider dividing an output of the VCO into two paths by power distribution;
A power amplifier for amplifying a signal output from the power divider;
A frequency multiplier 2 for multiplying a frequency signal output from the power amplifier;
A band-pass filter for removing unnecessary signals of the frequency signal outputted from the frequency multiplier 2;
An analog phase comparator for phase-comparing a signal output from the frequency multiplier with a signal output from the band pass filter;
A loop filter for removing a spurious signal of a signal output from the analog phase comparator and transmitting a voltage to the VCO;
And a low-pass filter for removing harmonics of a signal output from the power divider. 11. The method according to any one of claims 4, 6, 7, 9, and 10,
A direct digital synthesizer of the variable reference oscillation circuit, a filter bank 1-4, a DAC of a phase lock implementation circuit, a switch, and a VCO (Voltage Controlled Oscillator) bank when the output frequency of the frequency synthesizer is selected, And a control unit receiving the output of the ADC.

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