WO2014078311A4 - Frequency synthesis using a phase locked loop - Google Patents
Frequency synthesis using a phase locked loop Download PDFInfo
- Publication number
- WO2014078311A4 WO2014078311A4 PCT/US2013/069691 US2013069691W WO2014078311A4 WO 2014078311 A4 WO2014078311 A4 WO 2014078311A4 US 2013069691 W US2013069691 W US 2013069691W WO 2014078311 A4 WO2014078311 A4 WO 2014078311A4
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frequency
- circuit
- divider
- local oscillator
- phase
- Prior art date
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000003786 synthesis reaction Methods 0.000 title 1
- 230000008878 coupling Effects 0.000 claims abstract 2
- 238000010168 coupling process Methods 0.000 claims abstract 2
- 238000005859 coupling reaction Methods 0.000 claims abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B25/00—Simultaneous generation by a free-running oscillator of oscillations having different frequencies
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A phase locked loop circuit comprises a phase/frequency detector, a voltage-controlled oscillator (VCO), and a divider chain in a feedback path coupling the VCO output to the phase/frequency detector. The divider chain comprises a plurality of sequentially connected divider circuits and a plurality of local oscillator outputs interspersed at different locations within the divider chain, which enables the circuit to simultaneously output multiple oscillator signals having different frequencies.
Claims
1. A frequency synthesizer circuit comprising:
a phase/frequency detector;
a voltage-controlled oscillator (VCO);
a divider chain in a feedback path of a phase locked loop circuit comprising the phase/frequency detector and the VCO, the divider chain comprising a plurality of dividers connected in series in the feedback path; and
a plurality of local oscillator outputs interspersed at different locations within the divider chain to enable the frequency synthesizer circuit to produce a plurality of local oscillator output signals having different frequencies.
2. The circuit recited in Claim 1, wherein the divider chain comprises at least one variable divider circuit for enabling selectable values of at least one of the first frequency and the second frequency.
3. The circuit recited in Claim 2, wherein the at least one variable divider circuit and the local oscillator outputs are configured for generating multiple differing values of the first frequency, each paired with substantially identical values of the second frequency.
4. The circuit recited in Claim 1, further comprising a reference signal generator configured for providing selectable reference frequencies to the phase/frequency detector.
5. The circuit recited in Claim 1, configured to operate in at least one of an integer-N mode and a fractional -N mode.
6. A frequency synthesizer circuit, comprising:
a phase/frequency detector;
a voltage-controlled oscillator (VCO);
a divider chain comprising a first divider connected in series with a second divider in a feedback path coupling the VCO output to the phase/frequency detector, the divider chain comprising a first local oscillator output coupled before the first divider for providing a first local oscillator output signal from the frequency synthesizer having a first frequency, and a second local oscillator output coupled before the second divider for providing a second local oscillator output signal from the frequency synthesizer having a second frequency that is different from the first frequency.
7. The circuit recited in Claim 6, wherein the divider chain comprises at least one variable divider circuit for enabling selectable values of at least one of the first frequency and the second frequency.
15
8. The circuit recited in Claim 7, wherein at least one of the variable divider circuit, the first local oscillator output, and the second local oscillator output is configured for generating multiple differing values of the first frequency and substantially identical values of the second frequency.
9. The circuit recited in Claim 6, further comprising a reference signal generator configured for providing selectable reference frequencies to the phase/frequency detector.
10. The circuit recited in Claim 6, configured to operate in at least one of an integer-N mode and a fractional -N mode.
16
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261726166P | 2012-11-14 | 2012-11-14 | |
US61/726,166 | 2012-11-14 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2014078311A2 WO2014078311A2 (en) | 2014-05-22 |
WO2014078311A3 WO2014078311A3 (en) | 2014-08-21 |
WO2014078311A4 true WO2014078311A4 (en) | 2014-10-23 |
Family
ID=50731811
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2013/069691 WO2014078311A2 (en) | 2012-11-14 | 2013-11-12 | Frequency synthesis using a phase locked loop |
Country Status (2)
Country | Link |
---|---|
TW (1) | TWI650948B (en) |
WO (1) | WO2014078311A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104868911B (en) * | 2015-05-13 | 2017-08-25 | 中国电子科技集团公司第四十一研究所 | broadband phase locking frequency synthesis circuit |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2173659B (en) * | 1985-02-06 | 1988-06-08 | Plessey Co Plc | Frequency synthesisers |
WO1986005045A1 (en) * | 1985-02-21 | 1986-08-28 | Plessey Overseas Limited | Improvement in or relating to synthesisers |
GB2172760B (en) * | 1985-02-21 | 1988-05-18 | Plessey Co Plc | Fractional-n frequency |
GB8512912D0 (en) * | 1985-05-22 | 1985-06-26 | Plessey Co Plc | Phase modulators |
US7522898B2 (en) * | 2005-06-01 | 2009-04-21 | Wilinx Corporation | High frequency synthesizer circuits and methods |
KR100712527B1 (en) * | 2005-08-18 | 2007-04-27 | 삼성전자주식회사 | Spread spectrum clock generator reducing jitter problem |
US7538625B2 (en) * | 2007-02-27 | 2009-05-26 | International Business Machines Corporation | Method and enhanced phase locked loop circuits for implementing effective testing |
US7859344B2 (en) * | 2008-04-29 | 2010-12-28 | Renesas Electronics Corporation | PLL circuit with improved phase difference detection |
-
2013
- 2013-11-12 WO PCT/US2013/069691 patent/WO2014078311A2/en active Search and Examination
- 2013-11-13 TW TW102141222A patent/TWI650948B/en active
Also Published As
Publication number | Publication date |
---|---|
WO2014078311A2 (en) | 2014-05-22 |
TWI650948B (en) | 2019-02-11 |
TW201444296A (en) | 2014-11-16 |
WO2014078311A3 (en) | 2014-08-21 |
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