JP5717408B2 - Injection locking oscillator - Google Patents

Description

  The present invention relates to an injection-locked oscillator that generates a microwave or millimeter-wave signal used for a small and lightweight radio signal.

In a transmitter / receiver of a microwave or millimeter wave radio communication system, a radar system, or an optical communication system, a signal source circuit may be required to have low phase noise characteristics. One means for realizing such a low phase noise signal source circuit is an injection locked oscillator.
The self-oscillation frequency of the injection-locked oscillator is f ′, the frequency substantially equal to f ′ is f, the pulse signal generated from the reference signal having the frequency of f / N is injected into the oscillator, and the output frequency of the oscillator is set to f. Synchronize. At this time, the phase noise of the output signal from the oscillator becomes a value increased by 20 log (N) dB from the phase noise of the reference signal, and is determined only by the multiplication number N. That is, an output signal with low phase noise can be obtained by using a reference signal with low phase noise (see, for example, Non-Patent Document 1).

Jri Lee and one other, “Study of Subharmonic Injection-Locked PLLs”, “IEEE JOURNAL OF SOLID-STATE CIRCUITS”, IEEE, MAY 2009, VOL. 44, NO. 5, p. 1539-1553

  In the injection locked oscillator, the lock range is important. The lock range is the maximum value of the difference between the self-oscillation frequency f ′ of the oscillator and the output frequency f at the time of injection locking in a range where injection locking is applied. The phase noise characteristic of the oscillator output during the injection locking operation is a value obtained by increasing 20 log (N) from the phase noise value of the reference signal in the region where the detuning frequency is smaller than the lock range, but the region where the detuning frequency is larger than the lock range. However, the phase noise reduction effect by injection locking cannot be obtained, and the phase noise characteristic of the oscillator itself is obtained. For this reason, it is preferable to increase the lock range, but generally the lock range tends to decrease as the multiplication factor N increases, and there is a problem that it is difficult to obtain a phase noise reduction effect with an injection locked oscillator having a large N. . For example, in the circuit in Non-Patent Document 1, an injection-locked oscillator is connected in parallel, and the individual multiplication number is reduced to obtain a phase noise reduction effect even when N is large. However, there is a problem that this configuration cannot be realized when N is a number that cannot be factorized.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an injection-locked oscillator in which phase noise is reduced even when the multiplication number is an arbitrarily large number.

Injection-locked oscillator according to the present invention, in the injection-locked oscillator in synchronization with the injected signal is injected comprises an oscillator for oscillating a signal of a self-oscillation frequency, the multiplication factor N content of approximately the same frequency f as the self-oscillation frequency A pulse generation circuit that receives a reference signal having a frequency f / N of 1 and is triggered by the reference signal to generate a pulse having a pulse width 1 / (2 × f), and a pulse and timing generated by the pulse generation circuit differ by at least one of said generated pulse and the pulse number multiplication circuit by combining the pulse outputs as an injection signal generated by the pulse generating circuit, comprising a number of pulses multiplier circuit to generate a pulse, the pulse generator Delay times M / (2 × f) that are different from each other except for all or one of the plurality of pulses output from the circuit, where M is an integer greater than 1 and less than 2N, And at least one delay circuit that delays so as to be, and an XOR circuit that synthesizes a pulse output from the delay circuit, or synthesizes a pulse output from the delay circuit and one pulse removed .

  In the injection-locked oscillator according to the present invention, the number of pulses injected into the oscillator by the pulse number multiplication circuit increases several times, so that the frequency of the injection signal is apparently increased and the effective multiplication number is reduced. As a result, the lock range becomes larger than that of a conventional injection locked oscillator that does not include a pulse number multiplication circuit, and the frequency range in which the phase noise reduction effect can be obtained is widened.

1 is a configuration diagram of an injection locked oscillator according to Embodiment 1 of the present invention. FIG. 6 is a timing chart inside the injection-locked oscillator when the multiplication number N is 8 and the self-excited oscillation frequency of the oscillator 6 is f′Hz. It is a block diagram of the injection locking oscillator which concerns on Embodiment 2 of this invention. It is a block diagram of the injection locking oscillator which concerns on Embodiment 3 of this invention. It is a block diagram of the injection locking oscillator based on Embodiment 4 of this invention. It is a block diagram of the injection locking oscillator which concerns on Embodiment 5 of this invention. It is a block diagram of the injection locking oscillator based on Embodiment 6 of this invention.

A preferred embodiment of an injection locked oscillator according to the present invention will be described below with reference to the drawings.
Embodiment 1 FIG.
1 is a configuration diagram of an injection-locked oscillator according to Embodiment 1 of the present invention.
The injection locked oscillator according to the first embodiment of the present invention has a reference signal input terminal 1 to which a reference signal having a frequency obtained by dividing substantially the same frequency f by a multiplication number N to the self-excited oscillation frequency f ′ of the oscillator 6 is input. And a pulse generation circuit 2 that has an input connected to the reference signal input terminal 1 and is triggered by the reference signal to generate a pulse, and a pulse generated by the pulse generation circuit 2 has a delay time M / (2 × f) (however, , M is an integer greater than 1 and less than 2N), an XOR circuit 5 that outputs an exclusive OR of the pulse generated by the pulse generation circuit 2 and the pulse output by the delay circuit 4a, And an oscillator 6 in which charges output from the XOR circuit 5 are injected and oscillates to output an output signal. The delay circuit 4a and the XOR circuit 5 constitute a pulse number multiplication circuit 3 that increases the number of pulses included in one cycle of the reference signal more than twice.

  The pulse generation circuit 2 is connected to the input of the delay circuit 4 a and one input of the XOR circuit 5. The output of the delay circuit 4a is connected to the other input of the XOR circuit 5. In the XOR circuit 5, an exclusive OR of two inputs, that is, a pulse is output only when a pulse is input to one input, and when no pulse is input to both inputs or a pulse is input together. No pulse is output when

Next, the internal operation of the injection locked oscillator according to Embodiment 1 of the present invention will be described. FIG. 2 is an internal timing chart of the injection-locked oscillator when the multiplication number N is 8 and the self-excited oscillation frequency of the oscillator 6 is f ′ Hz.
Assuming that the reference signal has a frequency fHz substantially the same as the frequency f ′, a pulse signal having a frequency f / 8 is input to the pulse generation circuit 2.
The pulse generation circuit 2 generates a pulse having a pulse width 1 / (2 × f) in synchronization with the rising edge of the reference signal. In this example, the pulse is output in synchronization with the rising edge of the reference signal, but the falling edge may be synchronized, or the pulse may be output in synchronization with both the rising edge and the falling edge.

The output of the pulse generation circuit 2 is branched, one branched output is input to the XOR circuit 4, and the other branched output is input to the delay circuit 4a.
In the delay circuit 4a, a delay time is set to T _1, the delay time T ₁ is set to 2 / f. Thus, the input pulse is output after being delayed by the delay time T _1.

  In the XOR circuit 5, an exclusive OR operation is performed on the pulse directly input from the pulse generation circuit 2 and the pulse delayed by the delay circuit 4a, so that two pulses are included in one cycle of the reference signal. The signal is synthesized and an injection signal is injected into the oscillator 6.

  In the injection-locked oscillator according to the first embodiment of the present invention, the number of pulses injected into the oscillator 6 by the pulse number multiplying circuit 3 is doubled, so that the frequency of the injection signal is apparently increased and effective. As a result, the number of multiplications is reduced. As a result, the lock range is increased as compared with the conventional injection-locked oscillator without the pulse number multiplication circuit 3, and the frequency range in which the phase noise reduction effect can be obtained is widened.

Embodiment 2. FIG.
FIG. 3 is a block diagram of an injection locked oscillator according to Embodiment 2 of the present invention.
The injection-locked oscillator according to the second embodiment of the present invention is different from the injection-locked oscillator according to the first embodiment of the present invention in the pulse multiplication circuit 3B. Is added and explanation is omitted.
Pulse number multiplication circuit 3B according to the second embodiment of the invention, the delay circuit of the delay time T ₁ is different from the delay time T ₂ of the delay circuits 4a to the pulse number multiplication circuit 3 according to the first embodiment of the present invention 4B is added, and an XOR circuit 5B that performs a 3-input exclusive OR operation instead of the 2-input XOR circuit 5 is provided.

The delay time T2 of the delay circuit 4b is set to S / (2 × f), and S is an integer greater than 1 and less than 2N, unlike M.
In the XOR circuit 5B, three pulses, the pulse directly input from the pulse generation circuit 2 and the pulse delayed by the delay circuits 4a and 4b, are input, and a three-input exclusive OR operation is performed. In a 3-input exclusive OR operation, a pulse is output when only one input pulse is input, and no pulse is output when two or three pulses are input simultaneously.
Then, an injection signal in which two pulses are included in one cycle of the reference signal is injected into the oscillator 6 from the XOR circuit 5B.

In the injection-locked oscillator according to the second embodiment of the present invention, the number of pulses injected into the oscillator 6 by the pulse number multiplying circuit 3B increases three times, so that the injection-locked oscillator according to the first embodiment of the present invention Apparently, the frequency of the injection signal is further increased, and the effective multiplication number is further decreased. As a result, the lock range is further increased and the frequency range in which the phase noise reduction effect can be obtained is further widened.
The injection locked oscillator according to the second embodiment of the present invention includes two delay circuits 4a and 4b having different delay times, but may include three or more delay circuits having different delay times.
Further, although the pulse generation circuit 2 directly inputs to the XOR circuit 5B, the same effect can be obtained even if all the branched paths are provided with delay circuits having different delay times.

Embodiment 3 FIG.
The injection locking oscillator according to the first embodiment of the present invention has the following problems. The delay time T ₁ of the delay circuit 4a is, the above-mentioned M / (2 × f) (where, M is an integer and less than 2N exceed 1) when shifted from the value of the injection signal to the oscillator 6, the output signal And complete synchronization including the phase. For this reason, there is a possibility that the output signal is modulated with the period of the reference signal and the spurious of the output signal becomes large, or in some cases, the synchronization itself becomes impossible. That is, it is necessary to set the delay time of the delay circuit to an appropriate value in advance according to the cycle of the output signal.

FIG. 4 is a block diagram of an injection locked oscillator according to Embodiment 3 of the present invention.
An injection locking oscillator according to Embodiment 3 of the present invention includes a pulse number multiplication circuit 3C in place of the injection locking oscillator and pulse number multiplication circuit 3 according to Embodiment 1 of the present invention, and further includes a control voltage generation circuit. 20 is different, and the others are the same, so the same reference numerals are attached to the same parts and the description is omitted.
A pulse number multiplication circuit 3C according to the third embodiment of the present invention includes a variable delay circuit 8a instead of the delay circuit 4a. Since the variable delay circuit 8a has a variable delay time according to the input control voltage, the variable delay circuit 8a delays the pulse generated and branched from the pulse generation circuit 2 by changing the delay time.

The control voltage generation circuit 20 receives one signal obtained by branching the output signal from the oscillator 6 and outputs two signals φ ₁ and φ ₂ having different timings by dividing the output signal by N by a multiplication factor N. phase comparison with the multiphase output frequency divider 9, and outputs a pulse theta ₁ and the phase difference [psi ₁ signals phi ₁ pulse theta ₁ and the signal phi ₁ is input is input to the pulse generating circuit 2 outputs to and vessels 10a, a phase comparator 10b for outputting a phase difference [psi ₂ pulses theta ₂ and the signal phi ₂ input together with pulse theta ₂ and the signal phi ₂ to the variable delay circuit 8a outputs is inputted, the phase comparator high-frequency component of the 10a and the phase difference [psi ₁ output from the phase comparator _10b, a differential amplifier circuit 11a for generating a control voltage for converging the difference delta ₁ of [psi ₂ to zero, the control voltage output from the differential amplifier circuit 11a To cut Comprises a pass filter (LPF) 12a, the.

In the following description of the control voltage generation circuit 20, a signal is output according to the timing chart of FIG. That is, the multiphase output frequency divider 9 divides the output signal of the oscillator 6 by 8 and outputs the first signal φ ₁ and the third signal φ ₂ . In the phase comparator 10a, a phase difference ψ ₁ between the signal φ ₁ and the pulse θ ₁ generated by the pulse generation circuit 2 is calculated. The phase comparator 10b calculates the phase difference ψ ₂ between the signal φ ₂ and the pulse θ ₂ output from the variable delay circuit 8a.
The differential amplifier circuit 11a, calculates the difference delta ₁ phase difference [psi ₂ which is output from the phase difference [psi ₁ and phase comparator 10b output from the phase comparator 10a, a control so that the difference delta ₁ converges to zero Output voltage.
The LPF 12a cuts off the high frequency component of the control voltage output from the differential amplifier circuit 11a and inputs it to the variable delay circuit 8a.

Next, the internal operation of the injection locked oscillator according to Embodiment 3 of the present invention will be described.
The multiphase output frequency divider 9 divides the output signal of the oscillator 6 by 8 and outputs two signals φ ₁ and φ ₂ of the _first and third timings. The multiphase output frequency divider 9, for generating an output signal in synchronization with the input signal, as the timing difference between the signals phi ₁ and phi _2, exactly matched to an integer multiple of the frequency divider input signal Can be generated.
The delay of the variable delay circuit 8a is adjusted so that negative feedback is applied with the _two signals φ ₁ and φ ₂ as a reference, and the delay difference ψ ₁ , ψ of the _two signals θ ₁ and θ ₂ input to the XOR circuit 5 ₂ converges to be equal to the timing difference between the _two signals φ ₁ and φ ₂ of the polyphase output frequency divider 9.

In other words, the time T ₁ shown on the timing chart of FIG. 2, to become an integral multiple of the output signal, the injection signal to the oscillator 6, a fully synchronous signal to the output signal of the oscillator 6. By doing so, an injection signal having an appropriate timing is automatically generated, injection locking can be easily achieved, and an injection locking oscillator with a small spurious output signal can be realized.

Embodiment 4 FIG.
FIG. 5 is a block diagram of an injection locked oscillator according to Embodiment 4 of the present invention.
The injection-locked oscillator according to the fourth embodiment of the present invention is different from the injection-locked oscillator according to the third embodiment of the present invention, the pulse number multiplying circuit 3D, and the control voltage generating circuit 20B, and the rest are the same. The same reference numerals are given to similar parts, and the description thereof is omitted.
In the pulse number multiplication circuit 3D according to the fourth embodiment of the present invention, another variable delay circuit 8a is added to the pulse number multiplication circuit 3C according to the third embodiment of the present invention, and a two-input XOR circuit 5 is provided. Instead of providing an XOR circuit 5B that performs a 3-input exclusive OR operation, the rest is the same, so the same reference numerals are given to the same parts and the description is omitted.

A control voltage generation circuit 20B according to Embodiment 4 of the present invention includes a phase comparator 10c, a differential amplifier circuit 11b, and an LPF 12b added to the control voltage generation circuit 20 according to Embodiment 4 of the present invention, and a multiphase output. Since the three signals φ ₁ , φ ₂ , and φ ₃ having different timings are output from the frequency divider 9 and the rest are the same, the same reference numerals are given to the same parts and the description thereof is omitted.

The polyphase output frequency divider 9 divides the output signal output from the oscillator 6 by N, and outputs three signals φ ₁ , φ ₂ , and φ ₃ having different timings.
The three phase comparators 10a, 10b, and 10c include three signals θ ₁ , θ ₂ , and θ ₃ input to the XOR circuit 5B and three signals φ ₁ output from the polyphase output frequency divider 9, respectively. , Φ ₂ , φ ₃ respectively, phase differences ψ ₁ , ψ ₂ , ψ ₃ are calculated.
The difference amplifying circuits 11a and 11b use the phase difference ψ ₁ output from the phase comparator 10a as a reference and the phase difference ψ ₂ output from the phase comparator 10b and the phase difference ψ ₃ output from the phase comparator 10c. difference delta ₁ and _to detect the delta _2, the difference delta _1, and generates a control voltage so that delta ₂ to each zero.
The LPFs 12a and 12b cut high frequency components of the control voltage output from the differential amplifier circuits 11a and 11b.

The injection-locked oscillator according to Embodiment 4 of the present invention includes a pulse number multiplication circuit 3D that triples the number of pulses, and the delay time of each pulse is automatically adjusted to an optimum value so that injection locking can be easily obtained. An injection-locked oscillator with a small spurious output signal can be realized.
It is possible to further increase the number of pulses and reduce the effective multiplication number N by changing the parallel number of the variable delay circuit, the phase comparator, the differential amplifier circuit, and the LPF.

Embodiment 5 FIG.
In the injection-locked oscillators according to the third and fourth embodiments described above, spurious output signals can be reduced, but it is difficult to completely eliminate spurious due to the characteristics of the injection-locked oscillator.
The injection locking oscillator according to the fifth embodiment of the present invention aims to solve this problem.

6 is a block diagram of an injection locked oscillator according to Embodiment 5 of the present invention.
The injection-locked oscillator according to the fifth embodiment of the present invention differs from the injection-locked oscillator according to the first embodiment of the present invention in that a phase-locked loop (PLL) 19 is added. Therefore, the same reference numerals are added to the same parts, and the description is omitted. Even if the phase locked loop 19 is added to the injection locked oscillator according to the second to fourth embodiments of the present invention, the same effect can be obtained.

  The phase synchronization circuit 19 converts the phase difference between the output signal output from the oscillator 6 and the output signal output from the phase synchronization circuit 19 into a voltage and outputs the voltage, and the phase frequency comparator 14 A charge pump 15 that amplifies the output voltage, a loop filter 16 that blocks signal fluctuations in the short cycle of the amplified voltage, a voltage controlled oscillator 17 that controls the frequency of the output signal according to the input voltage, and voltage control And a frequency divider 18 that outputs the frequency of the output signal output from the oscillator 17 with a frequency divided by one.

Here, if the frequency dividing number of the frequency divider 18 is 1, a signal having the same frequency as the output signal of the oscillator 6 is output from the voltage controlled oscillator 17.
Since the spectrum in the vicinity of the carrier of the output signal from the oscillator 6 is suppressed by the loop filter 16 of the phase locked loop 19, an output signal with small spurious can be obtained from the output terminal 7.
The frequency divider 18 can be selected to have an arbitrary value of 1 or more. However, from the viewpoint of phase noise, the influence of noise generated in the phase synchronization circuit 19 increases as the frequency divider increases. Therefore, it is preferable that the frequency dividing number is as small as possible.

Embodiment 6 FIG.
FIG. 7 is a block diagram of an injection locked oscillator according to Embodiment 6 of the present invention.
The injection locking oscillator according to the sixth embodiment of the present invention includes a phase locking circuit (PLL) 19 added to the injection locking oscillator according to the third embodiment of the present invention and a phase locking to the multiphase output frequency divider 9. Since the output signal output from the circuit 19 is different and the rest is the same, the same parts are denoted by the same reference numerals and the description thereof is omitted. Note that a phase lock circuit 19 is also added to the injection locked oscillator according to the fourth embodiment of the present invention, and an output signal output from the phase lock circuit 19 is input to the multiphase output frequency divider 9. Produces the same effect.

  In the injection locked oscillator according to the sixth embodiment of the present invention, since the phase lock circuit 19 for spurious suppression is arranged between the oscillator 6 and the output terminal 7, the phase lock circuit 19 simply suppresses spurious output signals. In addition, since the input signal of the polyphase output frequency divider 9 is also a signal with small fluctuations due to suppression of spurious, the accuracy of the timing difference between the output signals of the polyphase output frequency divider 9 is increased. The injection locking operation can be performed reliably.

  1 reference signal input terminal, 2 pulse generation circuit, 3 3B, 3C, 3D pulse number multiplication circuit, 4a, 4b delay circuit, 5, 5B XOR circuit, 6 oscillator 7 output terminal, 8a variable delay circuit, 9 polyphase Output frequency divider, 10a, 10b, 10c phase comparator, 11a, 11b differential amplifier circuit, 12a, 12b low pass filter (LPF), 14 phase frequency comparator, 15 charge pump, 16 loop filter, 17 voltage controlled oscillator, 18 Frequency divider, 19 Phase synchronization circuit, 20, 20B Control voltage generation circuit.

Claims (4)

In an injection-locked oscillator including an oscillator that oscillates a signal having a self-excited oscillation frequency in synchronization with an injection signal to be injected,
A reference signal having a frequency f / N that is 1 / N times the multiplication frequency f of substantially the same frequency f as the self-excited oscillation frequency is input and triggered by the reference signal to generate a pulse having a pulse width 1 / (2 × f). A pulse generation circuit that
A pulse number multiplication circuit that generates at least one pulse having a timing different from that of the pulse generated by the pulse generation circuit and outputs the generated pulse and the pulse generated by the pulse generation circuit together as an injection signal;
With
The pulse number multiplication circuit
Delay times M / (2 × f) are different from each other except for all or one of a plurality of branched pulses output from the pulse generation circuit, where M is an integer greater than 1 and less than 2N. At least one delay circuit that
An XOR circuit that synthesizes a pulse output from the delay circuit, or synthesizes a pulse output from the delay circuit and the one removed pulse;
An injection-locked oscillator comprising: The delay circuit is varied by a control voltage to which the delay time is input,
The pulse number multiplication circuit outputs a different signal of the same timing as the number of pulses input the output signal to the XOR circuit by dividing by the multiplication number by the frequency divider of the oscillator, to the XOR circuit injection locking oscillator according to claim 1, characterized in that it comprises a control voltage generator difference of the phase difference of the input is a pulse signal outputted from the frequency divider to generate the control voltage becomes zero.   3. The injection locked oscillator according to claim 1, further comprising a phase locked loop arranged at a subsequent stage of the oscillator. A phase synchronization circuit disposed at a subsequent stage of the oscillator,
The delay circuit is varied by a control voltage to which the delay time is input,
The pulse number multiplication circuit outputs the phase synchronization circuit different signals by the output signal frequency divider of the same timing as the number of pulses input to the XOR circuit by dividing by the multiplication number of the XOR injection locking according to claim 1, characterized in that it comprises a control voltage generator circuit for generating the control voltage difference of the phase difference signal outputted from the pulse and the frequency divider to be input to the circuit is zero Oscillator.

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