JP4577761B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine including a random number generation unit, and more particularly to a gaming machine including a random number generation unit that generates a random number for symbol lottery or the like by hardware configured by a random number clock generation circuit or the like when playing a game. .

In a gaming machine equipped with such a random number generator, a predetermined number of digits are generated by a clock count circuit based on a clock generated at a predetermined cycle by a random number clock generator circuit composed of an oscillator such as a crystal resonator or an oscillator. The CPU that controls the game periodically extracts the count value stored in the count value storage circuit and reads it, and stops the read count value in the symbol display device on the game board. It is used as a random number for symbol drawing, etc. for determining symbols. By using a random number generator that counts random values by hardware as described above, the software load is reduced as compared with the case where software controlled by the CPU executes a program and counts random values. Random numbers can be generated and updated at high speed according to the clock generation cycle of the clock generation circuit. The above is also described in Patent Document 1 and Patent Document 2, for example.
JP 2003-190483 A JP 7-124296 A

  However, in a gaming machine using a random number generator that counts random values by hardware as described above, a random number clock generator (oscillator) that constitutes the random number generator, or a clock count that also constitutes the random number generator. When some abnormal operation occurs in the circuit, the random number value may not be counted periodically and may be stopped. In such a state, the CPU repeatedly reads the same count value stored in the count value storage circuit. And even if it falls into such a state, since a game machine continues operation | movement without alert | reporting abnormal operation | movement, it was hard to notice abnormal operation | movement of a random number generation part. At this time, if the random number for lottery which is disadvantageous to the game hall is repeatedly read by the player continuing the game as it is, the game hall side is damaged. In addition, when a failure occurs in the random number generator, it is difficult to determine whether this is due to abnormal operation in the random number clock generation circuit (oscillator) or abnormal operation in the clock count circuit. It was.

  In view of the problems as described above, in the present invention, it is possible to detect abnormal operation in a random number clock generation circuit and a clock count circuit that constitute a random number generation unit, determine an abnormal part, and notify this early. An object is to provide a gaming machine.

In order to solve the above-described problems, a gaming machine according to the present invention uses a random number clock generation unit (for example, a random number clock generation circuit B51 in the embodiment) that generates a clock at a predetermined frequency and a clock generated by the random number clock generation unit. Based on random number counting means (for example, the first clock count circuit B81, the second clock count circuit B82, the third clock count circuit B83, and the fourth clock count circuit B84 in the embodiment) that counts the random number value based on the random number value Random number extraction means for extracting one count value from the counted random number values (for example, the CPU 732 and the symbol lottery means B35 in the embodiment) and whether or not the count value extracted by the random number extraction means is a hit random number is determined. Random number determination means (for example, hit determination in the embodiment) Stage B37 and), based on the determination result of the random number determination unit is configured to have a symbol display device for displaying a predetermined symbol in the game surface plate, the normal input signal from the random number clock generating means of the random number clock generating means Pulse oscillation detection means (for example, clock monitoring circuit B95 in the embodiment) for detecting whether or not the pulse signal is output at a predetermined cycle by a simple operation, and an input signal from the random number clock generation means by the pulse oscillation detection signal when There is detected that not the pulse signal according to the normal operation of the random number clock generating means, the abnormality signal output means for outputting an abnormal signal indicating the occurrence of the abnormal operation of the random number clock generating means (for example, input in the embodiment circuit and parts B40), the count of the random number output from the random number counting means every time a round by the operation of the random number counting means Based on the count signal and outputs a monitor signal monitoring signal output means (e.g., the overflow signal output circuit B97 in the embodiment) and, from the abnormal signal output means based on whether the abnormality signal is output random clock generator And monitoring whether the monitoring signal is output from the monitoring signal output means at a predetermined cycle longer than a round of the random number count. When the signal is detected, it is determined that the random number counting unit is operating normally, and the monitoring signal is reset. When the monitoring signal is not detected, the signal monitoring unit determines that the random number counting unit is operating abnormally ( For example, the control unit 740) in the embodiment and the signal monitoring unit determine that the random number clock generating unit is operating abnormally. A first notification unit (for example, the first error display unit 61a in the embodiment) that performs a predetermined notification indicating the occurrence of an abnormal operation of the random number clock generation unit when disconnected, and the random number count unit is abnormal by the signal monitoring unit Notification means (for example, a second notification section (for example, the second error display section 61b in the embodiment)) that performs a predetermined notification indicating the occurrence of an abnormal operation of the random number counting means when it is determined that the operation has occurred . Error display device 61 and speaker 45) in the embodiment, and when the random number clock generating means or the random number counting means determines that an abnormal operation is occurring by the signal monitoring means , the random number determining means If the count value is determined to be the random number per stops the game operation performs more predetermined notification to the notification means, a random number If it is determined not to be a random number per count value by the constant unit configured to continue the game operation carried out only more predetermined notification to the notifying means.

In the gaming machine configured as described above, the pulse oscillation detection means smoothes the pulse signal generated by the normal operation of the random number clock generation means and always outputs a predetermined voltage or higher, and the voltage from the smoothing circuit section. It is preferable that the power source connected to the pulse oscillation detection means and the abnormal signal output means and a transistor for cutting off or conducting the pulse oscillation detection means by an on / off operation according to the load.

Further, in the gaming machine configured as described above, when the input signal from the random number clock generating means is a pulse signal due to the normal operation of the random number clock generating means, the transistor is turned on by the load of voltage from the smoothing circuit section and the power supply When the input signal from the random number clock generating means is not a pulse signal due to the normal operation of the random number clock generating means, the power source and the pulse oscillation detecting means are current from the power supply by being cut off is preferably configured as abnormality signal from the abnormality signal output means flows to the side of the abnormal signal outputting means is output.

Further, in the gaming machine having the above configuration, the monitoring signal is configured to switch from the low signal to the high signal based on the output of the count signal by the normal operation of the random number counting unit, and the signal monitoring unit counts the random number value. Monitors whether the monitoring signal switches from a low signal to a high signal every predetermined period longer than one cycle, and determines that the random number counting means is operating normally when a high signal is detected. Te resets the monitor signal low signal may be configured to determine that the random number counting means has caused an abnormal operation when the monitoring signal that is detected remains low signal. Further, at this time, it is preferable that the notification unit is configured to perform a predetermined notification in the second notification unit when the signal monitoring unit detects that the monitoring signal remains a low signal.

On the other hand, in the gaming machine configured as described above, the monitoring signal is configured to switch from the high signal to the low signal based on the output of the count signal due to the normal operation of the random number counting means, and the signal monitoring means counts the random number value. Monitors whether the monitoring signal has switched from a high signal to a low signal every predetermined period longer than one cycle, and determines that the random number counting means is operating normally when a low signal is detected. Te resets the monitoring signal to a high signal, may be configured to determine that the random number counting means has caused an abnormal operation when the monitoring signal is detected to remain high signal. Further, at this time, it is preferable that the notification unit is configured to perform a predetermined notification in the second notification unit when the signal monitoring unit detects that the monitoring signal remains a high signal.

According to the gaming machine according to the present invention, during the operation of the random number generation unit mounted on the gaming machine, the signal monitoring unit performs an abnormal signal indicating the occurrence of the abnormal operation of the random number clock generating unit and the abnormal operation of the random number counting unit. It is monitored whether or not a monitoring signal for detecting occurrence is output. Then, by detecting each signal and notifying that, it is possible to discriminate between the occurrence of an abnormal operation in the random number clock generating means and the occurrence of an abnormal operation in the random number counting means. Since the location where the abnormal operation occurs can be specified in this way, the parts replacement work at the location where the abnormality occurs and the inspection work (analysis work) at the location where the abnormality occurs can be performed quickly.

  In addition, when an abnormal operation is detected in the random number clock generating means or the random number counting means, if a random number for winning (a winning random number) that is disadvantageous for the game hall is repeatedly read by the random number extracting means, the operation of the gaming machine immediately Is configured to stop. For this reason, when an abnormal operation occurs in the random number clock generating means or the random number counting means, a game that is disadvantageous to the game hall side without being noticed is not continued, and damage is caused on the game hall side. Can be prevented.

  Hereinafter, a preferred embodiment of a gaming machine according to the present invention will be described in detail with reference to the accompanying drawings. 1 is an external front view of a pachinko machine described as an example of the above-mentioned ball game machine, FIG. 2 is a rear view seen from the back side of the pachinko machine, and FIG. 3 is a control system provided in the pachinko machine. FIG. 4 is a block diagram showing an outline, FIG. 4 is a block diagram showing a part relating to control of the pachinko machine provided in the pachinko machine and a part relating to generation of random numbers, and FIG. 5 is a random number generation part in the pachinko machine and its part FIG. 6 is an enlarged view of a clock monitoring circuit in the random number generator, and FIGS. 7 and 8 are timing charts showing signals generated in the random number generator. FIG. 9 is a diagram showing a main routine in a procedure for acquiring and using a random number for symbol lottery in a pachinko machine. FIGS. 10 and 11 are normal game processes in a procedure for acquiring and using a random number for symbol lottery in a pachinko machine. FIG. 12 and FIG. 13 are diagrams showing a part of a subroutine, and FIG. 12 and FIG. 13 are diagrams showing a part of a random number monitoring processing subroutine in a procedure for obtaining and using a random number for symbol lottery in the pachinko machine PM. FIG. 15 is a diagram showing a symbol variation processing subroutine in a procedure for acquiring and using a random number for symbol lottery in a pachinko machine.

  Here, first, a schematic configuration of a pachinko machine PM described as an example of the above-described ball game machine will be described with reference to FIG. 1 and FIG. This pachinko machine PM has a rectangular frame size and a front frame 2 that is configured to have a rectangular frame size corresponding to the front of the opening of the outer frame 1 that forms a vertical fixed holding frame. The hinge members 3a and 3b arranged on the left and upper sides are attached so as to be able to be opened and closed laterally and detachable, and normally in a closed state engaged with the outer frame 1 using a locking device 4 provided on the right side of the front. Retained.

  On the front side of the front frame 2, there is a glass door 5 that can be seen through the game board 20 through a transparent plate material such as a polycarbonate plate or a glass plate that has a rectangular shape matched to the front area of the front frame 2 and is attached to the center. Further, an upper ball tray 6 is arranged at the lower part of the glass door 5 to guide the game balls one by one to the hitting ball launching device 9 provided on the back surface of the front frame 2 by a hinge mechanism built in the left edge. 2 can be opened / closed and attached / detached sideways. The glass door 5 and the upper ball tray 6 are normally held in a closed state that covers the front surface of the front frame 2 using the locking device 4 and a lock mechanism (not shown). Further, a lower ball tray 7 is provided at the lower part of the front frame 2, and an operation handle 8 for performing a game ball launching operation is attached along with the lower ball tray 7.

  The game board 20 is configured by using a decorative board (also referred to as a veneer) 21 having a predetermined design cell attached to a surface of a laminated plywood having a thickness of about 19 mm cut into a predetermined shape as shown in the figure. . On the front side of the decorative plate 21, a belt-like outer rail 23a and an inner rail 23b are fixed in an arc shape, and a game area PA is defined on the inner side surrounded by the guide rails 23a and 23b. In the game area PA, there are a first start winning tool 24a, a second start winning tool 24b, a general winning tool 25, a winning tool such as an attacker 26 having a big winning opening, and a predetermined pattern according to the progress of the game. A symbol display device 28 or the like to be displayed is attached, and at the lower end of the game area PA, there is an out port 27 for discharging the game balls that have fallen without winning the prize-winning devices 24a, 24b, 25, 26 to the back side of the game board 20. Is provided. Further, four special symbol holding lamps 90, 90, 90, 90 are provided above the symbol display device 28.

  The symbol display device 28 is located almost at the center of the game board 20 and displays a “special symbol” consisting of a combination of three-digit symbols on a liquid crystal screen. Of these special symbols, three digits are displayed. In any case, a combination of the same type of pattern is referred to as a “big hit symbol”.

  When there is a prize for the first starting prize 24a or the second starting prize 24b, a prize is provided on the upper left side of the abutting plate 6a that forms a horizontal rectangle in the upper ball tray 6 and can be opened and closed with respect to the front frame 2. In addition to the five prize balls being paid out to the player from the ball payout exit 44, the symbol display device 28 is activated and the variation of the symbol is started. As a result of this change, when the special symbol to be stopped and displayed is a jackpot symbol, a “jackpot game” advantageous to the player is generated. When the hit ball wins the first start winning tool 24a or the second start winning tool 24b during the variable display on the symbol display device 28, the special symbol holding lamps 90, 90, 90, 90 are a maximum of four. It is supposed to light up to pieces. That is, the subsequent operation of the symbol display device 28 is guaranteed by the number of times corresponding to the number of the special symbol holding lamps 90, 90, 90, 90 being lit.

  In the first start winning tool 24a, a hitting ball flow path for detecting the hit of the first starting winning tool 24a is detected and a detection signal is output to start the symbol display on the symbol display device 28. A first start winning sensor 51 is provided. The first start winning sensor 51 uses a magnetic sensor and outputs a first start signal that takes two states of a high signal and a low signal as a detection signal. The first start signal is output as a high signal when a hit ball is not detected, and is output as a low signal only while a hit ball is detected. An optical or mechanical sensor may be used as the first start winning sensor 51.

  In the second starting winning tool 24b, a ball hitting path to the second starting winning tool 24b is detected by the same magnetic sensor as the first starting winning sensor 51, and a detection signal is outputted to the flow path of the hit ball. A second start winning sensor 52 for starting the variable display of the symbol 28 is provided. The second start winning sensor 52 outputs a second start signal that takes two states of a high signal and a low signal as a detection signal. The second start signal outputs a high signal when no hit ball is detected, but outputs a low signal only while the hit ball is passing. An optical or mechanical sensor may be used as the second start winning sensor 52.

As shown in FIG. 2, the lower part of the rear surface of the front frame 2 has a hitting ball launching device 9 that launches a game ball toward the outer rail 23 a, and an operation of the hitting ball launching device 9 in response to the turning operation of the operation handle 8. A launcher control board 200 to be controlled is attached. Further, behind the upper ball tray 6 is formed an auxiliary mechanism portion called a game assisting board whose front side is normally covered with the upper ball tray 6 that is normally held closed, and a ball hitting device on the front side. Foul ball collection that discharges the game ball launched by 9 toward the outer rail 23a and the foul ball returned to the ball launcher 9 side without reaching the game area PA to the lower ball tray 7 A route member, a speaker for generating sound effects according to the game development status, and the like are attached.

  A back set board 30 is attached to the back of the front frame 2. This back set board 30 has a rectangular shape somewhat smaller than the inner size of the outer frame 1, and is configured based on a base frame body 31 integrally formed with a window 31w penetrating the front and back at the center. . Back set board swinging hinge members 32 and 33 are fixed to the side edge of the base frame body 31 at a predetermined interval in the vertical direction. The upper and lower back set panel swinging hinge members 32 and 33 are fixed to the front frame 2. The back set board 30 is mounted on the back side of the front frame 2 so that it can be opened and closed laterally and detachable by engaging with the upper and lower fixed hinge members 12 and 13 and swinging or disengaging. The closing lever 34 is used to close and hold the back of the front frame 2.

  The back set board 30 is provided with a prize ball path for paying out prize balls so as to surround the window 31w. That is, on the back side of the base frame 31, a tank member 35 for storing and supplying game balls, an alignment rod member 36 for aligning and flowing down game balls supplied from the tank member 35, and an alignment rod member 36 are supplied. A prize ball standby passage 37 for receiving and waiting for a predetermined number of game balls, a ball payout device 38 for paying out the game balls waiting in the prize ball standby passage 37 based on predetermined winning conditions, etc. A prize ball path such as a prize ball payout path 39 for guiding the game balls paid out from the payout device 38 to the upper and lower ball trays 6 and 7 is provided. In addition, on the front side of the base frame 31, an out ball and a safe ball that are positioned below the window 31 w and discharged to the back side of the game board 20, and a punch that is discharged from the middle of the winning ball path by the ball punching mechanism. A collecting path (not shown) for collecting balls and the like is formed, and a ball discharging path (not shown) is formed on the back surface side of the base frame 31 to discharge the game balls gathered connected to the collecting path to a collection bucket on the gaming facility side. ing.

  In each part of the back surface of the back set board 30, a main board 700 that comprehensively controls the operation of the pachinko machine PM, a ball payout board 300 that controls the operation of the ball payout device 38 based on a command signal from the main board 700, A circuit board such as a lamp / sound control board 400 that controls the operation of effect lighting and sound effects, and a power supply board 500 that supplies power to these control boards and various electronic devices is detachably attached. An electronic device is connected by a wire harness (not shown) to constitute a pachinko machine PM. Also, below the ball payout board 300, an error display device 61 (error LED) is provided for notifying the occurrence of any abnormal operation or the like on these circuit boards including the main board 700. The error display device 61 includes a first error display unit 61a and a second error display unit 61b, and both display an error on a screen using a light emitting diode.

  The pachinko machine PM is used in a game with the glass door 5, the upper ball tray 6, the back set board 30 and the like closed, and the front frame 2 closed and locked to the outer frame 1. The game is started by storing the game balls in the upper ball tray 6 and rotating the operation handle 8, and the game balls stored in the upper ball tray 6 are sent one by one to the hitting ball launcher 9 and are operated. The pachinko game is developed by being struck into the game area PA with the strength corresponding to the rotation operation angle.

  Next, an outline of a control system for controlling the pachinko machine PM will be described. As shown in FIG. 3, the present control system includes a main board 700, a first start prize sensor 51, a second start prize sensor 52, a symbol display device 28, a first error display section 61a, and a second error display section 62b. And an error display device 61, a speaker 45, and the like, which are electrically connected by a cable or the like.

  The main board 700 includes a system program that manages the entire operation of the pachinko machine PM, a storage unit that is pre-stored with a game execution program, and a microprocessor that executes these programs (hereinafter, “ A main control unit 730 having a CPU ”and a random number generation unit 750 for generating random numbers for symbol drawing (65536 random values from 0 to 65535) irrespective of the control of the main board 700. Yes. In the present invention, the random number is not only a value that is randomly generated in a mathematical sense, but even if the generation is regular, the acquisition timing is random, so that the random number is substantially a random number. It also means a functional value. In the present invention, the random value counted by the clock count circuits B81 to B84, which will be described later, and stored in the first and second count value storage circuits B91 and B92 will be specifically referred to as “count value”.

  The control unit 740 in the main control unit 730 is provided with a ROM 733 and a RAM 734 in addition to the CPU 732 described above, and a control program to be executed by the CPU 732 and data necessary for the control process are described in the ROM 733. The main control unit 730 is provided with a reference clock generation circuit 731. The reference clock generation circuit 731 is a circuit that generates a reference clock that is an operation reference of the CPU 732 that plays a central role in the control of the pachinko machine PM. ). In addition, the reference clock may be obtained by appropriately dividing the pulse by the frequency divider 735.

  The CPU 732 has a symbol lottery means B35 and a hit determination means B37. When the main board 700 detects a low signal from the first start prize sensor 51 or the second start prize sensor 52, the symbol lottery means B35 detects one of 65536 random numbers sequentially generated from the random number generator 750. By obtaining the count value, the stop symbol in the symbol display device 28 is determined.

  In the symbol data table B36 on the ROM 733, symbol data for determining a stop symbol in the symbol display device 28 is recorded. Each symbol data is given an address number, and one symbol data is specified from one address number. As described above, when a low signal from the first start winning sensor 51 or the second start winning sensor 52 is detected, the symbol lottery count value drawn by the random number generator 750 and the symbol data table are selected. A stop symbol is selected by collation with symbol data in B36. Then, a predetermined symbol selected based on the control signal from the main board 700 is displayed on the symbol display device 28.

  In the hit determination table B38 on the ROM 733, data is recorded so that a unique determination result of “Random number” or “Lose random number” for one random number value is determined for the entire range of random values. ing. That is, the 65536 random number values always belong to either the winning random number or the lost random number, and do not belong to both or neither. Here, the winning random number means a random value such that a predetermined symbol combination that generates a jackpot game is stopped and displayed on the symbol display device 28. The hit determination means B37 in the CPU 732 compares the count value extracted by the symbol lottery means B35 with the determination table B38, and determines whether or not the determination result corresponding to the count value, that is, the count value is a hit random number. , Or whether it is a lost random number.

  Further, the error display device 61 and the speaker 45 are connected to the main board 700 via wiring cables, respectively, and by a control signal supplied from the control unit 740 that detects an abnormality in each circuit board such as the main board 700, The first error display unit 61a or the second error display unit 61b in the error display device 61 can be turned on and the sound of the speaker 45 can be emitted.

  Here, with reference to FIG. 4 and FIG. 5, the structure of the part which concerns on generation | occurrence | production of the random number in the pachinko machine PM, and this extraction is demonstrated. The input circuit unit B40 is a part to which input information from outside the main substrate 700, a random number generated by a random number generation unit 750 provided in the main substrate 700, and an abnormal signal from a clock monitoring circuit B95 described later are input. For example. Specifically, the input circuit unit B40 receives from the first start winning sensor 51 or the second start winning sensor 52 that is output in accordance with the winning of the hit ball to the first start winning tool 24a or the second start winning tool 24b. And the upper and lower 8 bits of the random number generated by the random number generator 750 are input. Further, an output signal from a random number clock generation means B51, which will be described later, is input to the input circuit section B40, and whether or not this output signal is a pulse signal due to the normal operation of the random number clock generation means B51 is determined. Is monitored by the control unit 740.

  The output circuit unit B45 receives a read signal for reading a signal such as a control signal to an electrical component (lamp, speaker, etc.) outside the main board 700 and a random number generated by the random number generator 750 provided in the main board 700. The output part is composed of an IC such as a buffer. Specifically, from the output circuit unit B45, when the main board 700 determines that the first starting prize-winning tool 24a has won a prize, the first read signal that triggers reading of the count value corresponding to the prize, When the main board 700 determines that the second starting prize-winning tool 24b has won a prize, a second read signal that triggers reading of the count value corresponding to the prize is output. Further, when an abnormal operation is detected in the random number clock generation means B51 or the clock count circuits B81 to B84, a control signal is output to the error display device 61 to display a predetermined error.

  The first start signal from the first start winning sensor 51 is input to the 1A terminal of the IC 14 of the input circuit unit B40. On the other hand, the second start signal from the second start winning sensor 52 is input to the 2A terminal of the IC 14 of the input circuit unit B40. Further, the 3A terminal of the IC 14 is connected to the collector of the transistor TR1 constituting the clock monitoring circuit B95, and when a voltage is applied to the base of the transistor TR1, a collector current flows from the input circuit part B40 side. Yes.

  The random number generator 750 generates a count value used as a random number. Specifically, the random number generator 750 includes a random number clock generation circuit B51, a random number clock inversion circuit B61, first and second latch signal output circuits B71, B72, The first to fourth clock count circuits B81, B82, B83, and B84, first and second count value storage circuits B91 and B92, a clock monitoring circuit B95, and an overflow signal output circuit B97 are configured.

  The random number clock generation circuit B51 (OSC1) is for generating a clock for counting random numbers and includes a clock output unit (OUT) for outputting the generated clock. The random number clock generation circuit B51 is constituted by, for example, a crystal oscillator that generates a 7.15909 MHz clock.

  The random number clock inversion circuit B61 (IC18) inverts the clock output from the random number clock generation circuit B51, and uses the inverted clock as an inverted clock, which will be described later, a first latch signal output circuit B71 (IC16) and a second latch signal output circuit. The data is output to B72 (IC17). Specifically, in the IC 18, a signal obtained by inverting the signal output from the 1Q terminal is output as an inverted signal from the 1Q inverting terminal that is the inverted clock output unit, and the rising edge of the clock is the falling edge of the inverted clock. The falling edge of the clock corresponds to the rising edge of the inverted clock. The random number clock inverting circuit B61 may be configured using an IC such as a NOT gate.

  The first to fourth clock count circuits B81, B82, B83, and B84 each have a random number clock input unit (CK) that inputs a clock and a count output unit (QA to QD) that outputs the counted value. ing. As shown in FIG. 5, the first to fourth clock count circuits B81, B82, B83, and B84 are constituted by a circuit in which four 4-bit increment counters (from IC1 to IC4) are cascade-connected to generate a random number clock. This is a circuit for adding at the rising edge of the clock generated by the circuit B51 and outputting the addition result.

  In response to the input of the clock from the random number clock generation circuit B51, first, the first clock count circuit B81 (IC1) counts a value for four digits (for example, “0001” and “0011”). When "1111" is counted and the count of four digits ends, a carry signal is output from the CO terminal of IC1 to the ENT terminal of the second clock count circuit B82 (IC2) each time. In order for the second clock count circuit B82 to start counting, it is necessary to input the carry signal from the first clock count circuit B81. That is, in the IC2, the next four digits are started only after the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B51 are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC2, a carry signal is sent from the CO terminal of IC2 to the third clock count circuit B83 each time. It is output to the ENT terminal of (IC3). In order for the third clock count circuit B83 to start counting, it is necessary to input the carry signal from the second clock count circuit B82. That is, in IC3, the count of the value for the next four digits is started only when the carry signal and the clock from the random number clock generation circuit B51 (input to the CK terminal) are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC3, the carry signal is counted from the CO terminal of IC3 to the fourth clock each time. It is output to the ENT terminal of the circuit B84 (IC4). In order for the fourth clock count circuit B84 to start counting, it is necessary to input the carry signal from the third clock count circuit B83. That is, in the IC4, the count of the next four digits is started only when the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B51 are input simultaneously.

  As described above, 16-bit binary numbers are generated by the clock count circuits B81 to B84. That is, among the 16-digit binary numbers, the first clock count circuit B81 (IC1) is the lowest four digits, the second clock count circuit B82 (IC2) is the upper four digits, and the third clock count circuit B83 (IC3 ) Is further responsible for the upper 4 digits and the fourth clock count circuit B84 (IC4).

  The counts added by the four clock count circuits B81 to B84 are sent to the first count value storage circuit B91 and the second count value storage circuit B92 via the respective count output sections (QA, QB, QC and QD terminals). Each is output and stored. In this embodiment, an addition type increment counter is used as the clock count circuit. However, in other embodiments, a subtraction type decrement counter may be used. In this embodiment, a 16-bit random number (4 bits × 4) is generated. However, in other embodiments, the number of bits is not limited to 16 bits and may be changed as appropriate. .

  The latch signal output circuits B71 and B72 include a first latch signal output circuit B71 (IC16) related to acquisition of a random number associated with winning in the first start winning tool 24a and a random number associated with winning in the second starting winning tool 24b. The second latch signal output circuit B72 (IC17) related to acquisition is divided.

  The inverted clock from the random number clock inverter circuit B61 (IC18) is input to the first latch signal output circuit B71 (IC16) via the first inverted clock input section (1CK). At the same time, the first start signal from the first start winning sensor 51 is input to the first start signal input unit (1D) via the buffer (IC13). When the first start signal (low signal) is input via the first start signal input section (1D), the first latch signal output circuit B71 uses the rising edge of this signal as the first inverted clock input. The first count value storage circuit B91 (IC5 and IC6) passes through the first latch signal output unit (1Q) as the first latch signal after being delayed in synchronization with the rising edge of the inverted clock input from the unit (1CK). Output to.

  On the other hand, the second latch signal output circuit B72 (IC17) receives the inverted clock from the random number clock inverter circuit B61 via the second inverted clock input section (2CK). At the same time, the second start signal from the second start winning sensor 52 is input to the second start signal input unit (2D). When the second start signal (low signal) is input through the second start signal input unit (2D), the second latch signal output circuit B72 sends the rising edge of this signal from the inverted clock input unit. After being delayed so as to be synchronized with the rising edge of the input inverted clock, the second latch signal is output to the second count value storage circuit B92 (IC7 and IC8) via the second latch signal output unit (2Q).

  The first and second start signals are also input to the main control unit 730 via the input circuit unit B40 and the like, as will be described later, and may be used as a timing for starting a program executed for random number acquisition. It is supposed to be used.

  The count value storage circuits B91 and B92 are a first count value storage circuit B91 for temporarily storing a random number derived from winning in the first start winning tool 24a, and a random number derived from winning in the second starting winning tool 24b. Is divided into a second count value storage circuit B92 for temporarily storing.

  The first count value storage circuit B91 uses the count value counted by the clock count circuits B81 to B84 based on the first latch signal from the first latch signal output circuit B71 (the first count from the first start winning sensor 51). When a start signal is received and a latch signal is output from the first latch signal output circuit B71, it is stored. On the other hand, the second count value storage circuit B92 calculates the count value counted by the clock count circuits B81 to B84 based on the second latch signal from the second latch signal output circuit B72 (from the second start winning sensor 52). The second start signal is received and stored (when a latch signal is output from the second latch signal output circuit B72).

  As shown in FIG. 5, the first count value storage circuit B91 includes a register unit (IC5 and IC6) including two 8-bit ICs and a buffer unit (IC9 and IC10) including two 8-bit ICs. The Similarly, the second count value storage circuit B92 includes a register unit (IC7 and IC8) including two 8-bit ICs and a buffer unit (IC11 and IC12) including two 8-bit ICs.

  Of the register portion of the first count value storage circuit B91, the IC5 receives the 4-digit count value from the first clock count circuit B81 (IC1) through the D1 terminal to the D4 terminal, The 4-digit count value from the clock count circuit B82 (IC2) is input via the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC5 function as a count input unit, and the lower 8 digits of the 16-bit binary count value derived from the first start prize 24a are input to the IC5 through them. .

  Of the register section of the first count value storage circuit B91, the IC6 receives the 4-digit count value from the third clock count circuit B83 (IC3) via the D1 terminal to the D4 terminal, A 4-digit count value from the clock count circuit B84 (IC4) is input from the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC 6 function as a count input unit, and the upper 8 digits of the 16-bit binary count value derived from the first start prize 24a are input to the IC 6 through these. .

  Of the register unit of the second count value storage circuit B92, the IC7 receives the 4-digit count value from the first clock count circuit B81 (IC1) through the D1 terminal to the D4 terminal, The 4-digit count value from the clock count circuit B82 (IC2) is input via the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC 7 function as a count input unit, and the lower 8 digits of the 16-bit binary count value derived from the second start prize 24b are input to the IC 7 through these terminals. .

  Of the register unit of the second count value storage circuit B92, the IC8 receives the 4-digit count value from the third clock count circuit B83 (IC3) through the D1 terminal to the D4 terminal, A 4-digit count value from the clock count circuit B84 (IC4) is input from the D5 terminal to the D8 terminal. That is, the D8 terminal to D8 terminal of the IC8 function as a count input unit, and the IC8 receives the upper 8 digits of the 16-bit binary count value derived from the second start prize 24b through them. The

  The first latch signal from the first latch signal output circuit B71 is input to the CLOCK terminal in the register unit (IC5 and IC6) of the first count value storage circuit B91. That is, these CLOCK terminals function as a first latch signal input unit. The count value input from the clock count circuits B81 to B84 at the time of the rising edge when the first latch signal input from the first latch signal input unit becomes a high signal is stored in the register unit. .

  The second latch signal from the second latch signal output circuit B72 is input to the CLOCK terminal in the register unit (IC7 and IC8) of the second count value storage circuit B92. That is, these CLOCK terminals function as a second latch signal input unit. The count value input from the clock count circuits B81 to B84 at the time of the rising edge when the second latch signal input from the second latch signal input unit becomes a high signal is stored in the register unit. .

  The G1 terminal in the buffer unit (IC9 and IC10) of the first count value storage circuit B91 corresponds to a read signal output from the output circuit unit B45 of the main control unit 730 based on a program executed for random number acquisition. Thus, one count value consisting of 16 digits stored in the first count value storage circuit B91 is output to the CPU 732. That is, at the time of the falling edge when the read signal input from the read signal input unit becomes a low signal, the random numbers stored in the register units (IC5 and IC6) are transferred to the CPU via the Y1 terminal to Y8 terminal, respectively. Output to the data bus.

  Of the random numbers output from the first count value storage circuit B91, those passing through the IC 9 are input to the CPU 732 and handled as the lower 8 digits of the 16-digit random numbers. On the other hand, among the random numbers output from the first count value storage circuit B91, those passing through the IC 10 are input to the CPU 732 and handled as the upper 8 digits of the 16-digit random numbers.

  The terminal G1 in the buffer unit (IC11 and IC12) of the second count value storage circuit B92 stores a second count value according to the read signal output from the output circuit unit B45 of the main control unit 730 based on the program. One count value consisting of 16 digits stored in the circuit B 92 is output to the CPU 732. That is, at the time of the falling edge when the read signal input from the read signal input unit becomes a low signal, the random numbers stored in the register units (IC7 and IC8) are transferred to the CPU data via the Y1 terminal to Y8 terminal, respectively. Output to the bus.

  Among the random numbers output from the second count value storage circuit B92, those passing through the IC 11 are input to the CPU 732 and handled as the lower 8 digits of the 16-digit random numbers. On the other hand, among the random numbers output from the second count value storage circuit B92, those passing through the IC 12 are input to the CPU 732 and handled as the upper 8 digits of the 16-digit random numbers.

  Further, in the fourth clock count circuit B84 (IC4), every time the random number value for 16 bits is counted (every bit value becomes “1”), the count from the fourth clock count circuit B84 is counted. A signal (for example, a high signal) is output from the CO terminal of IC4 toward the 1CK terminal of overflow signal output circuit B97. The count signal is stopped when the first clock count circuit B81 starts counting the random number value again (that is, switched to a low signal).

  On the other hand, when any trouble occurs in the first to fourth clock count circuits B81 to B84, the random number value is not normally counted up in any of the first to fourth clock count circuits B81 to B84. The count signal output from the CO terminal of IC4 to the 1CK terminal of overflow signal output circuit B97 remains a low signal.

  The overflow signal output circuit B97 is configured such that the first to fourth clock count circuits B81 to B84 operate normally, and the CO of the fourth clock count circuit B84 is output every predetermined period when the 16-bit random number count ends. When a count signal as a high signal output from the terminal is input, an overflow signal (second abnormal signal) as a high signal is output from the 1Q terminal to the CPU 732. In contrast, when the abnormal operation occurs in any of the first to fourth clock count circuits B81 to B84, the count signal output from the CO terminal of the fourth clock count circuit B84 remains a low signal. The overflow signal output circuit B97 outputs an overflow signal as a low signal from the 1Q terminal to the CPU 732.

  When the CPU 732 detects that the overflow signal is a high signal in the random number monitoring process described later, the CPU 732 determines that all of the first to fourth clock count circuits B81 to B84 are operating normally. Then, a control signal is output to the overflow signal output circuit B97, and the overflow signal output from the overflow signal output circuit B97 is reset to a low signal.

  On the other hand, when the CPU 732 detects that the overflow signal output from the overflow signal output circuit B97 remains a low signal in the random number monitoring process to be described later, the CPU 732 executes the operations of the first to fourth clock count circuits B81 to B84. It is determined that one of them is malfunctioning.

  As described above, the random number clock generation circuit B51 generates a random number clock of about 7 MHz. Then, the clock count circuits B81 to B84 count 65536 random numbers of 16 bits and output the count signal to the overflow signal output circuit B97, and the cycle in which the overflow signal is output from the overflow signal output circuit B97 to the CPU 732 is 10 ms or less. (This is roughly estimated as follows. That is, the random number clock generation cycle by the random number clock generation circuit B51 is approximately 0.14 μs, and the normally operated clock count circuits B81 to B84 count up to 16 bits. By multiplying the number of count values (65536), it is possible to calculate the generation period of the count signal (also the generation period of the overflow signal as a high signal). Therefore, the random number clock generation circuit B51 is normal. If it works, this 1 Overflow signal ms at a period of the following order as a high signal is always outputted. Therefore, if the overflow signal output from the overflow signal output circuit B97 is monitored at a period longer than 10 ms, it can be reliably detected whether or not the random number clock generation circuit B51 is operating normally.

  Next, the clock monitoring circuit B95 will be described together with FIG. 6 which is an enlarged view of the clock monitoring circuit B95 in the random number generation unit 750. The clock monitoring circuit B95 for monitoring the abnormal operation of the clock generation circuit B51 is composed of capacitors C3 and C4, diodes D1 and D2, a transistor TR1 and the like. The capacitor C3 is connected to the 1Q terminal of the random number clock inverting circuit B61 as a coupling capacitor, and the collector side of the transistor TR1 is connected to the 3A terminal of the input circuit unit B40. The collector side of the transistor TR1 is also connected to the positive side of the power supply E via a resistor R6. The diode D1 and the resistor R5 are both for keeping the cathode side of the diode D1 always at a positive potential.

  The capacitor C3 has a role of passing only a periodic pulse signal (clock signal) from the clock generation circuit B51 from which the DC component is cut to the clock monitoring circuit B95 side. For this reason, when the clock generation circuit B51 stops operating (pulse oscillation is stopped) due to some trouble occurring in the clock generation circuit B51, the clock generation circuit B51 outputs a constant high signal or low signal that does not change with time. Thus, the output signal from the clock generation circuit B51 is not transmitted to the clock monitoring circuit B95 side. That is, the input signal input to the clock monitoring circuit B95 changes according to the operation status of the clock generation circuit B51.

  The smoothing circuit unit B96 configured in the clock monitoring circuit B95 smoothes the pulse signal input from the clock generation circuit B51 and always outputs a voltage higher than a predetermined value (for example, 5 V or more). It comprises a diode D2 connected as an anode, a smoothing capacitor C4 connected between the cathode of the diode D2 and the ground, and the like. The diode D2 is for always holding the cathode side at a positive potential. Further, the smoothing capacitor C4 smoothes the pulse signal that has passed through the diode D2 and always outputs a voltage higher than a predetermined value, and this output voltage is applied to the transistor TR1 as a base voltage.

  The collector side of the transistor TR1 is connected to the 3A terminal of the (IC14) of the input circuit unit B40. As described above, the branch line branched from the circuit to the input circuit unit B40 is connected to the power supply E via the resistor R6. Connected to the positive side. In a state where the clock generation circuit B51 normally oscillates a pulse signal, an output voltage equal to or higher than a predetermined level smoothed by the smoothing circuit portion B96 is applied to the transistor TR1 as a base voltage. When a predetermined base voltage (for example, 5 V) is applied to the transistor TR1, a collector current Ic flows from the collector side to the emitter side (ground side) of the transistor TR1.

  The collector current Ic is supplied from the power supply E. When a current flows from the power supply E to the collector side of the transistor TR1, the current Ia does not flow toward the input circuit section B40 (IC14). At this time, an abnormal signal (first abnormal signal) indicating an abnormal operation of the clock generation circuit B51 is not output from the IC 14 to the CPU 732, but a low signal indicating a normal operation of the clock generation circuit B51 is output. The control unit 740 detects the low signal from the IC 14 and determines that the clock generation circuit B51 is operating normally.

  On the other hand, when an abnormal operation occurs in the clock generation circuit B51 and the oscillation of the pulse signal is stopped, no voltage is applied from the smoothing circuit portion B96 to the transistor TR1, and the base voltage is zero (below a predetermined value). Collector current Ic does not flow. For this reason, the current Ia flows from the power source E toward the input circuit section B40 (IC14). When the current Ia flows through the IC 14, a high signal as an abnormal signal is output from the IC 14. When detecting a high signal from the IC 14, the control unit 740 determines that an abnormal operation has occurred in the clock generation circuit B51.

  As described above, the transistor TR1 serves as a switch that allows the current supplied from the power source E to flow to the clock monitoring circuit B95 side or cuts off this current, and to the IC14 side by stopping the oscillation of the pulse signal. When the current Ia flows, the controller 740 can determine the abnormal operation of the clock generation circuit B51 by outputting an abnormal signal from the IC 14 via the CPU data bus to the CPU 732.

  FIG. 7 and FIG. 8 are waveform diagrams showing temporal changes of signal waveforms in the clock generation circuit B51, the clock monitoring circuit B95, and the input circuit unit B40. 7 and 8, Va indicates a clock signal (pulse signal) output from the clock generation circuit B51 and input to the clock monitoring circuit B95. Vb represents the cathode side output of the diode D1 of the input signal that has passed through the coupling capacitor C3.

  As shown in FIG. 7, the clock generation circuit B51 operates normally until the time point a and the pulse signal is oscillated toward the clock monitoring circuit B95. Therefore, Vb has the same pulse as the input waveform to the clock monitoring circuit B95. Signal.

  On the other hand, when a low signal is output from the clock generation circuit B51, the oscillation of the pulse signal is stopped at the time point a, and after that, a constant low signal that does not change with time is output from the clock generation circuit B51. The signal does not pass through the capacitor C3, and the cathode side output Vb of the diode D1 becomes zero.

Vc shows the base voltage of the transistor TR1 which is smoothed by the smoothing circuit B96, the transistor TR1 is made to flow the collector current Ic when the base voltage Vc is greater than or equal _to V ₀ (e.g., more than 5V) it is. As shown in FIG. 7, until a time point a, a base voltage equal to or higher than V _{0 is} always applied to the transistor TR1 due to the input of the pulse signal to the clock monitoring circuit B95, so that the collector current from the power source E toward the transistor TR1. Ic flows. On the other hand, after the time point a, the pulse signal does not pass through the capacitor C3 and the pulse signal is not output to the cathode side of the diode D1, so the base voltage Vc of the transistor TR1 becomes V ₀ or less and the collector current Ic flows. Absent.

As described above, when the collector current Ic does not flow from the power source E toward the transistor TR1, a current flows from the power source E toward the IC 14, and an abnormal signal is output from the IC 14 toward the CPU 732. Yes. As shown in FIG. 7, the abnormal signal Vd is not output (a low signal is output) until time point a when a base voltage equal to or higher than V ₀ is generated in the transistor TR1. On the other hand, after the time point “a” when the base voltage of the transistor TR1 becomes V ₀ or less, the abnormal signal Vd is output (a high signal is output).

  When the control unit 740 detects the output of the abnormal signal Vd, the control unit 740 determines that an abnormal operation has occurred in the clock generation circuit B51 and outputs a control signal, whereby the first of the error display device 61 is detected. It is possible to notify the abnormal operation by turning on the error display portion 61a and emitting sound from the speaker 45.

On the other hand, as shown in FIG. 8, the pulse signal oscillation stops at the time point b when the high signal is output from the clock generation circuit B51, and a constant high signal that does not change with time from the clock generation circuit B51 thereafter. The same applies to the case where it is output, and the abnormal signal Vd is not output until a time point b at which a base voltage equal to or higher than V ₀ is generated in the transistor TR1 (a low signal is output). On the other hand, after the time point b when the base voltage of the transistor TR1 becomes V ₀ or less, the abnormal signal Vd is output (a high signal is output).

  As described above, the control unit 740 detects whether the clock generation circuit B51 is operating normally by detecting the abnormal signal Vd output from the input circuit unit B40 according to the operation state of the clock generation circuit B51. The control unit 740 can make a determination.

  Next, a first embodiment of the procedure for acquiring, using and monitoring random numbers in an actual game will be described with reference to the flowcharts of FIGS. Note that the flowcharts shown in FIGS. 10 and 11 constitute a single flowchart in which the portions of the circle A are connected to each other, and the flowcharts shown in FIGS. 12 and 13 have one flowchart in which the portions of the circle B are connected. Is configured.

  When the power of the pachinko machine PM is turned on, necessary parameters are initialized and the game process is executed according to the main routine shown in FIG. In this main routine, first, the normal game processing subroutine R1 is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine R1, in step S100, the winning of the hit ball to each winning tool 24a, 24b, 25, 26 is checked.

  Here, the detection period of the start signal from the start winning sensors 51 and 52 by the CPU 732 is set to a predetermined period. A winning that is valid only when the start signal is detected to be a low signal in a certain detection cycle, and a high signal is detected twice in succession to the next detection cycle and further to the next detection cycle. Determined.

  In step S110, it is determined whether or not there is a prize for the first starting prize-winning tool 24a. If it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S180 in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S120.

  In step S120, the first read signal for the upper 8 bits of the 16-bit random number is output from the output circuit unit B45. Then, the first read signal for the upper 8 bits is input to the first read signal input section (G1 terminal of the IC 10) of the first count value storage circuit B91. The count value stored in the register unit (IC6) of the first count value storage circuit B91 is input to the first random number output unit (Y1 terminal to .about.Y1) of the buffer unit (IC10) by the input of the first latch signal based on the winning. Y8 terminal). Then, the process proceeds to step S130.

  In step S130, the count value output in the above stage is input to the main control unit 730 from the upper random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S140. In step S140, the count value input in the above stage is stored in the RAM 734 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to step S150.

  In step S150, the first read signal for the lower 8 bits of the 16-bit random number is output from the first read signal output unit of the output circuit unit B45. Then, the first read signal for the lower 8 bits is input to the first read signal input unit (G1 terminal of IC9) of the first count value storage circuit B91. Then, the count value stored in the register unit (IC5) of the first count value storage circuit B91 by the input of the first latch signal based on the winning is the first random number output unit (Y1 terminal to Y8) of the buffer unit (IC9). Terminal). Then, the process proceeds to step S160.

  In step S160, the count value output in the above stage is input from the lower random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S170. In step S170, the count value input in the above stage is stored in the RAM 734 as the lower 8 bits of a 16-bit random number. Then, together with the upper 8 bits stored in the previous step S140, it is handled as a 16-bit random number. Then, the process proceeds to step S180 in FIG.

  In step S180 of FIG. 11, it is determined whether or not there has been a prize for the second starting prize-winning tool 24b. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S250. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S190.

  In step S190, the second read signal output unit for the upper 8 bits of the 16-bit random number is output from the second read signal output unit of the output circuit unit B45. Then, the second read signal for the upper 8 bits is input to the second read signal input unit (G1 terminal of IC12) of the second count value storage circuit B92. Then, the count value stored in the register unit (IC8) of the second count value storage circuit B92 by the input of the second latch signal based on the winning is the second random number output unit (Y1 terminal to Y8) of the buffer unit (IC12). Terminal). Then, the process proceeds to step S200.

  In step S200, the count value output in the above stage is input to the main control unit 730 from the upper random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S210. In step S210, the count value input in the above stage is stored in the RAM 734 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to step S220.

  In step S220, the second read signal for the lower 8 bits of the 16-bit random number is output from the second read signal output unit of the output circuit unit B45. Then, the second read signal for the lower 8 bits is input to the second read signal input unit (G1 terminal of IC11) of the second count value storage circuit B92. Then, the count value stored in the register unit (IC7) of the second count value storage circuit B92 by the input of the second latch signal based on the winning is the second random number output unit (Y1 terminal to Y8) of the buffer unit (IC11). Terminal). Then, the process proceeds to step S230.

  In step S230, the count value output in the above stage is input from the lower random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S240. In step S240, the count value input in the above stage is stored in the RAM 734 as the lower 8 bits of the 16-bit random number. Then, together with the upper 8 bits stored in the previous step S210, it is handled as a 16-bit random number. Then, the process proceeds to step S250.

  In step S250, various software random numbers used for determining the special symbol are acquired and stored in the RAM 734 as well. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 9, a random number monitoring process subroutine R2 is executed according to the flowchart shown in FIG.

  In the random number monitoring processing subroutine R2, first, in step S300 of FIG. 12, it is determined whether or not there is a winning for the first start winning tool 24a. At this time, when it is determined that the first start winning tool 24a has been won, in the subsequent step S310, the control unit 740 determines whether an abnormal signal is output from the input circuit unit B40.

  Here, if it is determined that an abnormal signal has not been output, it is determined in step S330 whether or not there has been a prize for the second start winning tool 24b. On the other hand, if it is determined in step S310 that an abnormal signal has been output, whether or not there has been a prize for the second start winning tool 24b in step S330 after the first notification determination flag is set in step S320. Is determined. If it is determined in step S300 that the first start winning tool 24a has not been won, the second start winning tool 24b is immediately determined in step S330.

  If it is determined that the second start winning tool 24b has been won as a result of the determination on the second start winning tool 24b in step S330, the control unit 740 uses the input circuit unit B40 in step S340. It is determined whether or not an abnormal signal is output.

  At this time, if it is determined that an abnormal signal has not been output, in the subsequent step S360, it is detected whether the overflow signal is a high signal or a low signal. On the other hand, if it is determined in step S340 that an abnormal signal has been output, after the first notification determination flag is set in step S350, the overflow signal is a high signal or a low signal in step S360. Whether it is a signal is detected. If it is determined in step S330 that the second start winning tool 24b has not been won, the overflow signal is immediately detected in step S360.

  In step S360, when the CPU 732 detects that the overflow signal is a high signal, it is determined that all of the first to fourth clock count circuits B81 to B84 are operating normally, and subsequent step S370. The high signal output from the overflow signal output circuit B97 is reset to the low signal by the control signal output from the CPU 732 toward the overflow signal output circuit B97. Thereafter, the process proceeds to the notification determination process shown in FIG.

  In this manner, by changing the overflow signal as the high signal from the overflow signal output circuit B97 to the low signal under the control of the CPU 732, preparation for the next monitoring by the CPU 732 is made. That is, in the next monitoring, if all of the first to fourth clock count circuits B81 to B84 are operating normally, the high signal is output again from the overflow signal output circuit B97, and the first to fourth clocks are output. If any of the count circuits B81 to B84 has a problem, the overflow signal as a low signal remains output, so that the operation check of the first to fourth clock count circuits B81 to B84 is performed every monitoring. Is possible.

  In step S360, when the CPU 732 detects that the overflow signal remains a low signal, it is determined that a failure has occurred in any of the first to fourth clock count circuits B81 to B84. After the second notification determination flag is set in step S380, the process proceeds to the notification determination process shown in FIG.

  In the notification determination process, first, in step S400, it is determined whether the first notification determination flag or the second notification determination flag is set. At this time, if it is determined that neither the first notification determination flag nor the second notification determination flag is set, the process returns to the main routine. On the other hand, when it is determined that the first notification determination flag or the second notification determination flag is set, the count value stored in the RAM 734 in the previous step S170 is read into the CPU 732 (step S410). In subsequent step S420, the hit determination means B37 determines whether the count value read into the CPU 732 is a win random number or a lost random number. Specifically, the corresponding determination result is acquired with reference to the count value and the data in the hit determination table B38 in the ROM 733.

  At this time, when the hit determination means B37 determines that the count value is a hit random number, in step S430, the control unit 740 outputs a control signal to the error display device 61 to display an error, In addition, a control signal is output to the speaker 45 to generate a warning sound. Here, when the first notification determination flag is set, the first error display unit 61a is turned on to indicate an abnormal operation of the random number clock generation circuit B51, and the second notification determination flag is set. The second error display portion 61b is turned on to indicate abnormal operation of the first to fourth clock count circuits B81 to B84.

  In the subsequent step S440, the operation of the pachinko machine PM is stopped based on the control signal output from the control unit 740, and the game is disabled. Then, using a reset button (not shown) for releasing the operation stop of the pachinko machine PM as a release condition (step S450), the first notification determination flag and the second notification determination flag are reset (step S460). Return to the routine.

  On the other hand, if the hit determination means B37 determines in step S420 that the count value is a random random number, the control unit 740 outputs a control signal to the error display device 61 to display an error in step S470. In addition, a control signal is output to the speaker 45 to generate a warning sound. Here, when the first notification determination flag is set, the first error display unit 61a is turned on to indicate an abnormal operation of the random number clock generation circuit B51, and the second notification determination flag is set. The second error display portion 61b is turned on to indicate abnormal operation of the first to fourth clock count circuits B81 to B84. However, in this case, only the error display and the warning sound are generated as described above, and the process returns to the main routine without stopping the operation of the pachinko machine PM.

  In the main routine shown in FIG. 9, following the random number monitoring process, a symbol variation processing subroutine R3 is executed according to the flowchart shown in FIG.

  In the symbol variation processing subroutine R3, first, in step S500 of FIG. 15, it is determined whether or not the number of reserved balls is one or more. When the number of reserved balls is 0, the symbol variation process is not executed, and the process returns to the main routine shown in FIG. On the other hand, if the number of held balls is 1 or more, the process proceeds to step S510. In step S510, 1 is subtracted from the number of reserved balls. Then, the process proceeds to step S520.

  In step S520, among the 16-bit random numbers (up to 4) stored in the RAM 734 in the previous normal game processing subroutine R1, the first stored one is the storage area for work from the storage area on the RAM 734. Is read. The random number is deleted from the storage area. Then, the process proceeds to step S530. In step S530, the random number read into the working storage area in the above-described stage is compared with the symbol data in the symbol data table B36 to determine whether or not the winning is made. If not, the process proceeds to step S550. On the other hand, in the case of winning, the process proceeds to step S540.

  In step S540, a special game flag is set. Then, the process proceeds to step S550. In step S550, the special symbol type is determined according to the presence / absence of winning using the software random number acquired in step S250 of the previous normal game processing subroutine R1, and the special symbol is finally displayed. Such variation display is executed by the symbol display device 28 on the game board 20. Then, the process returns to the main routine shown in FIG.

  In the main routine shown in FIG. 9, next, a special game processing subroutine R4 is executed. In the special game processing subroutine R4, when the special game flag is set in step S540 of the previous symbol variation processing subroutine R3, a special game, that is, a big hit game is executed. Then, after the jackpot game is over, the special game flag is cleared and then the process returns to the main routine. On the other hand, if the special game flag is not set, the process immediately returns to the main routine.

  In the main routine, the game is continued by repeating the subroutines R1 to R4 described above.

  As described above, in the first embodiment, it is possible to determine the occurrence of an abnormal operation in the random number clock generating unit or the random number counting unit. And when abnormal operation | movement generate | occur | produces in these, a game is not continued without noticing this, and it can prevent that a damage arises on the game hall side or the player side.

  Here, a second embodiment of the gaming machine according to the present invention will be described with reference to FIG. 9 to FIG. 13 and FIG. 16 to FIG. In the present embodiment, a brief description will be given centering on the differences from the first embodiment. FIG. 16 is a diagram showing notification determination processing in the random number monitoring processing subroutine, and FIG. 17 is a diagram showing error processing in the normal game processing subroutine.

  In the present embodiment, the notification determination process is executed according to the flow shown in FIG. 16, and in step S900, it is determined whether the first notification determination flag or the second notification determination flag is set in the immediately preceding random number monitoring process. Is done. At this time, if it is determined that neither the first notification determination flag nor the second notification determination flag is set, the process immediately returns to the main routine. On the other hand, if it is determined that the first notification determination flag or the second notification determination flag is set, the preliminary flag is set in subsequent step S910, and then the process returns to the main routine.

  In the main routine, the symbol variation processing subroutine R3 and the special game processing subroutine R4 are continuously executed, and then the normal game processing subroutine R1 is executed again.

  In the present embodiment, when it is determined in step S110 of the normal game processing subroutine R1 shown in FIG. 10 that the first start winning tool 24a has been won, in step S170, the lower order of the 16-bit random numbers is determined. After 8 bits are stored in the RAM 734, the process proceeds to an error processing subroutine as indicated by a chain line. As shown in FIG. 17, in the error processing subroutine, it is determined in step S800 whether or not a preliminary flag is set in the notification determination process. Here, if it is determined that the reserve flag is not set, the process proceeds to step S180 in FIG. 11, and the normal game process is continued thereafter.

  On the other hand, if it is determined in step S110 that there is no winning in the first start winning tool 24a, the process proceeds to step S180 in FIG. 11, and the normal game process is continued thereafter.

  In step S180, if it is determined that the second start winning tool 24b has been won, the lower 8 bits of the 16-bit random number are stored in the RAM 734 in step S240, and then indicated by a chain line. Return to the error processing subroutine again. As shown in FIG. 16, in the error processing subroutine, in step S800, it is determined whether or not the preliminary flag is set in the notification determination processing. Here, if it is determined that the reserve flag is not set, in step S250, various software random numbers for use in determining the special symbol are acquired and stored in the RAM 734. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 9, a random number monitoring process subroutine R2 is executed according to the flowchart shown in FIG.

  On the other hand, if it is determined in step S180 that there has been no winning in the second start winning tool 24b, the process proceeds to step S250. In step S250, various software random numbers to be used for determining the special symbols are acquired and stored in the RAM 734. Then, the process returns to the main routine shown in FIG. 9, and the random number monitoring processing subroutine R2 is a flowchart shown in FIG. Executed according to

  If it is determined in step S1100 in FIG. 17 that the preliminary flag has been set in the previous notification determination process, the count value read into the CPU 732 by the hit determination means B37 in step S1110 is a hit random number. It is determined whether it is a lost random number or not. Specifically, the corresponding determination result is acquired with reference to the count value and the data in the hit determination table B38 in the ROM 733.

  At this time, when the hit determination means B37 determines that the count value is a hit random number, in step S1120, the control unit 740 outputs a control signal to the error display device 61 to display an error, In addition, a control signal is output to the speaker 45 to generate a warning sound. Here, when the first notification determination flag is set, the first error display unit 61a is turned on to indicate an abnormal operation of the random number clock generation circuit B51, and the second notification determination flag is set. The second error display portion 61b is turned on to indicate abnormal operation of the first to fourth clock count circuits B81 to B84.

  In the following step S1130, the operation of the pachinko machine PM is stopped based on the control signal output from the control unit 740, and the game is disabled. Then, the operation of a reset button (not shown) for releasing the operation stop of the pachinko machine PM is set as a release condition (step S1140), the preliminary flag is reset (step S1150), the first notification determination flag, and the second notification determination flag. Is reset (step S1160), and the process returns to the main routine.

  On the other hand, if the hit determination means B37 determines in step S1110 that the count value is a random random number, the control unit 740 outputs a control signal to the error display device 61 to display an error in step S1170. In addition, a control signal is output to the speaker 45 to generate a warning sound. Here, when the first notification determination flag is set, the first error display unit 61a is turned on to indicate an abnormal operation of the random number clock generation circuit B51, and the second notification determination flag is set. The second error display portion 61b is turned on to indicate abnormal operation of the first to fourth clock count circuits B81 to B84. However, in this case, only the error display and the warning sound are generated as described above, and the process returns to the main routine without stopping the operation of the pachinko machine PM.

  As described above, in the second embodiment, it is possible to determine the occurrence of an abnormal operation in the random number clock generation means or the random number count means, and obviously an abnormal operation occurs in the random number clock generation means or the random number count means. Since it is determined that the random number is acquired, it is possible to determine that the acquired random number is generated by an abnormal operation of the random number clock generation unit or the random number counting unit.

  Although preferred embodiments of the present invention have been described so far, the scope of the present invention is not necessarily limited to the above-described embodiments. For example, in the above embodiment, the abnormal signal Vd is switched from the low signal to the high signal based on the oscillation stop of the clock generation circuit B51, and when the high signal is detected, the random number clock generation circuit B51 When a normal abnormal operation is determined, but on the contrary, the abnormal signal Vd is switched from a high signal to a low signal based on the oscillation stop of the clock generation circuit B51, and a low signal is detected. Alternatively, the abnormal operation of the random number clock generation circuit B51 may be determined to perform a predetermined notification indicating the abnormal operation of the clock generation circuit B51 and stop the game.

  In addition, the abnormal signal output from the input circuit unit B40 is input and stored in, for example, the RAM 734 as operation information of the random number clock generation circuit B51, and the control unit 740 monitors the operation information stored in the RAM 734. It may be configured to detect whether or not the random number clock generation circuit B51 is operating normally.

  According to such a configuration, when an abnormal signal output from the input circuit unit B40 is input to the RAM 734 as a low signal (inversely, it may be a high signal), for example, operation information as off information is stored in the RAM 734. When the off information in the RAM 734 is read by monitoring by the control unit 740 (the operation information as the on information may be stored in the RAM 734, and this on information may be read. It is determined that the random number clock generation circuit B51 is operating normally.

  On the other hand, when an abnormal operation occurs in the random number clock generation circuit B51, an abnormality as a high signal is output, and the RAM 734 stores operation information as ON information. At this time, the control unit 740 can read the ON information in the RAM 734 to determine the abnormal operation of the random number clock generation circuit B51 (stored in the RAM 734 as ON information when a low signal is output, On-information may be read by the control unit 740 to determine abnormal operation).

  In the above embodiment, the overflow signal is switched from the low signal to the high signal based on the output of the count signal from the fourth clock count circuit B84, and the first signal is detected when the high signal is detected. When the normal operation of the fourth clock count circuits B81 to B84 is determined and a low signal is detected, the abnormal operation in any of the first to fourth clock count circuits B81 to B84 is determined. On the contrary, it is configured to switch from a high signal to a low signal based on the output of the count signal, and when the low signal is detected, the first to fourth clock count circuits B81 to B84 are normal. When the operation is judged and a high signal is detected, any of the first to fourth clock count circuits B81 to B84 is judged to be abnormal. It may be.

  Further, the count signal output from the carry signal output unit (CO terminal) of the fourth clock count circuit B84 is configured to be output to the overflow signal output circuit B97 every time 16-bit counting is completed. However, for example, a count signal output terminal may be provided between the count output units QC and QD of the first clock count circuit B81, and the count signal may be output from the count signal output terminal. According to such a configuration, every time a count is output from the count output unit QC of the first clock count circuit B81, a count signal is output to the abnormal signal output means. Then, the abnormal signal monitoring means monitors whether an abnormal signal as a high signal (or low signal) is output from the abnormal signal output means, so that one of the first to fourth clock count circuits B81 to B84. Any abnormal operation can be detected.

  Further, the overflow signal output from the overflow signal output circuit B97 is input and stored in, for example, the RAM 734 as the operation information of the first to fourth clock count circuits B81 to B84, and the CPU 732 stores the operation information stored in the RAM 734. By monitoring, it may be configured to detect whether or not all of the first to fourth clock count circuits B81 to B84 are operating normally.

  According to such a configuration, when the overflow signal output from the overflow signal output circuit B97 is input to the RAM 734 as a high signal (the count signal from the count circuit is input directly to the RAM 734 to store the operation information). For example, the operation information as on-information is stored in the RAM 734, and when the CPU 732 reads the on-information in the RAM 734 (the operation information as off-information is stored in the RAM 734, the off-information is stored in the RAM 734). It is also possible to read them.) It is determined that all of the first to fourth clock count circuits B81 to B84 are operating normally. The CPU 732 rewrites the on information in the RAM 734 to off information (when stored as off information, it is rewritten to on information).

  On the other hand, if an abnormal operation occurs in any of the first to fourth clock count circuits B81 to B84, the overflow signal is output as a low signal, and the RAM 734 stores operation information as off information. At this time, the CPU 732 reads off information in the RAM 734 to determine an abnormal operation in any of the first to fourth clock count circuits B81 to B84 (on when a low signal is output). The information may be stored in the RAM 734 as information, and the on-information may be read by the CPU 732 to determine abnormal operation).

  In the above embodiment, a pachinko machine PM has been described as an example of a gaming machine having a random number generator, but the pachinko machine PM is an example of a gaming machine, and the gaming machine is not limited to a pachinko machine. It may be a slot machine. In this case, the symbol display device that displays a plurality of types of symbols based on the extraction result by the random number extraction means is constituted by, for example, a spinning reel device having a plurality of spinning reels that can be rotated by a motor drive. .

It is a front view of the game board of the gaming machine according to the present invention. It is a figure showing the internal structure of the gaming machine according to the present invention. It is a block diagram showing the outline of the control system provided in the said gaming machine. It is a block diagram showing the part concerning control of the gaming machine provided in the gaming machine and the part concerning generation of random numbers. It is a circuit diagram showing the random number generation part in the said gaming machine. It is an enlarged view of the clock monitoring circuit in the random number generator. It is the figure which showed the signal produced | generated in the said random number generation part with the timing chart. It is the figure which showed the signal produced | generated in the said random number generation part with the timing chart. It is the figure which showed the main routine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed a part of random number monitoring process subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed a part of random number monitoring process subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed the alerting | reporting determination process in the said random number monitoring process subroutine. It is the figure which showed the symbol fluctuation process subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed the alerting | reporting determination process in the random number monitoring process subroutine in 2nd Embodiment. It is the figure which showed the process for error in the normal game process subroutine in 2nd Embodiment.

Explanation of symbols

28 Symbol display device 45 Speaker (notification means)
61 Error display device (notification means)
61a First error display section ( first notification section )
61b Second error display section ( second notification section )
732 CPU (Random number extraction means)
740 Control unit ( signal monitoring means )
750 Random number generator B35 Symbol lottery means (random number extraction means)
B37 Hit determination means (random number determination means)
B40 input circuit (abnormal signal output means)
B51 Random number clock generation circuit (random number clock generation means)
B81 First clock count circuit (random number counting means)
B82 Second clock count circuit (random number counting means)
B83 Third clock count circuit (random number counting means)
B84 Fourth clock count circuit (random number counting means)
B95 Clock monitoring circuit (pulse oscillation detection means)
B96 Smoothing circuit section
B97 Overflow signal output circuit (monitoring signal output means)
E Power supply TR1 Transistor PM Pachinko machine (game machine)

Claims (7)

A random number clock generating means for generating a clock at a predetermined frequency; a random number counting means for counting a random number value based on a clock generated by the random number clock generating means; and the random value counted by the random number counting means. Random number extracting means for extracting one count value, random number determining means for determining whether or not the count value extracted by the random number extracting means is a hit random number, and predetermined on the game board based on a determination result by the random number determining means in the symbol display device and game machine configured to have a for displaying the symbols,
Pulse oscillation detection means for detecting whether or not the input signal from the random number clock generation means is a pulse signal output at a predetermined period by a normal operation of the random number clock generation means;
When it input signal from the random clock generator by the pulse oscillation detection signal is not the pulse signal according to the normal operation of the random number clock generating means is detected, indicating the occurrence of abnormal operation of the random number clock generating means An abnormal signal output means for outputting an abnormal signal ;
A monitoring signal output means for outputting a monitoring signal based on a count signal output from the random number counting means every time the random number value is counted by the operation of the random number counting means ;
Based on whether or not the abnormal signal is output from the abnormal signal output means, it is determined whether or not the random number clock generating means is operating normally, and the monitoring signal is output from the monitoring signal output means Whether or not the random number count is cycled over a predetermined period, and when the monitoring signal is detected, it is determined that the random number counting means is operating normally. And the signal monitoring means for determining that the random number counting means is operating abnormally when the monitoring signal is not detected ,
A first notification unit for performing a predetermined notification indicating the occurrence of an abnormal operation of the random number clock generation unit when the signal monitoring unit determines that the random number clock generation unit is performing an abnormal operation; and Notification means comprising a second notification unit for performing a predetermined notification indicating the occurrence of abnormal operation of the random number counting means when it is determined by the means that the random number counting means is causing abnormal operation ;
When the random number clock generating means or said random number counting means is judged to be abnormally operated by the signal monitoring means, said when the count value is determined to be the random number per by the random number determination unit stops the game operation with more performing said predetermined notification to the notification means, wherein when it is determined not to be a random number per the count value by the random number determination unit performs only more predetermined notification to the notification means A gaming machine characterized by continuing a gaming operation . It said pulse oscillation detection means, always a smoothing circuit section for outputting a predetermined voltage higher than the pulse signal is smoothed by the normal operation of the random number clock generating means off in response to the load voltage from the smoothing circuit 2. The gaming machine according to claim 1, comprising a power source connected to the pulse oscillation detection means and the abnormal signal output means and a transistor that cuts off or conducts the pulse oscillation detection means by operation. The random number clock when the input signal from the generating means is the pulse signal according to the normal operation of the random number clock generating means, the current from the power source the transistor is turned on by the load voltage from the smoothing circuit Flows to the side of the pulse oscillation detection means,
When the input signal from the random clock generator is not the pulse signal according to the normal operation of the random number clock generating means, the power supply by the off operation of the transistor and the power supply and the pulse oscillation detection means is interrupted The gaming machine according to claim 2, wherein the current flows from the abnormal signal output means and the abnormal signal is output from the abnormal signal output means . The monitoring signal is configured to switch from a low signal to a high signal based on an output of the count signal by a normal operation of the random number counting means,
The signal monitoring means monitors whether the monitoring signal is switched from the low signal to the high signal every predetermined period longer than the round of the random number count , and the high signal is detected. wherein when said random number counting means determines that is operating normally resets said monitoring signal to said low signal, it is detected the monitoring signal remains the low signal when the The gaming machine according to any one of claims 1 to 3, wherein the random number counting means determines that an abnormal operation has occurred . The monitoring signal is configured to switch from a high signal to a low signal based on the output of the count signal by normal operation of the random number counting means,
The signal monitoring means monitors whether or not the monitoring signal is switched from the high signal to the low signal every predetermined period longer than the round of the random number count , and the low signal is detected. wherein when said random number counting means determines that is operating normally resets said monitoring signal to said high signal, it is detected the monitoring signal remains the high signal when the The gaming machine according to any one of claims 1 to 3, wherein the random number counting means determines that an abnormal operation has occurred . Said notification means, when said monitor signal by the signal monitoring means remains the low signal has been detected, to claim 4, characterized in that the predetermined notification in the second notification unit The gaming machine described. Said notification means, when said monitoring signal remains the high signal is detected by the signal monitoring means, to claim 5, characterized in that the predetermined notification in the second notification unit The gaming machine described.

Images