JP2006136625A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent possible damages on the side of the game parlor by detecting the abnormality at the random number generation part of the game machine. <P>SOLUTION: A pachinko game machine PM is constituted of a random number generation circuit B51, clock counting circuits B81-B84, first-fourth counts memory circuits B91-B94, a pattern lottery means B35, a pattern display device 28 for displaying the winning pattern or the loss pattern based on the result of the lottery by the pattern lottery means B35. It also has a clock monitoring circuit B95 which detects whether the input signal from the random number clock generation circuit B51 is the pulse signal or not, an input circuit part B40 which outputs the abnormality signal indicating the generation of the abnormal operation of the random number clock generation circuit B51 when it is detected that the input signal is not the pulse signal and a special game regulation means (CPU 732) which regulates the special game based on the detection of the abnormality signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine including a random number generation unit, and more particularly to a gaming machine including a random number generation unit that generates a random number for symbol lottery or the like by hardware configured by a random number clock generation circuit or the like when playing a game. .

In a gaming machine equipped with such a random number generator, a predetermined number of digits are generated by a clock count circuit based on a clock generated at a predetermined cycle by a random number clock generator circuit composed of an oscillator such as a crystal resonator or an oscillator. The CPU that controls the game periodically extracts the count value stored in the count value storage circuit and reads it, and stops the read count value in the symbol display device on the game board. It is used as a random number for symbol drawing, etc. for determining symbols. By using a random number generator that counts random values by hardware as described above, the software load is reduced as compared with the case where software controlled by the CPU executes a program and counts random values. Random numbers can be generated and updated at high speed according to the clock generation cycle of the clock generation circuit. The above is also described in Patent Document 1 and Patent Document 2, for example.
JP 2003-190483 A JP 7-124296 A

  However, in a gaming machine using a random number generator that counts a random value by hardware as described above, if any abnormal operation occurs in a random number clock generator circuit (oscillator) that constitutes the random number generator, There was a case where the random number value was not counted periodically and the count was stopped. In such a state, the CPU repeatedly reads the same count value stored in the count value storage circuit. And even if it falls into such a state, since a game machine continues operation | movement without alert | reporting abnormal operation | movement, it was hard to notice abnormal operation | movement of a random number generation part. At this time, if a lottery random number which is disadvantageous for the game hall is repeatedly read by the player continuing the game, damage has occurred on the game hall side.

  In view of the problems as described above, an object of the present invention is to provide a gaming machine capable of detecting an abnormal operation in a random number clock generation circuit constituting a random number generation unit and preventing damage to the gaming hall side. And

  In order to solve the above-described problems, a gaming machine according to the present invention uses a random number clock generation unit (for example, a random number clock generation circuit B51 in the embodiment) that generates a clock at a predetermined frequency and a clock generated by the random number clock generation unit. Based on random number counting means (for example, the first clock count circuit B81, the second clock count circuit B82, the third clock count circuit B83, and the fourth clock count circuit B84 in the embodiment) that counts the random number value based on the random number value Random number extraction means (for example, CPU 732 and symbol lottery means B35 in the embodiment) for extracting and outputting one count value at a predetermined timing from the counted random number values, and the count value output from the random number extraction means To generate special games that benefit players A hit determination means for comparing a predetermined hit random number value to determine whether or not the count value is a predetermined hit random number value, and a predetermined value when the hit determination means determines that the count value is a hit random number value. In a gaming machine configured to display a winning symbol and to display a predetermined loss symbol in a visible manner when it is determined that the winning symbol is not a random number value, the input signal from the random number clock generating unit generates a random number clock. Pulse oscillation detection means (for example, clock monitoring circuit B95 in the embodiment) for detecting whether or not the pulse signal is output at a predetermined cycle due to normal operation of the means, and the input signal from the random number clock generation means is a random number When it is detected that the signal is not a pulse signal due to the normal operation of the clock generator, the occurrence of abnormal operation of the random clock generator is indicated. Abnormal signal output means for outputting an abnormal signal (for example, the input circuit unit B40 in the embodiment) and special game restriction means for restricting a special game based on detection of the abnormal signal (for example, the CPU 732 in the embodiment). .

  Further, in the gaming machine having the above-described configuration, the special game restricting means determines in the hit determining means that the count value is a predetermined random number value that causes the predetermined display symbol to be displayed in the symbol display means based on the detection of the abnormal signal. It is preferable to change the count value input to the hit determination means as described above.

  On the other hand, in the gaming machine having the above-described configuration, the special game regulation unit may display a predetermined loss symbol on the symbol display unit without performing the determination by the hit determination unit based on the detection of the abnormal signal.

Furthermore, in the gaming machine configured as described above, the special game regulation means is based on the detection of an abnormal signal.
Even if it is determined that the count value is a random number value by the hit determination means, the transition to the special game may be prohibited.

  In the gaming machine configured as described above, the pulse oscillation detection means smoothes the pulse signal generated by the normal operation of the random number clock generation means and always outputs a predetermined voltage or higher, and the voltage from the smoothing circuit section. A power source connected to the pulse oscillation detection means and the abnormal signal output means and a transistor that cuts off or conducts the pulse oscillation detection means by an on / off operation according to the load.

  Further, in the gaming machine configured as described above, when the input signal from the random number clock generating means is a pulse signal due to the normal operation of the random number clock generating means, the transistor is turned on by the load of voltage from the smoothing circuit section and the power supply When the input signal from the random number clock generating means is not a pulse signal due to the normal operation of the random number clock generating means, the power source and the pulse oscillation detecting means are As a result of the interruption, the current from the power source flows to the abnormal signal output means side, and the abnormal signal output means outputs an abnormal signal.

  Further, in the gaming machine having the above configuration, notification signal output means for outputting a notification signal for performing a predetermined notification indicating an abnormal operation of the random number clock generation means when an abnormal signal is detected by the abnormal signal output means (for example, It is preferable to have the control unit 740) in the embodiment.

  According to the gaming machine according to the present invention, the pulse oscillation detecting means monitors whether or not an abnormal operation has occurred in the random number clock generating means during the operation of the random number generating unit mounted on the gaming machine. When an abnormal operation of the random number clock generating means occurs, the pulse oscillation detecting means immediately detects the abnormal operation of the random number clock generating means, and the abnormal signal output means outputs an abnormal signal. The special game restricting means is configured to restrict a special game that gives a profit to the player based on the detection of the abnormal signal. Therefore, the abnormal operation of the random number clock generation means can be detected immediately, and a disadvantageous game is not played in the game hall without noticing the malfunction of the clock generation means (so-called “big hit game” is performed). It is possible to prevent damage to the game hall side.

  The special game regulation means can regulate the special game by various methods. That is, the special game is regulated by determining that the winning random number value is a lost random number value based on the detection of the abnormal signal, or without determining whether or not the random number value is the winning random number in the hit determining means. The game hall side by several methods, such as preventing the generation of a special game when the abnormal signal is detected, but the count value is extracted by the random number extraction means. Can be prevented from being damaged.

  Further, if the special game is restricted as described above by executing software, it can be handled only by changing the software, and the special game can be restricted at a low cost. Further, when an abnormality occurs in hardware other than the random number clock generation means, for example, even when an abnormality occurs in the random number counting means, which cannot be detected by the pulse oscillation detection means, special execution is performed as described above. Since it is configured to restrict the game, it can cope with the occurrence of an abnormality in the entire hardware, and can surely prohibit the transition to the special game.

  Furthermore, a random number change circuit is provided to change the count value output from the random number counting means based on the abnormal signal or the count value stored in the random number storage means to a random number that is disadvantageous to the player, and an abnormal signal is output. During this time, it is possible to prevent damage on the game hall side by a method in which the lost random number is output from the random number counting means or the random number storage means.

  Further, according to the gaming machine having the above configuration, when an abnormal operation of the random number clock generating means occurs, a notification signal is output, and the occurrence of the abnormal operation is immediately displayed by the error display device. It is possible to recognize this abnormal operation early.

  Further, according to the gaming machine configured as described above, the pulse oscillation detection means for checking whether or not the pulse signal is output from the random number clock generation means and causing the abnormal signal output means to output the abnormal signal, the diode, It can be configured with only inexpensive parts such as transistors and capacitors.

  Hereinafter, a preferred embodiment of a gaming machine according to the present invention will be described in detail with reference to FIGS. 1 is an external front view of a pachinko machine described as an example of the above gaming machine, FIG. 2 is a rear view showing the internal structure of the pachinko machine, and FIG. 3 is an outline of a control system provided in the pachinko machine. FIG. 4 is a block diagram showing a part related to the control of the pachinko machine provided in the pachinko machine and a part related to the generation of random numbers. FIG. 5 shows a random number generation part and its surroundings in the pachinko machine. FIG. 6 is an enlarged view of the clock monitoring circuit in the random number generator, and FIGS. 7 and 8 are timing charts showing signals generated in the random number generator. 9 to 20 are diagrams showing procedures for obtaining and using the random numbers for symbol lottery and detecting an abnormality in the random number generator.

  Here, first, a schematic configuration of a pachinko machine PM described as an example of the gaming machine will be described with reference to FIG. 1 and FIG. As shown in FIG. 1, this pachinko machine PM is configured to have a rectangular frame size and a rectangular frame size adapted to the opening front of the outer frame 1 that forms a vertically fixed holding frame. The front frame 2 is attached by hinge members 3a and 3b disposed on the upper left and right sides of the front side so that it can be opened and closed laterally and attached and detached. It is held in the engaged closed state.

  On the front side of the front frame 2, a glass door 5 that can be seen through the game board 20 through a transparent plate material such as a polycarbonate plate or a glass plate that has a square shape matched to the front area of the front frame 2 and is attached to the center portion; The upper ball tray 6 that aligns the game balls stored in the ball tray and guides them one by one to the hitting ball launching device 9 is assembled so as to be openable and closable and detachable sideways by a hinge mechanism built in the left edge. Usually, it is held in a closed state covering the front surface of the front frame 2 using the locking device 4 and a lock mechanism (not shown). A prize ball payout exit 6b for paying out a prize ball is provided on the upper left side of the contact plate 6a which is a horizontal rectangle in the upper ball tray 6 and can be opened and closed with respect to the front frame 2. On the lower left side of the upper ball tray 6, there is provided a sound emitting unit 6c that emits sound from a speaker (not shown) that generates sound effects according to the game development status. A lower ball tray 7 for storing game balls is provided at the lower part of the front frame 2, and an operation handle 8 for performing a game ball launching operation is attached along with the lower ball tray 7.

  The game board 20 includes a decorative board (also referred to as a veneer) 21 having a predetermined design cell attached to a surface of a laminated plywood having a thickness of about 19 mm cut into a predetermined shape. On the front side of the decorative plate 21, a belt-like outer rail 23a and an inner rail 23b are fixed in an arc shape, and a game area PA is defined on the inner side surrounded by the guide rails 23a and 23b. In the game area PA, the first start winning tool 24a, the second start winning tool 24b, the general winning tool 25, the winning tool such as an attacker having the large winning tool 26, and a predetermined pattern according to the progress of the game are displayed. A symbol display device 28 or the like that is displayed so as to be visible to the player is attached, and game balls that have fallen without winning the prize-winning tools 24a, 24b, 25, and 26 are placed on the back side of the game board 20 at the lower end of the game area PA. An outlet 27 for discharging is provided. Further, four special symbol holding lamps 90, 90, 90, 90 are provided above the symbol display device 28.

  The symbol display device 28 is located almost at the center of the game board 20 and displays a “special symbol” consisting of a combination of three-digit symbols on a liquid crystal screen. Of these special symbols, three digits are displayed. In any case, a combination of the same kind of patterns is referred to as a “hit pattern”.

  In addition to a predetermined number of prize balls (for example, five balls) being paid out to the player from the prize ball outlet 6b of the upper ball tray 6 when there is a prize for the first start prize 24a or the second start prize 24b. The symbol display device 28 is activated, and the variation of the symbol is started. As a result of this change, when the special symbol to be stopped and displayed is a winning symbol, a “hit game” advantageous to the player is generated.

  In this jackpot game, the big prize 26 which is normally closed is opened. When there is a prize for the big prize tool 26, a predetermined number (for example, 15 balls) of prize balls are paid out to the player from the prize ball payout exit 6b. The big winning tool 26 is temporarily closed when either a predetermined time (for example, 30 seconds) has elapsed after being opened or when a predetermined number (for example, 10 balls) has been won. If there is a prize in a V zone (not shown) provided inside the big prize tool 26 while the big prize tool 26 is opened, the big prize tool 26 is once closed and then opened again. It is supposed to be. As a result, the opening of the big prize tool 26 can be continued up to 16 times. In addition, when the big winning tool 26 has been opened 16 times, or when there is no winning in the V zone during the opening of the big winning tool 26, the big hit game is ended.

  When the hit ball wins the first start winning tool 24a or the second start winning tool 24b during the variable display on the symbol display device 28, the special symbol holding lamps 90, 90, 90, 90 are a maximum of four. It is supposed to light up to pieces. That is, the subsequent operation of the symbol display device 28 is guaranteed by the number of times corresponding to the number of the special symbol holding lamps 90, 90, 90, 90 being lit.

  In the first start winning tool 24a, a hitting ball flow path for detecting the hit of the first starting winning tool 24a is detected and a detection signal is output to start the symbol display on the symbol display device 28. A first start winning sensor 51 is provided. The first start winning sensor 51 uses a magnetic sensor and outputs a first start signal that takes two states of a high signal and a low signal as a detection signal. The first start signal is output as a high signal when a hit ball is not detected, and is output as a low signal only while a hit ball is detected. An optical or mechanical sensor may be used as the first start winning sensor 51.

  In addition, the hitting flow path in the second start winning tool 24b is detected by the same magnetic sensor as the first start winning sensor 51 to detect the hit of the hit ball on the second starting winning tool 24b, and a detection signal is output. A second start winning sensor 52 is provided for starting the display of symbol variation on the display device 28. The second start winning sensor 52 outputs a second start signal that takes two states of a high signal and a low signal as a detection signal. The second start signal outputs a high signal when no hit ball is detected, but outputs a low signal only while the hit ball is passing. An optical or mechanical sensor may be used as the second start winning sensor 52.

As shown in FIG. 2, the lower part of the rear surface of the front frame 2 has a hitting ball launching device 9 that launches a game ball toward the outer rail 23 a, and an operation of the hitting ball launching device 9 in response to the turning operation of the operation handle 8. A launcher control board 200 to be controlled is attached. Further, behind the upper ball tray 6 is formed an auxiliary mechanism portion called a game assisting board whose front side is normally covered with the upper ball tray 6 that is normally held closed, and a ball hitting device on the front side. Foul ball collection that discharges the game ball launched by 9 toward the outer rail 23a and the foul ball returned to the ball launcher 9 side without reaching the game area PA to the lower ball tray 7 A route member, a speaker (not shown) and the like for generating sound effects according to the game development status are attached.

  A back set board 30 is attached to the back of the front frame 2. This back set board 30 has a rectangular shape somewhat smaller than the inner size of the outer frame 1, and is configured based on a base frame body 31 integrally formed with a window 31w penetrating the front and back at the center. . Back set board swinging hinge members 32 and 33 are fixed to the side edge of the base frame body 31 at a predetermined interval in the vertical direction. The upper and lower back set panel swinging hinge members 32 and 33 are fixed to the front frame 2. The back set board 30 is mounted on the back side of the front frame 2 so that it can be opened and closed laterally and detachable by engaging with the upper and lower fixed hinge members 12 and 13 and swinging or disengaging. The closing lever 34 is used to close and hold the back of the front frame 2.

  The back set board 30 is provided with a prize ball path for paying out prize balls so as to surround the window 31w. That is, on the back side of the base frame 31, a tank member 35 for storing and supplying game balls, an alignment rod member 36 for aligning and flowing down game balls supplied from the tank member 35, and an alignment rod member 36 are supplied. A prize ball standby passage 37 for receiving and waiting for a predetermined number of game balls, a ball payout device 38 for paying out the game balls waiting in the prize ball standby passage 37 based on predetermined winning conditions, etc. A prize ball path such as a prize ball payout path 39 for guiding the game balls paid out from the payout device 38 to the upper and lower ball trays 6 and 7 is provided. In addition, on the front side of the base frame 31, an out ball and a safe ball that are positioned below the window 31 w and discharged to the back side of the game board 20, and a punch that is discharged from the middle of the winning ball path by the ball punching mechanism. A collecting path (not shown) for collecting balls and the like is formed, and a ball discharging path (not shown) is formed on the back surface side of the base frame 31 to discharge the game balls gathered connected to the collecting path to a collection bucket on the gaming facility side. ing.

  In each part of the back surface of the back set board 30, a main board 700 that comprehensively controls the operation of the pachinko machine PM, a ball payout board 300 that controls the operation of the ball payout device 38 based on a command signal from the main board 700, A lamp / voice control board 400 that controls the operation of effect lighting and sound effects, a power supply board 500 that supplies power to these control boards and various electronic devices, and a gaming machine management device (management computer) installed in the game hall On the other hand, a circuit board such as an external terminal board 600 as an external connection device that outputs various game information is detachably attached, and each circuit board and electronic equipment are connected by a wire harness (not shown) to constitute a pachinko machine PM. Is done. Also, below the ball payout board 300, an error display device 61 (error LED) is used to notify when an abnormal operation or the like occurs in these circuit boards including the main board 700 on a screen using a light emitting diode. Is provided.

  The pachinko machine PM is used in a game with the glass door 5, the upper ball tray 6, the back set board 30 and the like closed, and the front frame 2 closed and locked to the outer frame 1. The game is started by storing the game balls in the upper ball tray 6 and rotating the operation handle 8, and the game balls stored in the upper ball tray 6 are sent one by one to the hitting ball launcher 9 and are operated. The pachinko game is developed by being struck into the game area PA with the strength corresponding to the rotation operation angle.

  Next, an outline of a control system for controlling the pachinko machine PM will be described with reference to FIG. As shown in FIG. 3, the control system includes a main board 700, a first start winning sensor 51, a second start winning sensor 52, a symbol display device 28, an external terminal board 600, and an error display device 61. It is electrically connected by a cable or the like.

  The main board 700 includes a system program that manages the entire operation of the pachinko machine PM, a storage unit that is pre-stored with a game execution program, and a microprocessor that executes these programs (hereinafter, “ A main control unit 730 having a CPU ”and a random number generation unit 750 for generating random numbers for symbol lottery (65536 random numbers from 0 to 65535) irrespective of the control of the main board 700. Yes. In the present invention, the random number is not only a value that is randomly generated in a mathematical sense, but even if the generation is regular, the acquisition timing is random, so that the random number is substantially a random number. It also means a functional value. In the present invention, the random value counted by the clock count circuits B81 to B84, which will be described later, and stored in the first and second count value storage circuits B91 and B92 will be specifically referred to as “count value”.

  The control unit 740 in the main control unit 730 is provided with a ROM 733 and a RAM 734 in addition to the CPU 732 described above, and a control program to be executed by the CPU 732 and data necessary for the control process are described in the ROM 733. The main control unit 730 is provided with a reference clock generation circuit 731. The reference clock generation circuit 731 is a circuit that generates a reference clock that is an operation reference of the CPU 732 that plays a central role in the control of the pachinko machine PM. ). In addition, the reference clock may be obtained by appropriately dividing the pulse by the frequency divider 735.

  The CPU 732 has a symbol lottery means B35 including a hit determination means B37. When the main board 700 detects a low signal from the first start prize sensor 51 or the second start prize sensor 52, the symbol lottery means B35 causes the random number generator 750 to sequentially generate 65536 random numbers. By acquiring one count value, the stop symbol in the symbol display device 28 is determined.

  In the hit determination table B38 on the ROM 733, data is recorded so that a unique determination result of “Random number” or “Lose random number” for one random number value is determined for the entire range of random values. ing. That is, 65536 random numbers always belong to either the winning random number or the lost random number, and do not belong to both or neither. Here, the winning random number means a random value that causes the symbol display device 28 to stop-display a predetermined winning symbol combination that generates a jackpot game.

  The hit determination means B37 in the CPU 732 compares and refers to the count value extracted and output by the symbol lottery means B35 and the data stored in the determination table B38, that is, the determination result corresponding to the count value, that is, Whether the count value is a hit random number or a lost random number is acquired.

  In the symbol data table B36 on the ROM 733, symbol data for determining a stop symbol in the symbol display device 28 is recorded. Each symbol data is given an address number, and one symbol data is specified from one address number. When the count value extracted by the symbol lottery means B35 is determined to be a winning by the hit determining means B37, the symbol data in which the winning symbol is stored is selected as appropriate. Then, a predetermined symbol selected based on the control signal from the main board 700 is displayed on the symbol display device 28.

  As will be described later, the random number generation unit 750 includes a clock monitoring circuit B95 that detects whether or not the random number clock generation circuit B51 is operating normally.

  The main board 700 is electrically connected to the outside of the pachinko machine PM via the external terminal board 600, and various game information output from the main board 700 is transmitted to a management computer outside the pachinko machine PM. It can be made to. The game information includes a notification signal output from the control unit 740 that detects some abnormality in the main board 700 and the like, and can notify the management computer of the abnormality of the pachinko machine PM. The hall can immediately recognize this abnormality.

  Further, the error display device 61 is connected to the main board 700 via a wiring cable, and the error display device 61 is notified by a notification signal output from the control unit 740 that detects an abnormality in each circuit board such as the main board 700. Can be turned on.

  Here, with reference to FIG. 4 and FIG. 5, the structure of the part which concerns on generation | occurrence | production of the random number in the pachinko machine PM, extraction of this, and abnormality detection of a random number generation means is demonstrated. The input circuit unit B40 is a part to which input information from outside the main substrate 700, a random number generated by a random number generation unit 750 provided in the main substrate 700, an abnormal signal from a clock monitoring circuit B95 described later, and the like are input. It is composed of a buffer IC or the like. Specifically, the input circuit unit B40 receives from the first start winning sensor 51 or the second start winning sensor 52 that is output in accordance with the winning of the hit ball to the first start winning tool 24a or the second start winning tool 24b. And the upper and lower 8 bits of the random number generated by the random number generator 750 are input. Further, an output signal from the random number clock generation means B51 is input to the input circuit section B40, and whether or not this output signal is a pulse signal due to normal operation of the random number clock generation means B51 is input via the input circuit section B40. Is monitored by the control unit 740.

  The output circuit unit B45 outputs a read signal for reading control signals to the electrical components (lamps, speakers, etc.) outside the main substrate 700 and random numbers generated by the random number generator 750 provided in the main substrate 700. This part is composed of an IC such as a buffer. Specifically, from the output circuit unit B45, when the main board 700 determines that the first starting prize-winning tool 24a has won a prize, the first read signal that triggers reading of the count value corresponding to the prize, When the main board 700 determines that the second starting prize-winning tool 24b has won a prize, a second read signal that triggers reading of the count value corresponding to the prize is output. Further, when an abnormal operation is detected in the random number clock generation means B51 or the clock count circuits B81 to B84, a notification signal is output to the outside of the pachinko machine PM through the external terminal board 600. In addition, a notification signal is output toward the error display device 61 to display a predetermined error.

  The first start signal from the first start winning sensor 51 is input to the 1A terminal of the IC 14 of the input circuit unit B40. On the other hand, the second start signal from the second start winning sensor 52 is input to the 2A terminal of the IC 14 of the input circuit unit B40. Further, the 3A terminal of the IC 14 is connected to the collector of the transistor TR1 constituting the clock monitoring circuit B95, and when a voltage is applied to the base of the transistor TR1, a collector current flows from the input circuit part B40 side. Yes.

  The random number generator 750 generates a count value used as a random number. Specifically, the random number generator 750 includes a random number clock generation circuit B51, a random number clock inversion circuit B61, first and second latch signal output circuits B71, B72, The first to fourth clock count circuits B81, B82, B83, and B84, first and second count value storage circuits B91 and B92, and a clock monitoring circuit B95 are included.

  The random number clock generation circuit B51 (OSC1) is for generating a clock for counting random numbers and includes a clock output unit (OUT) for outputting the generated clock. The random number clock generation circuit B51 is constituted by, for example, a crystal oscillator that generates a 7.15909 MHz clock.

  The random number clock inversion circuit B61 (IC18) inverts the clock output from the random number clock generation circuit B51, and uses the inverted clock as an inverted clock, which will be described later, a first latch signal output circuit B71 (IC16) and a second latch signal output circuit. The data is output to B72 (IC17). Specifically, in the IC 18, a signal obtained by inverting the signal output from the 1Q terminal is output as an inverted signal from the 1Q inverting terminal that is the inverted clock output unit, and the rising edge of the clock is the falling edge of the inverted clock. The falling edge of the clock corresponds to the rising edge of the inverted clock. The random number clock inverting circuit B61 may be configured using an IC such as a NOT gate.

  Each of the first to fourth clock count circuits B81, B82, B83, and B84 has a random number clock input unit (CK) for inputting a clock and a count output unit (QA to QD) for outputting the counted random number value. ing. As shown in FIG. 5, the first to fourth clock count circuits B81, B82, B83, and B84 are constituted by a circuit in which four 4-bit increment counters (from IC1 to IC4) are cascade-connected to generate a random number clock. This is a circuit for adding at the rising edge of the clock generated by the circuit B51 and outputting the addition result.

  In response to the input of the clock from the random number clock generation circuit B51, first, the first clock count circuit B81 (IC1) counts a value for four digits (for example, “0001” and “0011”). When "1111" is counted and the count of four digits ends, a carry signal is output from the CO terminal of IC1 to the ENT terminal of the second clock count circuit B82 (IC2) each time. In order for the second clock count circuit B82 to start counting, it is necessary to input the carry signal from the first clock count circuit B81. That is, in the IC2, the next four digits are started only after the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B51 are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC2, a carry signal is sent from the CO terminal of IC2 to the third clock count circuit B83 each time. It is output to the ENT terminal of (IC3). In order for the third clock count circuit B83 to start counting, it is necessary to input the carry signal from the second clock count circuit B82. That is, in IC3, the count of the value for the next four digits is started only when the carry signal and the clock from the random number clock generation circuit B51 (input to the CK terminal) are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC3, the carry signal is counted from the CO terminal of IC3 to the fourth clock each time. It is output to the ENT terminal of the circuit B84 (IC4). In order for the fourth clock count circuit B84 to start counting, it is necessary to input the carry signal from the third clock count circuit B83. That is, in the IC4, the count of the next four digits is started only when the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B51 are input simultaneously.

  As described above, 16-bit binary numbers are generated by the clock count circuits B81 to B84. That is, among the 16-digit binary numbers, the first clock count circuit B81 (IC1) is the lowest four digits, the second clock count circuit B82 (IC2) is the upper four digits, and the third clock count circuit B83 (IC3 ) Is further responsible for the upper 4 digits and the fourth clock count circuit B84 (IC4).

  The counts added by the four clock count circuits B81 to B84 are sent to the first count value storage circuit B91 and the second count value storage circuit B92 via the respective count output sections (QA, QB, QC and QD terminals). Each is output and stored. In this embodiment, an addition type increment counter is used as the clock count circuit. However, in other embodiments, a subtraction type decrement counter may be used. In this embodiment, a 16-bit random number (4 bits × 4) is generated. However, in other embodiments, the number of bits is not limited to 16 bits and may be changed as appropriate. .

  The latch signal output circuits B71 and B72 include a first latch signal output circuit B71 (IC16) related to acquisition of a random number associated with winning in the first starting prize-winning tool 24a and a random number associated with winning in the second starting prize-winning tool 24b. The second latch signal output circuit B72 (IC17) related to acquisition is divided.

  The inverted clock from the random number clock inverter circuit B61 (IC18) is input to the first latch signal output circuit B71 (IC16) via the first inverted clock input section (1CK). At the same time, the first start signal from the first start winning sensor 51 is input to the first start signal input unit (1D) via the buffer (IC13). When the first start signal (low signal) is input via the first start signal input section (1D), the first latch signal output circuit B71 uses the rising edge of this signal as the first inverted clock input. The first count value storage circuit B91 (IC5 and IC6) passes through the first latch signal output unit (1Q) as the first latch signal after being delayed in synchronization with the rising edge of the inverted clock input from the unit (1CK). Output to.

  On the other hand, the second latch signal output circuit B72 (IC17) receives the inverted clock from the random number clock inverter circuit B61 via the second inverted clock input section (2CK). At the same time, the second start signal from the second start winning sensor 52 is input to the second start signal input unit (2D). When the second start signal (low signal) is input through the second start signal input unit (2D), the second latch signal output circuit B72 sends the rising edge of this signal from the inverted clock input unit. After being delayed so as to be synchronized with the rising edge of the input inverted clock, the second latch signal is output to the second count value storage circuit B92 (IC7 and IC8) via the second latch signal output unit (2Q).

  The first and second start signals are also input to the main control unit 730 via the input circuit unit B40 and the like, as will be described later, and may be used as a timing for starting a program executed for random number acquisition. It is supposed to be used.

  The count value storage circuits B91 and B92 are a first count value storage circuit B91 that temporarily stores a random number derived from winning in the first start winning tool 24a and a random number derived from winning in the second starting winning tool 24b. Is divided into a second count value storage circuit B92 for temporarily storing.

  The first count value storage circuit B91 uses the count value counted by the clock count circuits B81 to B84 based on the first latch signal from the first latch signal output circuit B71 (the first count from the first start winning sensor 51). When a start signal is received and a latch signal is output from the first latch signal output circuit B71, it is stored. On the other hand, the second count value storage circuit B92 calculates the count value counted by the clock count circuits B81 to B84 based on the second latch signal from the second latch signal output circuit B72 (from the second start winning sensor 52). The second start signal is received and stored (when a latch signal is output from the second latch signal output circuit B72).

  As shown in FIG. 5, the first count value storage circuit B91 includes a register unit (IC5 and IC6) including two 8-bit ICs and a buffer unit (IC9 and IC10) including two 8-bit ICs. The Similarly, the second count value storage circuit B92 includes a register unit (IC7 and IC8) including two 8-bit ICs and a buffer unit (IC11 and IC12) including two 8-bit ICs.

  Of the register portion of the first count value storage circuit B91, the IC5 receives the 4-digit count value from the first clock count circuit B81 (IC1) through the D1 terminal to the D4 terminal, The 4-digit count value from the clock count circuit B82 (IC2) is input via the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC5 function as a count input unit, and the lower 8 digits of the 16-bit binary count value derived from the first start prize 24a are input to the IC5 through them. .

  Of the register section of the first count value storage circuit B91, the IC6 receives the 4-digit count value from the third clock count circuit B83 (IC3) via the D1 terminal to the D4 terminal, A 4-digit count value from the clock count circuit B84 (IC4) is input from the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC 6 function as a count input unit, and the upper 8 digits of the 16-bit binary count value derived from the first start prize 24a are input to the IC 6 through these. .

  Of the register unit of the second count value storage circuit B92, the IC7 receives the 4-digit count value from the first clock count circuit B81 (IC1) through the D1 terminal to the D4 terminal, The 4-digit count value from the clock count circuit B82 (IC2) is input via the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC 7 function as a count input unit, and the lower 8 digits of the 16-bit binary count value derived from the second start prize 24b are input to the IC 7 through these terminals. .

  Of the register unit of the second count value storage circuit B92, the IC8 receives the 4-digit count value from the third clock count circuit B83 (IC3) through the D1 terminal to the D4 terminal, A 4-digit count value from the clock count circuit B84 (IC4) is input from the D5 terminal to the D8 terminal. That is, the D8 terminal to D8 terminal of the IC8 function as a count input unit, and the IC8 receives the upper 8 digits of the 16-bit binary count value derived from the second start prize 24b through them. The

  The first latch signal from the first latch signal output circuit B71 is input to the CLOCK terminal in the register unit (IC5 and IC6) of the first count value storage circuit B91. That is, these CLOCK terminals function as a first latch signal input section, and at the time of the rising edge when the first latch signal input from the first latch signal input section becomes a high signal, the clock count circuit B81. The count value input from ~ B84 is stored in the register unit.

  The second latch signal from the second latch signal output circuit B72 is input to the CLOCK terminal in the register unit (IC7 and IC8) of the second count value storage circuit B92. That is, these CLOCK terminals function as a second latch signal input unit, and at the time of the rising edge when the second latch signal input from the second latch signal input unit becomes a high signal, the clock count circuit B81. The count value input from ~ B84 is stored in the register unit.

  The G1 terminal in the buffer unit (IC9 and IC10) of the first count value storage circuit B91 corresponds to a read signal output from the output circuit unit B45 of the main control unit 730 based on a program executed for random number acquisition. Thus, one count value consisting of 16 digits stored in the first count value storage circuit B91 is output to the CPU 732. That is, at the time of the falling edge when the read signal input from the read signal input unit becomes a low signal, the random numbers stored in the register units (IC5 and IC6) are transferred to the CPU via the Y1 terminal to Y8 terminal, respectively. Output to the data bus.

  Of the random numbers output from the first count value storage circuit B91, those passing through the IC 9 are input to the CPU 732 and handled as the lower 8 digits of the 16-digit random numbers. On the other hand, among the random numbers output from the first count value storage circuit B91, those passing through the IC 10 are input to the CPU 732 and handled as the upper 8 digits of the 16-digit random numbers.

  The terminal G1 in the buffer unit (IC11 and IC12) of the second count value storage circuit B92 stores a second count value according to the read signal output from the output circuit unit B45 of the main control unit 730 based on the program. One count value consisting of 16 digits stored in the circuit B 92 is output to the CPU 732. That is, at the time of the falling edge when the read signal input from the read signal input unit becomes a low signal, the random numbers stored in the register units (IC7 and IC8) are transferred to the CPU data via the Y1 terminal to Y8 terminal, respectively. Output to the bus.

  Among the random numbers output from the second count value storage circuit B92, those passing through the IC 11 are input to the CPU 732 and handled as the lower 8 digits of the 16-digit random numbers. On the other hand, among the random numbers output from the second count value storage circuit B92, those passing through the IC 12 are input to the CPU 732 and handled as the upper 8 digits of the 16-digit random numbers.

  Next, the clock monitoring circuit B95 will be described together with FIG. 6 which is an enlarged view of the clock monitoring circuit B95 in the random number generation unit 750. The clock monitoring circuit B95 for monitoring the abnormal operation of the clock generation circuit B51 is composed of capacitors C3 and C4, diodes D1 and D2, a transistor TR1 and the like. The capacitor C3 is connected to the 1Q terminal of the random number clock inverting circuit B61 as a coupling capacitor, and the collector side of the transistor TR1 is connected to the 3A terminal of the input circuit unit B40. The collector side of the transistor TR1 is also connected to the positive side of the power supply E via a resistor R6. The diode D1 and the resistor R5 are both for keeping the cathode side of the diode D1 always at a positive potential.

  The capacitor C3 has a role of passing only a periodic pulse signal (clock signal) from the clock generation circuit B51 from which the DC component is cut to the clock monitoring circuit B95 side. For this reason, when the clock generation circuit B51 stops operating (pulse oscillation is stopped) due to some trouble occurring in the clock generation circuit B51, the clock generation circuit B51 outputs a constant high signal or low signal that does not change with time. Thus, the output signal from the clock generation circuit B51 is not transmitted to the clock monitoring circuit B95 side. That is, the input signal input to the clock monitoring circuit B95 changes according to the operation status of the clock generation circuit B51.

  The smoothing circuit unit B96 configured in the clock monitoring circuit B95 smoothes the pulse signal input from the clock generation circuit B51 and always outputs a voltage higher than a predetermined value (for example, 5 V or more). It comprises a diode D2 connected as an anode, a smoothing capacitor C4 connected between the cathode of the diode D2 and the ground, and the like. The diode D2 is for always holding the cathode side at a positive potential. Further, the smoothing capacitor C4 smoothes the pulse signal that has passed through the diode D2 and always outputs a voltage higher than a predetermined value, and this output voltage is applied to the transistor TR1 as a base voltage.

  The collector side of the transistor TR1 is connected to the 3A terminal of the (IC14) of the input circuit unit B40. As described above, the branch line branched from the circuit to the input circuit unit B40 is connected to the power supply E via the resistor R6. Connected to the positive side. In a state where the clock generation circuit B51 normally oscillates a pulse signal, an output voltage equal to or higher than a predetermined level smoothed by the smoothing circuit portion B96 is applied to the transistor TR1 as a base voltage. When a predetermined base voltage (for example, 5 V) is applied to the transistor TR1, a collector current Ic flows from the collector side to the emitter side (ground side) of the transistor TR1.

  The collector current Ic is supplied from the power supply E. When a current flows from the power supply E to the collector side of the transistor TR1, the current Ia does not flow toward the input circuit section B40 (IC14). At this time, an abnormal signal indicating an abnormal operation of the clock generation circuit B51 is not output from the IC 14 to the CPU 732.

  On the other hand, when an abnormal operation occurs in the clock generation circuit B51 and the oscillation of the pulse signal is stopped, no voltage is applied from the smoothing circuit portion B96 to the transistor TR1, and the base voltage is zero (below a predetermined value). Collector current Ic does not flow. For this reason, the current Ia flows from the power source E toward the input circuit section B40 (IC14). When the current Ia flows through the IC 14, an abnormal signal is output from the IC 14 toward the CPU 732.

  As described above, the transistor TR1 serves as a switch that allows the current supplied from the power source E to flow to the clock monitoring circuit B95 side or cuts off this current, and to the IC14 side by stopping the oscillation of the pulse signal. When the current Ia flows, an abnormal signal is output from the IC 14 to the CPU 732 via the CPU data bus, so that the control unit 740 can determine the abnormal operation of the clock generation circuit B51.

  FIG. 7 and FIG. 8 are waveform diagrams showing temporal changes of signal waveforms in the clock generation circuit B51, the clock monitoring circuit B95, and the input circuit unit B40. 7 and 8, Va indicates a clock signal (pulse signal) output from the clock generation circuit B51 and input to the clock monitoring circuit B95. Vb represents the cathode side output of the diode D1 of the input signal that has passed through the coupling capacitor C3.

  As shown in FIG. 7, the clock generation circuit B51 operates normally until the time point a and the pulse signal is oscillated toward the clock monitoring circuit B95. Therefore, Vb has the same pulse as the input waveform to the clock monitoring circuit B95. Signal.

  On the other hand, when a low signal is output from the clock generation circuit B51, the oscillation of the pulse signal is stopped at the time point a, and after that, a constant low signal that does not change with time is output from the clock generation circuit B51. The signal does not pass through the capacitor C3, and the cathode side output Vb of the diode D1 becomes zero.

Vc shows the base voltage of the transistor TR1 which is smoothed by the smoothing circuit B96, the transistor TR1 is made to flow the collector current Ic when the base voltage Vc is greater than or equal _to V ₀ (e.g., more than 5V) is. As shown in FIG. 7, until a time point a, a base voltage equal to or higher than V _{0 is} always applied to the transistor TR1 due to the input of the pulse signal to the clock monitoring circuit B95. Ic flows. On the other hand, after the time point a, the pulse signal does not pass through the capacitor C3 and the pulse signal is not output to the cathode side of the diode D1, so that the base voltage Vc of the transistor TR1 becomes V ₀ or less and the collector current Ic flows. Absent.

As described above, when the collector current Ic does not flow from the power source E toward the transistor TR1, a current flows from the power source E toward the IC 14, and the abnormal signal Vd is input to the 3A terminal of the IC 14. ing. As shown in FIG. 7, the abnormal signal Vd is not output toward the IC 14 (a low signal is output) until a time point a at which a base voltage equal to or higher than V ₀ is generated in the transistor TR1. On the other hand, after the time point “a” when the base voltage of the transistor TR1 becomes V ₀ or less, the abnormal signal Vd is output (a high signal is output).

  When the abnormal signal Vd is output to the 3A terminal of the IC 14, an abnormal signal as a low signal is output from the 3Y terminal of the IC 14. When the control unit 740 detects the abnormal signal as the low signal, the control unit 740 determines that an abnormal operation has occurred in the clock generation circuit B51 and outputs a notification signal to the outside of the pachinko machine PM via the external terminal board 600. To do. In addition, the control unit 740 can also output a notification signal to the error display device 61 to turn on the error display device 61 and notify the abnormal operation of the clock generation circuit B51.

On the other hand, as shown in FIG. 8, the pulse signal oscillation stops at the time point b when the high signal is output from the clock generation circuit B51, and thereafter, a constant high signal that does not change with time is generated from the clock generation circuit B51. The same applies to the case where the signal is output, and the abnormal signal Vd is not output until the time point b at which the base voltage equal to or higher than V ₀ is generated in the transistor TR1 (a low signal is output). On the other hand, after the time point b when the base voltage of the transistor TR1 becomes V ₀ or less, the abnormal signal Vd is output (a high signal is output). When the abnormal signal Vd is output, an abnormal signal as a low signal is output from the 3Y terminal of the IC 14, and when the control unit 740 detects the abnormal signal as the low signal, the control unit 740 causes the pachinko machine to A notification signal is output outside the PM, and the error display device 61 is turned on to notify the abnormal operation of the clock generation circuit B51.

  As described above, when the input circuit unit B14 (IC14) detects the abnormal signal Vd output from the input circuit unit B40 according to the operating state of the clock generation circuit B51, the clock generation circuit B51 operates normally. The control unit 740 can determine whether or not there is an abnormality, and when it is determined that an abnormal operation has occurred, this can be notified.

  Next, procedures for obtaining and using random numbers in an actual game and detecting an abnormality in the random number generator will be described with reference to the flowcharts of FIGS. The control program is executed by the CPU 732 along the flowchart shown below. The control program to be executed by the CPU 732 and data necessary for the control process are described in the ROM 733.

  First, the first embodiment will be described with reference to FIGS. FIG. 9 is a diagram showing a main routine in the procedure for obtaining, using, and detecting abnormality of the random number generator in the pachinko machine, and FIGS. 10 and 11 are for obtaining the random numbers for design lottery in the pachinko machine. FIG. 12 is a diagram showing a part of the normal game processing subroutine in the procedure for detecting abnormality in the use and random number generator, and FIG. 12 is a symbol variation in the procedure for acquiring, using, and detecting abnormality in the random number generator in the pachinko machine It is the figure which showed the processing subroutine. Further, the flowcharts shown in FIGS. 10 and 11 constitute one flowchart in which the portions of the circle A are connected to each other.

  When the power of the pachinko machine PM is turned on, necessary parameters are initialized, and then a program relating to game processing is executed according to the main routine shown in FIG. In this main routine, first, the normal game processing subroutine R1 is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine R1, in step S100, the winning of the hit ball to the first starting winning tool 24a and the second starting winning tool 24b is checked.

  Here, the detection period of the start signal from the start winning sensors 51 and 52 by the CPU 732 is set to a predetermined period. A winning that is valid only when the start signal is detected to be a low signal in a certain detection cycle, and a high signal is detected twice in succession to the next detection cycle and further to the next detection cycle. Determined.

  In step S110, it is determined whether or not there is a prize for the first starting prize-winning tool 24a. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S200 in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S120.

  In step S120, the control unit 740 determines whether an abnormal signal is output from the input circuit unit B40. If it is determined that an abnormal signal is output, the random number extracted by the symbol lottery means B35 is rewritten to the predetermined lost random number stored in the hit determination table B38 in step S190, Saved in the RAM 734. Further, in step S195, the control unit 740 outputs a notification signal to the error display device 61 to display an error. The notification signal is transmitted to the management computer installed in the game hall via the external terminal board 600, and this abnormality is immediately recognized on the game hall side. Then, the process proceeds to step S200 in FIG.

  If it is determined in step S120 that no abnormal signal has been output, the process proceeds to step S130. In step S130, the first read signal for the upper 8 bits of the 16-bit random number is output from the output circuit unit B45. Then, the first read signal for the upper 8 bits is input to the first read signal input section (G1 terminal of the IC 10) of the first count value storage circuit B91. The count value stored in the register unit (IC6) of the first count value storage circuit B91 is input to the first random number output unit (Y1 terminal to .about.Y1) of the buffer unit (IC10) by the input of the first latch signal based on the winning. Y8 terminal). Then, the process proceeds to step S140.

  In step S140, the count value output in the above stage is input to the main control unit 730 from the upper random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S150. In step S150, the count value input in the above stage is stored in the RAM 734 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to step S160.

  In step S160, the first read signal for the lower 8 bits of the 16-bit random number is output from the first read signal output unit of the output circuit unit B45. Then, the first read signal for the lower 8 bits is input to the first read signal input unit (G1 terminal of IC9) of the first count value storage circuit B91. Then, the count value stored in the register unit (IC5) of the first count value storage circuit B91 by the input of the first latch signal based on the winning is the first random number output unit (Y1 terminal to Y8) of the buffer unit (IC9). Terminal). Then, the process proceeds to step S170.

  In step S170, the count value output in the above stage is input to the main control unit 730 from the lower random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S180. In step S180, the count value input in the above stage is stored in the RAM 734 as the lower 8 bits of the 16-bit random number. Then, together with the upper 8 bits stored in the previous step S150, it is handled as a 16-bit random number. Then, the process proceeds to step S185. In step S185, various software random numbers used for determining the special symbols are acquired and stored in the RAM 734 as well. Then, the process proceeds to step S200 in FIG.

  In step S200 of FIG. 11, it is determined whether or not there is a prize for the second starting prize-winning tool 24b. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process returns to the main routine shown in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there is a winning, the number of reserved balls is incremented by 1, and the process proceeds to step S210.

  In step S210, the control unit 740 determines whether an abnormal signal is output from the input circuit unit B40. If it is determined that an abnormal signal is output, the random number extracted by the symbol lottery means B35 is rewritten to the predetermined lost random number stored in the hit determination table B38 in step S290, Saved in the RAM 734. Further, in step S295, the control unit 740 outputs a notification signal to the error display device 61 to display an error. The notification signal is transmitted to the management computer installed in the game hall via the external terminal board 600, and this abnormality is immediately recognized on the game hall side. Then, the process returns to the main routine shown in FIG.

  If it is determined in step S210 that no abnormal signal has been output, the process proceeds to step S220. In step S220, the second read signal for the upper 8 bits of the 16-bit random number is output from the second read signal output unit of the output circuit unit B45. Then, the second read signal for the upper 8 bits is input to the second read signal input unit (G1 terminal of IC12) of the second count value storage circuit B92. Then, the count value stored in the register unit (IC8) of the second count value storage circuit B92 by the input of the second latch signal based on the winning is the second random number output unit (Y1 terminal to Y8) of the buffer unit (IC12). Terminal). Then, the process proceeds to step S230.

  In step S230, the count value output in the above stage is input to the main control unit 730 from the upper random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S240. In step S240, the count value input in the above stage is stored in the RAM 734 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to step S250.

  In step S250, the second read signal for the lower 8 bits of the 16-bit random number is output from the second read signal output unit of the output circuit unit B45. Then, the second read signal for the lower 8 bits is input to the second read signal input unit (G1 terminal of IC11) of the second count value storage circuit B92. Then, the count value stored in the register unit (IC7) of the second count value storage circuit B92 by the input of the second latch signal based on the winning is the second random number output unit (Y1 terminal to Y8) of the buffer unit (IC11). Terminal). Then, the process proceeds to step S260.

  In step S260, the count value output in the above stage is input from the lower random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S270. In step S270, the count value input in the above stage is stored in the RAM 734 as the lower 8 bits of the 16-bit random number. Then, together with the upper 8 bits stored in the previous step S210, it is handled as a 16-bit random number. Then, the process proceeds to step S280.

  In step S280, various software random numbers used for determining the special symbol are acquired and stored in the RAM 734 as well. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 9, the symbol variation processing subroutine R2 is executed according to the flowchart shown in FIG.

  In the symbol variation processing subroutine R2, first, in step S300 of FIG. 12, is the symbol variation permitted state in which the symbol displayed on the symbol display device 28 is stopped and the special game is not executed? It is determined whether or not. Here, when it is determined that the symbol variation permission state is not set, that is, it is determined that the symbol is being variably displayed on the symbol display device 28 or the special game is being performed. If so, the process returns to the main routine shown in FIG. On the other hand, if it is determined that the symbol variation permission state is set, the process proceeds to step S305. In step S305, it is determined whether or not the number of held balls is one or more. When the number of reserved balls is 0, the symbol variation process is not executed, and the process returns to the main routine shown in FIG. On the other hand, if the number of reserved balls is 1 or more, the process proceeds to step S310. In step S310, 1 is subtracted from the number of reserved balls. Then, the process proceeds to step S320.

  In step S320, among the 16-bit random numbers (up to four) stored in the RAM 734 in the previous normal game processing subroutine R1, the first stored one is the work in the control unit 740 from the storage area on the RAM 734. Read into the storage area. The random number is deleted from the storage area on the RAM 734. Then, the process proceeds to step S330. In step S330, the random number read into the working storage area in the above stage (including the predetermined lost random number read and stored in step S190 and step S290) is stored in the hit determination table B38 by the hit determination means B37. It is determined whether or not it is a win by comparing with the data. If not, the process proceeds to step S350. On the other hand, in the case of winning, the process proceeds to step S340.

  In step S340, a special game flag is set. Then, the process proceeds to step S350. In step S350, a stop symbol is selected by collating the random number read in the work storage area with the symbol data in the symbol data table B36, and finally a predetermined winning symbol or a lost symbol is stopped and displayed. Such variation display is executed by the symbol display device 28 on the game board 20. Then, the process returns to the main routine shown in FIG.

  In the main routine shown in FIG. 9, next, a special game processing subroutine R3 is executed. In the special game processing subroutine R3, when the special game flag is set in step S340 of the previous symbol variation processing subroutine R2, a special game, that is, a jackpot game is executed. In this jackpot game, the big prize device 26 is opened for a predetermined time, which is advantageous for the player. Then, after the jackpot game is over, the special game flag is cleared and then the process returns to the main routine. On the other hand, if the special game flag is not set, the process immediately returns to the main routine.

  In the main routine, the game is continued by repeating the subroutines R1 to R3 described above.

  As described above, in the first embodiment, the special game restricting means (CPU 732) detects the abnormal random number value in the hit judging means based on the detection of the abnormal signal from the abnormal signal output means (input circuit unit B40). By determining that there is a special game, it is possible to regulate the special game and prevent the game hall from being damaged. Further, when an abnormality is detected, the symbol display device 28 is processed so that the lost symbol is stopped and displayed, so that it can be said that the player does not recognize the occurrence of the abnormality.

  Next, a second embodiment of the procedure for acquiring and using random numbers and detecting abnormality in the random number generator will be described with reference to FIG. 9 and the flowcharts of FIGS. Here, the description will focus on the parts different from the first embodiment. FIG. 9 is a diagram showing a main routine in the procedure for obtaining, using, and detecting abnormality of the random number generator in the game machine, and FIGS. 13 and 14 are for obtaining the random numbers for design lottery in the pachinko machine. FIG. 15 is a diagram showing a part of a normal game processing subroutine in the procedure for detecting abnormality in the use and random number generator, and FIG. 15 is a symbol variation in the procedure for acquiring, using, and detecting abnormality in the random number generator in the pachinko machine. It is the figure which showed the processing subroutine. In the flowcharts shown in FIG. 13 and FIG. 14, the circled portions B are connected to each other to form one flowchart.

  Also in the case of the present embodiment, game processing is executed according to the main routine shown in FIG. In this main routine, first, the normal game processing subroutine R1 is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine R1, in step S1100, the winning of a hit ball to the first start winning tool 24a and the second start winning tool 24b is checked.

  In step S1110, it is determined whether or not there is a winning for the first start winning tool 24a. If it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S1200 in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there is a winning, the number of reserved balls is incremented by 1, and the process proceeds to step S1130.

  In steps S1130 to S1180, as in the case of the first embodiment, the upper 8 bits and lower 8 bits of the 16-bit random numbers are stored in the RAM 734 and handled as 16-bit random numbers. . Then, the process proceeds to step S1190. In step S1190, various software random numbers used for determining the special symbol are acquired and stored in the RAM 734 as well. Then, the process proceeds to step S1200 in FIG.

  In step S1200 of FIG. 14, it is determined whether or not there is a winning for the second start winning tool 24b. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process returns to the main routine shown in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S1220.

  In steps S1220 to S1270, as in the case of the first embodiment, the upper 8 bits and lower 8 bits of the 16-bit random numbers are stored in the RAM 734 and handled as 16-bit random numbers. . Then, the process proceeds to step S1280. In step S1280, various software random numbers used for determining the special symbol are acquired and stored in the RAM 734 as well. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 9, the symbol variation processing subroutine R2 is executed according to the flowchart shown in FIG.

  In the symbol variation processing subroutine R2, first, in step S1300 in FIG. 15, is the symbol variation permitted state in which the symbol displayed on the symbol display device 28 is stopped and the special game is not executed? It is determined whether or not. Here, when it is determined that the symbol variation permission state is not set, that is, it is determined that the symbol is being variably displayed on the symbol display device 28 or the special game is being performed. If so, the process returns to the main routine shown in FIG. On the other hand, if it is determined that the symbol variation permission state is set, the process advances to step S1305. In step S1305, it is determined whether or not the number of reserved balls is one or more. When the number of reserved balls is 0, the symbol variation process is not executed, and the process returns to the main routine shown in FIG. On the other hand, when the number of reserved balls is 1 or more, the process proceeds to step S1310. In step S1310, 1 is subtracted from the number of reserved balls. Then, the process proceeds to step S1320.

  In step S1320, among the 16-bit random numbers (maximum 4) stored in the RAM 734 in the previous normal game processing subroutine R1, the first stored one is the work in the control unit 740 from the storage area on the RAM 734. Read into the storage area. The random number is deleted from the storage area on the RAM 734. Then, the process proceeds to step S1330.

  In step S1330, control unit 740 determines whether an abnormal signal is output from input circuit unit B40. If it is determined that an abnormal signal is output, in step 1370, a stop symbol that finally displays a predetermined lost symbol is selected from the symbol data in the symbol data table B36. Is done. Then, in step S1380, the symbol variation display that finally displays the selected predetermined lose symbol is executed on the symbol display device 28 on the game board 20, and in step S1390, the control unit 740 is displayed. Outputs a notification signal to the error display device 61 to display an error. The notification signal is transmitted to the management computer installed in the game hall via the external terminal board 600, and this abnormality is immediately recognized on the game hall side. Then, the process returns to the main routine shown in FIG.

  On the other hand, if it is determined in step S1330 that an abnormal signal has not been output, in the subsequent step S1340, the random number read into the work storage area in the above-described stage is determined by the hit determination means B37 by the hit determination table. By comparing with the data in B38, it is determined whether or not it is a win. If not winning, in step S1355, a stop symbol that finally displays a predetermined lost symbol is selected from the symbol data in the symbol data table B36. Then, the process proceeds to step S1360.

  On the other hand, in the case of winning, in step S1345, a stop symbol that finally displays a predetermined winning symbol is selected from the symbol data in the symbol data table B36, and the process proceeds to step S1350. In step S1350, a special game flag is set. Then, the process proceeds to step S1360. In step S1360, a stop symbol is selected by collating the random number read in the work storage area with the symbol data in symbol data table B36, and finally a predetermined winning symbol or a lost symbol is stopped and displayed. Such a symbol change display is executed by the symbol display device 28 on the game board 20. Then, the process returns to the main routine shown in FIG.

  In the main routine shown in FIG. 9, next, a special game processing subroutine R3 is executed. In the special game processing subroutine R3, when the special game flag is set in step S1340 of the previous symbol variation processing subroutine R2, a special game, that is, a big hit game is executed. In this jackpot game, the big prize device 26 is opened for a predetermined time, which is advantageous for the player. Then, after the jackpot game is over, the special game flag is cleared and then the process returns to the main routine. On the other hand, if the special game flag is not set, the process immediately returns to the main routine.

  In the main routine, the game is continued by repeating the subroutines R1 to R3 described above.

  As described above, in the second embodiment, when an abnormal signal is detected, the CPU 732 does not determine whether or not the count value is a predetermined hit random number in the hit determination means B37. It is possible to prevent damage from occurring. In this embodiment, since the process of rewriting the random number extracted by the symbol lottery means B35 is not performed, it can be said that the software process is easy and the burden on executing the software is light. In addition, when an abnormality is detected, the symbols that are stopped and displayed on the symbol display device 28 are processed so that the lost symbols are automatically set, so that the player does not recognize the occurrence of the abnormality. Can be said

  Next, a third embodiment of the procedure for acquiring and using random numbers and detecting abnormality in the random number generator will be described with reference to the flowcharts of FIGS. Here, the description will focus on the parts different from the first embodiment. FIG. 16 is a diagram showing a main routine in the procedure for obtaining, using, and detecting abnormality of the random number generator in the pachinko machine. FIG. 17 and FIG. FIG. 19 is a diagram showing a part of a normal game processing subroutine in the procedure for detecting abnormality in the use and random number generator, and FIG. 19 is a symbol variation in the procedure for acquiring and using random numbers for symbol lottery in the pachinko machine and detecting the abnormality in the random number generator FIG. 20 is a diagram showing a special game transition processing subroutine in a procedure for obtaining and using a random number for symbol lottery in a pachinko machine and detecting an abnormality in the random number generator, and FIG. 21 is a diagram in the pachinko machine. The figure which shows the design fluctuation processing subroutine in the procedure of acquisition and use of random numbers for lottery and abnormality detection of the random number generator Figure 22 is acquired random number for the symbol lottery in pachinko machine is a diagram showing a special game migration processing subroutine in the use and random number generating unit anomaly detection procedure. In the flowcharts shown in FIGS. 17 and 18, the circled portions C are connected to each other to form one flowchart.

  In this embodiment, the program is executed according to the main routine shown in FIG. In this main routine, first, the normal game processing subroutine R1 ′ is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine R1 ′, in step S2100, the winning of the hit ball to the first start winning tool 24a and the second start winning tool 24b is checked.

  In a succeeding step S2110, it is determined whether or not there is a winning for the first start winning tool 24a. If it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S2200 in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S2120.

  In steps S2120 to S2170, as in the case of the first embodiment, the upper 8 bits and lower 8 bits of the 16-bit random number are stored in the RAM 734 and handled as a 16-bit random number. . Then, the process proceeds to step S2180. In step S2180, various software random numbers used for determining the special symbol are acquired and stored in the RAM 734 as well. Then, the process proceeds to step S2200 in FIG.

  In step S2200 of FIG. 18, it is determined whether or not there has been a prize for the second starting prize-winning tool 24b. If it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S2270. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S2210.

  In steps S2210 to S2260, as in the case of the first embodiment, the upper 8 bits and lower 8 bits of the 16-bit random numbers are stored in the RAM 734 and handled as 16-bit random numbers. . Then, the process proceeds to step S2270. In step S2270, various software random numbers used for determining the special symbol are acquired and stored in the RAM 734 as well. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 16, the symbol variation processing subroutine R2 ′ is executed according to the flowchart shown in FIG.

  In steps S2300 to S2350 in the symbol variation processing subroutine R2 ′, processing similar to that in steps S300 to S350 in the first embodiment as shown in FIG. 12 is executed. In step S2350, a stop symbol is selected by comparing the random number read in the work storage area with the symbol data in symbol data table B36, and then a predetermined winning symbol or a lost symbol is finally stopped and displayed. Such a symbol change display is executed by the symbol display device 28 on the game board 20. Then, the process returns to the main routine shown in FIG.

  In the main routine shown in FIG. 16, next, a special game transition processing subroutine R3 ′ is executed. In the special game process transfer subroutine R3 ′, it is determined in step S2400 whether or not a time period for which the symbol variation timer has already been set as the specified value has elapsed. If it is determined that the symbol variation timer has not yet passed the specified value, the process returns to the main routine shown in FIG.

  On the other hand, if it is determined in step S2400 that the symbol variation timer has passed the specified value, the symbol determination flag is set in subsequent step S2410. In step S2420, it is determined whether or not the special game flag is set in step S2340 of the previous symbol variation processing subroutine R2 ′. If it is determined that the special game flag has not been set, the process returns to the main routine shown in FIG.

  If it is determined in step S2420 that the special game flag has been set in step S2340 of the previous symbol variation processing subroutine R2 ′, an abnormal signal is output from the input circuit unit B40 by the control unit 740 in step S2430. It is determined whether or not it has been done. If it is determined that an abnormal signal is output, the special game flag is reset in step S2440, and then the control unit 740 outputs a notification signal to the error display device 61 in step S2450. Make a display. The notification signal is transmitted to the management computer installed in the game hall via the external terminal board 600, and this abnormality is immediately recognized on the game hall side. Then, the process returns to the main routine shown in FIG.

  On the other hand, if it is determined in step S2430 that an abnormal signal has not been output, the process immediately returns to the main routine shown in FIG. 16, and the special game subroutine R4 ′ is executed.

  In the main routine shown in FIG. 16, next, a special game subroutine R4 ′ is executed. In the special game subroutine R4 ′, a special game, that is, a jackpot game is executed. In this jackpot game, the big prize device 26 is opened for a predetermined time, which is advantageous for the player. Then, after the jackpot game ends, the process returns to the main routine.

  In the main routine, the game is continued by repeating the subroutines R1 to R4 described above.

  The symbol variation processing subroutine R2 ′ and the special game transition processing subroutine R3 ′ may be executed as follows, and the symbol variation processing subroutine R2 ′ and the special game transition processing are performed with reference to FIGS. A modification example of the subroutine R3 ′ will be described.

  As shown in FIG. 21, in steps S3300 to S3330, the same processing as in steps S2300 to S2330 in the symbol variation processing subroutine R2 ′ as shown in FIG. 19 is executed. In step S3330, the random number read into the work storage area of the control unit 740 is compared with the data in the hit determination table B38 by the hit determination means B37 to determine whether or not the winning is made. If not, the process proceeds to step S3380. On the other hand, in the case of winning, the process proceeds to step S3340.

  In step S3340, control unit 740 determines whether or not an abnormal signal is output from input circuit unit B40. If it is determined that an abnormal signal is output, in step S3360, a stop symbol that finally displays a predetermined losing symbol is selected from the symbol data in the symbol data table B36. Is done. Then, the process proceeds to step S3370.

  On the other hand, if it is determined in step S3340 that an abnormal signal has not been output, a stop symbol that finally displays a predetermined winning symbol from symbol data in symbol data table B36 in step S3350. Is selected. Then, the process proceeds to step S3370.

  In step S3370, a special game flag is set. Then, the process proceeds to step S3380. In step S3380, the stop symbol is selected by comparing the random number read into the work storage area of the control unit 740 with the symbol data in the symbol data table B36, and then the predetermined winning symbol or the lost symbol is finally finalized. The symbol change display is executed on the game board 20 by the symbol display device 28 so as to stop the display. Then, the process returns to the main routine shown in FIG.

  In the main routine shown in FIG. 16, a modified example of the special game transition processing subroutine R3 ′ as shown in FIG. 22 is executed. Here, in step S3400, it is determined whether or not the time period for which the symbol variation timer has already been set as the specified value has elapsed. If it is determined that the symbol variation timer has not yet passed the specified value, the process returns to the main routine shown in FIG.

  On the other hand, if it is determined in step S3400 that the symbol variation timer has passed the specified value, the symbol determination flag is turned on in subsequent step S3410. In step S3420, it is determined whether or not the special game flag is set in step S3370 of the previous symbol variation processing subroutine R2 ′. If it is determined that the special game flag has not been set, the process returns to the main routine shown in FIG.

  If it is determined in step S3420 that the special game flag has been set in step S3370 of the previous symbol variation processing subroutine R2 ′, then in step S3430, it is lost in step S3360 of the previous symbol variation processing subroutine R2 ′. It is determined whether or not a symbol has been set. If it is determined that the lost symbol is set, the special game flag is reset in step S3440, and the control unit 740 outputs a notification signal to the error display device 61 in step S3450. Make a display. The notification signal is transmitted to the management computer installed in the game hall via the external terminal board 600, and this abnormality is immediately recognized on the game hall side. Then, the process returns to the main routine shown in FIG. 16 and the special game subroutine R4 ′ is executed.

  As described above, in the third embodiment, the special game restriction means (CPU 732) is operated by the random number extraction means (symbol lottery means B35) regardless of whether there is an abnormal operation in the random number clock generation means (random number clock generation circuit B51). The count value is extracted, but if an abnormal signal from the abnormal signal output means (input circuit unit B40) is detected, a special game is not generated so that damage is caused on the game hall side. It can be prevented. In this embodiment, since the process of rewriting the random number extracted by the symbol lottery means B35 is not performed, it can be said that the software process is easy and the burden on executing the software is light. In addition, when an abnormality is detected, even if the winning symbol is stopped and displayed, it does not shift to a special game, so it is possible to recognize the occurrence of an abnormality in the gaming machine from the outside. On the other hand, in the case of the modified example of the third embodiment, when an abnormality is detected, the symbol that is stopped and displayed on the symbol display device 28 is processed so that the lost symbol is automatically set. Therefore, it can be said that the player does not recognize the occurrence of the abnormality.

  Next, a fourth embodiment of the procedure for acquiring and using random numbers, and detecting the abnormality of the random number generator will be described with reference to the circuit diagrams of FIGS. 23 and 24 and the flowcharts of FIGS. Here, the description will focus on the parts different from the first embodiment. FIG. 23 is a circuit diagram showing a random number generation unit and its periphery in a pachinko machine, and FIG. 24 is an excerpt of a part of the circuit diagram of the random number generation unit and the like as an embodiment of the random number generation circuit provided in the random number change unit. FIG. 25 is a diagram showing a main routine in a procedure for acquiring and using a random number for symbol lottery in a pachinko machine. FIGS. 26 and 27 are procedures for acquiring and using a random number for symbol lottery in a pachinko machine. FIG. 28 is a diagram showing a part of a normal game processing subroutine in FIG. 28, FIG. 28 is a diagram showing a random number monitoring processing subroutine in a procedure for obtaining and using a random number for symbol drawing in a pachinko machine, and FIG. 29 is a symbol drawing in a pachinko machine. It is the figure which showed the design fluctuation processing subroutine in the procedure of acquisition and use of the random number for use.

  Since the circuit configuration of the random number generation unit in this embodiment is slightly different from that in the first embodiment, first, the circuit configuration of the random number generation unit in this embodiment will be described with reference to FIG. The random number generator in this embodiment is configured by further providing a random number changing circuit B97 in the circuit of the first embodiment. The random number changing circuit B97 is configured by a so-called OR circuit having two signal input units (A terminal and B terminal) and one signal output unit (C terminal). The signal input unit includes an abnormal signal input unit (A terminal) to which an abnormal signal output from the 3Y terminal of the input circuit unit B40 (IC14) is input, and a reset signal input unit to which a reset signal from the CPU 732 is input. (B terminal). The signal output unit (C terminal) includes each clear signal input unit (CLR terminal) of the clock count circuits B81 to B84, each clear signal input unit (CLEAR terminal) of the first count value storage circuit B91 (IC5 and IC6), and It is input to each clear signal input section (CLEAR terminal) of the second count value storage circuit B92 (IC7 and IC8).

  Since the random number changing circuit B97 is composed of an OR circuit, when a low signal is input to either the A terminal or the B terminal, a low signal is output from the C terminal. That is, when an abnormal signal as a low signal is input to the A terminal or a reset signal as a low signal is input to the B terminal, a clear signal as a low signal is output from the C terminal. ing.

  With such a circuit configuration, a control signal (low signal) from the CPU 732 is used to reset the random number values of the clock count circuits B81 to B84 and reset the count values stored in the count value storage circuits B91 and B92. The clock monitoring circuit B95 detects an abnormal operation of the random number clock generation circuit B51 and the abnormal signal as a low signal output from the input circuit unit B40 is not only when the reset signal) is input to the B terminal. Even when it is input to the terminal, it is possible to output a clear signal as a low signal toward the clock count circuits B81 to B84, the first count value storage circuit B91, and the second count value storage circuit B92. .

  When a clear signal as a low signal from the random number changing circuit B97 is input to each clear signal input unit (CLR terminal) of the clock count circuits B81 to B84, it is output from each clock count circuit B81 to B84. The count value becomes the reset value (default value) “0000”. That is, while the clear signal as the low signal from the random number changing circuit B97 is being input to each clear signal input unit (CLR terminal), the count value output as the whole of the clock count circuits B81 to B84 is “0000000000000000000”. Become.

  In such a circuit configuration, if “0000000000000000000” is not included as a hit random number stored in the hit determination table B38, a low signal is input to each clear signal input unit (CLR terminal) of each clock count circuit B81 to B84. While the clear signal as a signal is being input, unless the high signal is input to the A terminal of the random number changing circuit B97 by returning the random number clock generation circuit B51 to the normal state, the first latch signal output circuit B71 Even if the first latch signal and the second latch signal from the second latch signal output circuit B72 are input, the winning random numbers in the first count value storage circuit B91 and the second count value storage circuit B92 are advantageous for the player. Is not input as the count value. Therefore, no random number is extracted when an abnormal operation occurs in the random number clock generation circuit B51, and so-called “big hit game” advantageous to the player does not occur.

  In addition, although the value of “0000” has been exemplified as the reset value, even if the value is other than “0000”, it constitutes a lost random number recorded in advance in the hit determination table B38 of the ROM 733. I just need it. That is, a predetermined random number stored in advance in the hit determination table B38 is changed to a random number to be displayed on the symbol display device by the random number changing circuit B97 and output from the first to fourth clock count circuits B81 to B84. The count value may not be included.

  Further, when a clear signal as a low signal from the random number changing circuit B97 is input to each clear signal input section (CLEAR terminal) in the IC5 to IC8 of the first count value storage circuit B91 and the second count value storage circuit B92. The count values stored in IC5 to IC8 at that time are respectively changed to values (for example, “00000000”) that clear the stored contents in IC5 to IC8. That is, while the clear signal as the low signal from the random number changing circuit B97 is being input to each clear signal input unit (CLEAR terminal), each of the first count value storage circuit B91 and the second count value storage circuit B92 The output count value is “0000000000000000000”.

  Thus, by changing the random number value, the clear signal as the low signal is input to each clear signal input section (CLEAR terminal) of the first count value storage circuit B91 and the second count value storage circuit B92. In the meantime, unless the high signal is input to the A terminal of the random number changing circuit B97 by the return of the random number clock generation circuit B51 to the normal state, the read signal output from the output circuit unit B45 is the first count value storage circuit B91. Even if it is input to the second count value storage circuit B92, a winning random number advantageous to the player is not output to the CPU 732. Therefore, no random number is extracted when an abnormal operation occurs in the random number clock generation circuit B51, and so-called “big hit game” advantageous to the player does not occur.

  Note that the random number to be changed in the IC5 to IC8 does not necessarily need to be a value of “00000000”, and even if it is other than a value of “00000000”, it is a loss recorded in advance in the hit determination table B38 of the ROM 733. What constitutes a random number may be used. That is, the first count value storage circuit B91 and the second count value storage circuit are changed by the random number changing circuit B97 to the winning random numbers for displaying the predetermined winning symbols stored in advance in the hit determination table B38 on the symbol display device. What is necessary is just to comprise so that the count value memorize | stored in B92 may not be included.

  Next, another embodiment as means for changing the random number will be described with reference to FIGS. Here, FIG. 24 shows an excerpt of a part of the circuit shown in FIG. This embodiment is an example of a mode in which the count value output from the random number counting means is changed by acting on the random number counting means.

  Specifically, as shown in FIG. 24, the abnormal signal output from the 3Y terminal of the input circuit unit B40 (IC14) is transmitted to the LOAD terminal of the fourth clock count circuit B84 (IC4), the random number clock inversion circuit B61 (IC18). ) 1CLR terminal and the input terminal of the inverter (NOT circuit). The output terminal of the inverter (NOT circuit) is input to one input terminal portion of the OR circuit, and the 1Q terminal of the random number clock inverter circuit B61 (IC18) is connected to the other input terminal portion of the OR circuit. Have been entered. The output terminal portion of the OR circuit is connected to the CK terminal of the fourth clock count circuit B84 (IC4).

  Although not shown in FIG. 24, the output terminal of the OR circuit and the 3Y terminal of the input circuit unit B40 are the fourth CK terminal and the LOAD terminal of the first to third clock count circuits B81 to B83, respectively. The fourth clock count circuit B84 is connected in the same manner as the clock count circuit B84. Hereinafter, the operation of the other clock count circuits B81 to B83 will be omitted.

  In the circuit configuration as described above, when the clock monitoring circuit B95 does not detect the abnormal operation of the random number clock generation circuit B51 as in FIG. 23, a high signal is output from the 3Y terminal of the input circuit unit B40. The clock count circuit B84 and the random number clock inversion circuit B61 connected to the terminals are in the same operation state as in FIG. Further, since a low signal is output from the output terminal of the inverter (NOT circuit), the output of the OR circuit depends on the output signal of the other input terminal, that is, the random number clock inverting circuit B61. As a result, when the abnormality is not detected by the clock monitoring circuit B95, the same operation as that in FIG. 23 is ensured.

  Next, when the clock monitoring circuit B95 detects an abnormal operation of the random number clock generation circuit B51, an abnormal signal as a low signal is output from the 3Y terminal of the input circuit unit B40 (IC14). Then, the LOAD terminal of the clock count circuit B84 (IC4) connected to the 3Y terminal of the input circuit unit B40 (IC14), the 1CLR terminal of the random number clock inversion circuit B61 (IC18), and the input terminal of the inverter (NOT circuit), respectively. When a low signal is input, the LOAD terminal and 1CLR terminal become valid. That is, a low signal is output from the 1Q terminal of the random number clock inverting circuit B61 (IC18), and the output signal of the OR circuit is supplied from the other input terminal of the OR circuit, that is, the output terminal of the inverter (NOT circuit). It depends on the signal.

  More specifically, when an abnormal signal indicating an abnormality of the random number clock generation circuit B51 is output from the clock monitoring circuit B95 (a low signal is output from the 3Y terminal of the input circuit unit B40 (IC14)), the clock count circuit A high signal including a rising edge is input to the CK terminal of B84 (IC4) via an inverter (NOT circuit) and an OR circuit. Thereby, even if the output from the random number clock generation circuit B51 is a failure in any state (for example, when a high signal or a low signal is continuously output or when an unstable pulse signal is output). The output of the clock count circuit B84 can be changed without depending on the output.

  Here, the IC 4 exemplified in the clock count circuit B84 counts when a rising signal is input to the CK terminal when the LOAD terminal is valid (a state in which a low signal is input). The random number values output from the output units QA to QD terminals are changed to values (default values) input to the input terminals A to D.

  Accordingly, when an abnormal signal indicating abnormality of the random number clock generation circuit B51 is output from the clock monitoring circuit B95, the output from the count output unit (QA to QD terminals) of the clock count circuit B84 is the default value of the clock count circuit B84. That is, the input values of the A to D terminals are output. Here, as shown in FIG. 24, in the present embodiment, since the inputs of the A to D terminals are fixed to the 5V power supply (high signal), they are output during the abnormal operation of the random number clock generation circuit B51. The default value is “1111”. If the default values output from the first to third clock count circuits B81 to B83 (not shown in FIG. 24) are similarly set to “1111”, the random number clock generation circuit as a whole of the clock count circuits B81 to B84 is formed. The count value output during the abnormal operation of B51 is “111111111111111111 (FFFFh)”.

  Under the present embodiment configured as described above, if the hit determination means B37 is set so as not to include FFFFh in the hit random number defined as the random value that generates the jackpot game, the previous embodiment As in the case of the above, no random number is extracted by the symbol lottery means B35 when the random number clock generation circuit B51 operates abnormally. In this embodiment, the random number value output from the first to third clock count circuits B81 to B83 is changed to the default value when the random number clock generation circuit B51 operates abnormally. A random number that can be easily compared on the software can be set as a random number. In other words, the default value should be used when software processing is easier, for example, when it is possible to execute with a small-capacity program including "0" as a random number or to refrain from using a register. By setting to a predetermined random number value (for example, other than “0”) that does not include a hit random number, the above-described effects can be realized by reducing the burden on software.

  In the case where it is not necessary to reduce the burden on software, the random number values counted in the first to fourth clock count circuits B81 to B84 are cleared as in the previous embodiment, so that the previous implementation is performed. The same effect as the example can be obtained.

  Next, the procedure for acquiring and using random numbers in an actual game will be described with reference to the flowcharts of FIGS. In the flowcharts shown in FIGS. 26 and 27, the circled portions D are connected to each other to form one flowchart.

  When the power of the pachinko machine PM is turned on, necessary parameters are initialized, and then the game process is executed according to the main routine shown in FIG. In this main routine, first, the normal game processing subroutine R1 ″ is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine R1 ″, in step S4100, the winning of the hit ball to the first start winning tool 24a and the second start winning tool 24b is checked.

  Here, the detection period of the start signal from the start winning sensors 51 and 52 by the CPU 732 is set to a predetermined period. A winning that is valid only when the start signal is detected to be a low signal in a certain detection cycle, and a high signal is detected twice in succession to the next detection cycle and further to the next detection cycle. Determined.

  In step S4110, it is determined whether or not there is a prize for first start prize-winning tool 24a. If it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S4180 in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there is a winning, the number of reserved balls is incremented by 1, and the process proceeds to step S4120.

  In step S4120 to step S4170, processing corresponding to step S130 to step S180 in the first embodiment is executed, and the process proceeds to step S4175. In step S4175, various software random numbers for use in determining special symbols are acquired and stored in the RAM 734 as well. Then, the process proceeds to step S4180 shown in FIG.

  In step S4180 of FIG. 27, it is determined whether or not there has been a prize for the second starting prize-winning tool 24b. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S4250. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S4190.

  In steps S4190 to S4240, processing corresponding to steps S220 to S270 in the first embodiment is executed.

  In step S4250, various software random numbers for use in determining the special symbol are acquired and stored in the RAM 734 as well. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 25, a random number monitoring process subroutine R2 ″ is executed according to the flowchart shown in FIG.

  In the random number monitoring processing subroutine R2 ″, first, in step S4300 in FIG. 28, the control unit 740 determines whether an abnormal signal is output from the input circuit unit B40. If it is determined that an abnormal signal is output, the control unit 740 outputs a notification signal to the error display device 61 to display an error in step S4310. The notification signal is transmitted to the management computer installed in the game hall via the external terminal board 600, and this abnormality is immediately recognized on the game hall side.

  On the other hand, if it is determined in step S4300 that no abnormal signal has been output, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 25, a symbol variation processing subroutine R3 ″ is then executed according to the flowchart shown in FIG. In the symbol variation processing subroutine R3 ″, processing similar to that shown in FIG. 12 in the first embodiment is executed. In step S4450, the type of special symbol is determined according to the presence or absence of winning using the software random number acquired in step S4250 of the previous normal game processing subroutine R1 ″, and the special symbol is finally determined. The symbol display device 28 on the game board 20 executes the variable display as shown in FIG. Then, the process returns to the main routine shown in FIG.

  Next, in the main routine shown in FIG. 25, a special game processing subroutine R4 ″ is executed. In the special game processing subroutine R4 ″, when the special game flag is set in step S4440 of the previous symbol variation processing subroutine R3 ″, a special game, that is, a jackpot game is executed. Then, after the jackpot game is over, the special game flag is cleared and then the process returns to the main routine. On the other hand, if the special game flag is not set, the process immediately returns to the main routine.

  In the main routine, the game is continued by repeating the above-described subroutines R1 ″ to R4 ″.

  Here, the effects achieved in the present invention are summarized as follows. In the gaming machine according to the present invention, the pulse oscillation detecting means monitors whether or not an abnormal operation has occurred in the random number clock generating means during the operation of the random number generating unit mounted on the gaming machine. When an abnormal operation of the random number clock generation means occurs, the pulse oscillation detection means immediately detects the abnormal operation of the random number clock generation means, and the abnormal signal output means outputs an abnormal signal and notifies that fact. It is supposed to be. Further, the special game regulation means provided in the gaming machine is configured to regulate a special game that gives a profit to the player based on the detection of the abnormal signal.

  Therefore, the abnormal operation of the random number clock generation means can be detected immediately, and a winning random number that is advantageous to the player is not extracted, so that it is possible for the game hall without noticing the malfunction of the clock generation means. Unfavorable games are not continued (so-called “big hit games” are not continued), and damage to the game hall can be prevented. When an abnormal operation of the random number clock generating means occurs, a notification signal is output and the occurrence of the abnormal operation is immediately displayed by the error display device, so the game hall side recognizes this abnormal operation early. Is possible.

  The special game regulation means can regulate the special game by various methods. In other words, without restricting the special game by determining that it is a random number value lost in the hit determining means based on the detection of the abnormal signal, or without determining whether the hit determining means is a hit random number No special game is generated, or the random number extraction means performs the count value extraction regardless of the occurrence of abnormal operation in the random number clock generation means, but if an abnormal signal is detected, the special game is It is possible to prevent damage on the game hall side by several methods such as preventing it from occurring.

  In addition, a random number change circuit is provided to change the count value output from the random number counting means based on the abnormal signal or the count value stored in the random number storage means to a random number that is disadvantageous to the player, and an abnormal signal is output. During this time, it is possible to prevent damage on the game hall side by a method in which the lost random number is output from the random number counting means or the random number storage means.

  Further, the gaming machine according to the present invention checks whether or not a pulse signal is output from the random number clock generation means, and includes a pulse oscillation detection means for causing the abnormal signal output means to output an abnormal signal, a diode, a transistor It is possible to configure with only inexpensive parts such as capacitors.

  Although the preferred embodiments of the present invention have been described so far, the scope of the present invention is not limited to the above-described embodiments. For example, if it is determined by the control unit 740 that an abnormal signal is output from the input circuit unit B40, even if a predetermined winning symbol is stopped and displayed on the symbol display device 28, the control is performed. By controlling the unit 740 so as not to open the big prize device 26, it is possible to restrict the occurrence of a “hit game” advantageous to the player. By performing such control, if an abnormality is detected, even if the winning symbol is stopped and displayed, it does not shift to a special game, so the occurrence of an abnormality in the gaming machine is recognized from the outside. Is possible.

  In addition, when the control unit 740 determines that an abnormal signal is output from the input circuit unit B40, even if the special prize process 26 is released and the special game is executed in the special game process, it is opened again. It is also possible not to count the winnings to a predetermined number of big winning tools 26 for the purpose. This is because the control unit 740 prevents the winning sensor provided in the hitting ball flow path in the winning tool 26 from detecting the winning of the hitting ball on the winning tool 26 from detecting the winning of the hitting ball to the winning tool 26. It can be realized by controlling. By performing such control, when an abnormality is detected, it is possible to recognize the occurrence of the abnormality of the gaming machine from the outside when the special game is executed.

  Furthermore, in the above embodiment, a gaming machine equipped with a random number generator has been described taking the pachinko machine PM as an example, but the pachinko machine PM is an example of a gaming machine, and the gaming machine is not limited to a pachinko machine. It may be a slot machine. In this case, the symbol display device that displays a plurality of types of symbols based on the extraction result by the random number extraction means is constituted by, for example, a spinning reel device having a plurality of spinning reels that can be rotated by a motor drive. .

It is a front view of the game board of the gaming machine according to the present invention. It is a rear view showing the internal structure of the gaming machine according to the present invention. It is a block diagram showing the outline of the control system provided in the said gaming machine. It is a block diagram showing the part concerning control of the gaming machine provided in the gaming machine and the part concerning generation of random numbers. It is a circuit diagram showing the random number generation part and its periphery in the said gaming machine. It is an enlarged view of a clock monitoring circuit in the random number generator. It is the figure which showed the signal produced | generated in the said random number generation part with the timing chart. It is the figure which showed the signal produced | generated in the said random number generation part with the timing chart. It is the figure which showed the main routine in the procedure of the acquisition of the design lottery random number of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed the symbol fluctuation process subroutine in the procedure of the acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the procedure of abnormality detection of a random number generation part. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed the symbol fluctuation process subroutine in the procedure of the acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the procedure of abnormality detection of a random number generation part. It is the figure which showed the main routine in the procedure of the acquisition of the design lottery random number of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the abnormality detection of a random number generation part. It is the figure which showed the symbol fluctuation process subroutine in the procedure of the acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the procedure of abnormality detection of a random number generation part. It is the figure which showed the special game transfer processing subroutine in the procedure of the acquisition of the design lottery random number of the above-mentioned game machine, utilization and the procedure of abnormality detection of the random number generation section. It is the figure which showed the symbol fluctuation process subroutine in the procedure of the acquisition of the random number for symbol drawing of the said gaming machine, utilization, and the procedure of abnormality detection of a random number generation part. It is the figure which showed the special game transfer processing subroutine in the procedure of the acquisition of the design lottery random number of the above-mentioned game machine, utilization and the procedure of abnormality detection of the random number generation section. It is a circuit diagram showing the random number generation part and its periphery in the said gaming machine. It is a figure which extracts and shows a part of circuit diagrams, such as a random number generation part, as one Example of the random number change circuit provided in the random number generation part. It is the figure which showed the main routine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed the random number monitoring process subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine. It is the figure which showed the symbol fluctuation process subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said gaming machine.

Explanation of symbols

PM Pachinko machine (game machine)
1 outer frame 2 front frame 20 game board 28 design display device 732 CPU (random number extraction means, special game regulation means)
740 Control unit (notification signal output means)
750 Random number generator B35 Symbol lottery means (random number extraction means)
B37 hit determination means B38 hit determination table B40 input circuit section (abnormal signal output means)
B51 Random number clock generation circuit (random number clock generation means)
B81 First clock count circuit (random number counting means)
B82 Second clock count circuit (random number counting means)
B83 Third clock count circuit (random number counting means)
B84 Fourth clock count circuit (random number counting means)
B91 First count value storage circuit B92 Second count value storage circuit B95 Clock monitoring circuit (pulse oscillation detection means)
B96 Smoothing circuit part B97 Random number change circuit E Power supply TR1 Transistor

Claims (7)

A random number clock generating means for generating a clock at a predetermined frequency; a random number counting means for counting a random number value based on a clock generated by the random number clock generating means; and the random value counted by the random number counting means. Random number extracting means for extracting and outputting one count value at a predetermined timing, and a predetermined perturbation for generating a special game that gives a profit to the player and the count value output from the random number extracting means A hit determination means for comparing the numerical value with each other to determine whether or not the count value is the winning random number value; and when the hit determining means determines that the count value is the winning random number value, The winning symbol is displayed, and when it is determined that the winning random number is not the predetermined random symbol, the predetermined losing symbol is displayed in a visible manner. In the gaming machine composed of a pattern display means,
Pulse oscillation detection means for detecting whether or not the input signal from the random number clock generation means is a pulse signal output at a predetermined period by a normal operation of the random number clock generation means;
An abnormal signal that outputs an abnormal signal indicating the occurrence of an abnormal operation of the random number clock generating means when it is detected that the input signal from the random number clock generating means is not a pulse signal due to a normal operation of the random number clock generating means Output means;
A gaming machine comprising: special game regulation means for regulating the special game based on detection of the abnormal signal.   The special game restricting means is determined by the hit determining means based on the detection of the abnormal signal as the count value is a predetermined random number value for displaying the predetermined lost symbol in the symbol display means. 2. The gaming machine according to claim 1, wherein the count value input to the hit determination means is changed.   The said special game regulation means displays the said predetermined lose symbol in the said symbol display means based on the detection of the said abnormal signal, without performing determination by the said hit determination means. Gaming machine.   The special game regulation means prohibits the transition to the special game even though the count value is determined to be the winning random number value by the hit determination means based on the detection of the abnormal signal. The gaming machine according to claim 1, wherein the gaming machine is characterized.   The pulse oscillation detection means includes a smoothing circuit section that smoothes a pulse signal generated by normal operation of the random number clock generation means and always outputs a predetermined voltage or more, and an on / off operation according to a voltage load from the smoothing circuit section. The gaming machine according to claim 1, further comprising: a power source connected to the pulse oscillation detection unit and the abnormal signal output unit, and a transistor for cutting off or conducting the pulse oscillation detection unit. When the input signal from the random number clock generating means is a pulse signal due to the normal operation of the random number clock generating means, the transistor is turned on by the voltage load from the smoothing circuit section, and the current from the power source is Flows to the side of the pulse oscillation detection means,
When the input signal from the random number clock generation means is not a pulse signal due to the normal operation of the random number clock generation means, the power supply and the pulse oscillation detection means are cut off by the turning off of the transistor, so that the power supply The gaming machine according to claim 5, wherein the current flows to the abnormal signal output means side and an abnormal signal is output from the abnormal signal output means.   The system further comprises a notification signal output means for outputting a notification signal for performing a predetermined notification indicating an abnormal operation of the random number clock generation means when the abnormality signal is output by the abnormality signal output means. The gaming machine according to 1-6.

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