JP4575348B2 - Packet error measuring device - Google Patents

Description

  The present invention relates to a technique for reliably measuring an error of a packet transmitted with a pseudo-random signal inserted in a payload portion.

  In order to test a network that transmits packet signals, a test packet in which a pseudo-random signal represented by a generator polynomial of a predetermined order N is inserted in a payload portion is sent to a specific address via a device or network to be tested Transmitting and measuring the error of the signal inserted in the payload portion of the packet signal received by the terminal at that address.

If the data sequence of the pseudo-random signal inserted into the payload portion of the test packet is the same every time and is known, error measurement can be correctly performed by comparing the known data with the received data on the receiving side. However, when the length of the payload portion is shorter than the code length (2 ^N −1) of the pseudo random signal, the randomness is lost, so that the data sequence of the pseudo random signal is different for each packet. In this case, a so-called synchronization determination process is required in which a correct data string serving as a reference for comparison is obtained from received data, and a subsequent reference signal is generated based on the data string.

  That is, on the receiving side, a reference signal generator including an N-stage shift register circuit and an EXOR (exclusive OR) circuit according to an N-th generation polynomial is provided, and an initial stage of the N-stage shift register circuit is provided. The data to be measured is taken as N bits from the beginning as a value, and thereafter, the reference signal generated and output from the reference signal generator according to the generator polynomial is compared with the data after the N + 1 bits of the measurement object in bit units, Error measurement is performed by assuming that synchronization is confirmed when no error occurs continuously for N bits, and that a reference signal generated thereafter is correct.

  A technique for performing error measurement after the synchronization is determined as described above is disclosed, for example, in Patent Document 1 below.

Japanese Patent No. 2899869

  In the process up to the above confirmation of synchronization, if an error is included in the initial N-bit data taken as an initial value, even if there is no error in the subsequent data, the comparison result is highly inconsistent, and the subsequent error Measurement cannot be performed correctly.

  Therefore, the data fetching process is performed again, bit comparisons for N bits are performed, and it is determined that synchronization has been confirmed when N bits are continuously matched, and error measurement for subsequent data is started.

  Therefore, the data input until the synchronization is determined becomes invalid, and no error measurement is performed on the data, so that the number of errors for all the bits of the payload portion cannot be obtained accurately.

  The present invention solves this problem and provides a packet error measuring device that can accurately determine an error in a signal inserted in a payload portion of a packet, including data input until synchronization is determined. It is aimed.

In order to achieve the above object, the packet error measurement device of the present invention comprises:
A payload detector (21) that receives a packet signal transmitted by inserting a pseudo-random signal generated in accordance with an Nth generation polynomial into the payload portion and detects data in the payload portion of the packet signal;
A forward reference signal generator (22) that takes data detected by the payload detector in N-bit units in the order of input, uses the fetched N-bit data as an initial value, and generates a reference signal in the forward direction according to the generator polynomial. )When,
A forward comparison unit (27) for comparing a reference signal output from the forward reference signal generation unit with data following the N-bit data captured as the initial value;
A backward reference signal generator (30) for taking N-bit data taken as an initial value in the forward reference signal generator as an initial value, and generating a reference signal in the backward direction according to the generator polynomial;
A data storage unit (35) for storing data detected by the payload detection unit in the order of input;
The previous data of the N-bit data taken-as the initial value is read out in the order of incorporation opposite from said data storage unit, the reverse direction comparing unit for reference signal and comparison output from the backward reference signal generator ( 36)
It said forward reference signal generating portion and the backward reference until a match determination consecutively N bits Ru are output in the forward direction comparing unit from the new N-bit data in the forward direction reference signal generating section is initialized N-bit data initially set in the signal generation unit is updated, and when the coincidence determination continues for N bits, it is initialized in the forward reference signal generation unit and the reverse reference signal generation unit as being determined to be synchronized. A control unit (40) that regulates updating of N-bit data and continuously outputs a reference signal ;
An arithmetic processing unit (45) that performs an error operation on all data in the payload portion of the packet, using the comparison results of the forward comparison unit and the backward comparison unit after the synchronization is determined as an effective error determination result; ,
While performing forward error determination processing on data input after the synchronization is determined, backward error determination processing is performed in parallel on data input before synchronization determination .

  As described above, in the packet error measurement device of the present invention, the comparison result between the reference signal output in the forward direction from the forward reference signal generation unit and the data in the payload is equal to N bits continuously in the forward comparison unit. After the synchronization is confirmed, the comparison result of the forward comparison unit is set as an effective determination result, and the backward reference signal generation unit is used in the backward comparison unit for the data input until the synchronization is confirmed. Is compared with a reference signal generated in the reverse direction, and this is used as an effective determination result, so that it is possible to accurately determine an error for all data in the payload portion.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a packet error measuring apparatus 20 to which the present invention is applied.

  The payload detection unit 21 of the packet error measuring device 20 receives a packet signal P transmitted by inserting a pseudo-random signal of an Nth order generation polynomial into the payload unit, and detects data D of the payload unit from the packet signal P Then, the information is output in the order of input, and information such as the data length of the payload portion is notified to the control portion 40 described later.

  The data D is output to the forward reference signal generator 22, the backward reference signal generator 30, and the data storage unit 35.

  The forward reference signal generation unit 22 takes in the data D detected by the payload detection unit 21 in N-bit units in the order of input in accordance with an instruction from the control unit 40 to be described later, and sets the taken N-bit data as an initial value. A reference signal Rf is generated in the forward direction in accordance with the Nth order generator polynomial.

  Here, the forward reference signal generator 22 is configured, for example, as shown in FIG. 2 so that the data D detected by the payload detector 21 can be processed continuously and in real time.

That is, when the Nth-order generation polynomial is, for example, 1 + x ¹⁸ + x ²³ (N = 23), the input data is sequentially synchronized with the shift clock C so that the reference signal (pseudo-random signal) can be generated according to the generation polynomial. Two 23-stage shift registers 23a and 23b that shift to the subsequent stage, and EXOR circuits 24a and 24b that obtain exclusive OR of the outputs of the final stage and a predetermined stage (in this example, 18 stages) and feed back to the first stage, , Switches 25a and 25b for initial data fetching, and a data selector 26 for selectively outputting one of the outputs fed back to the first stage of the shift registers 23a and 23b.

  The switches 25a and 25b are controlled by the control unit 40, and sequentially receive the data D output from the payload detection unit 21 from the first stage of the shift registers 23a and 23b when initial data is fetched, and an EXOR circuit instead of the data D when a reference signal is generated The outputs of 24a and 24b are input to the first stage of the shift registers 23a and 23b.

  Until the synchronization is established, the data D output from the payload detector 21 is alternately set in the two shift registers 23a and 23b in units of 23 bits. Of the shift registers 23a and 23b, the output signal that has not received the initial data is selected.

  The reference signal Rf output from the forward reference signal generation unit 22 configured in this way is input to the forward comparison unit 27, and is finally captured by the forward reference signal generation unit 22 as an initial value. It is compared bit by bit with the data that follows the data.

  On the other hand, the backward reference signal generator 30 takes N-bit data taken as an initial value by the forward reference signal generator 22 as an initial value, and generates a reference signal Rr in the backward direction according to the generator polynomial.

In the case where the generating polynomial is 1 + x ¹⁸ + x ²³ (N = 23), the backward reference signal generator 30 has 23 stages for shifting the input data to the subsequent stage in synchronization with the shift clock C as shown in FIG. The shift register 31, a 23-stage shift register 32 that receives the instruction from the control unit 40 and stores the output value of each stage of the shift register 31 as an initial value in reverse order, the final stage of the shift register 32, and a predetermined stage The exclusive OR of the outputs of the outputs (23-18 = 5th stage in this example) is constituted by the EXOR circuit 33 that feeds back to the first stage, and the signal fed back to the first stage of the shift register 32 is the reference signal in the reverse direction. Output as Rr.

  In the forward reference signal generator 22 described above, N-bit data is initialized in parallel (but in the forward direction) in parallel with the two shift registers 23a and 23b, similarly to the backward reference signal generator 30. May be adopted.

  The data storage unit 35 stores data from the beginning of the data D output from the payload detection unit 21 to the data that is finally taken in as an initial value in the backward reference signal generation unit 30.

  The backward comparison unit 36 receives the reference signal Rr output from the backward reference signal generation unit 30 and the data before the N-bit data initially set in the backward reference signal generation unit 30 as the data storage unit 35. Are read and compared in the reverse order of input.

  When the control unit 40 receives the information from the payload detection unit 21, the forward direction reference signal generation unit 22 and the backward direction reference signal generation unit 30 until the forward comparison unit 27 outputs a match determination continuously for N bits. The N-bit data that is initially set is updated to notify the arithmetic processing unit 45 that the synchronization has been established.

  The arithmetic processing unit 45 uses the comparison results output from the forward comparison unit 27 and the backward comparison unit 36 after the synchronization is determined as an effective error determination result, and performs error calculation on all data in the payload portion of the input packet P. .

Next, the operation of the packet error measuring apparatus 20 configured as described above will be described with reference to FIG.
For example, when the data D shown in (a) of FIG. 4 is output from the payload detection unit 21, the data d (1) to d (N) from the first bit to the Nth bit according to the instruction of the control unit 40 As shown in FIG. 4B, the Nth-order generator polynomial is initialized in one shift register 23a of the forward reference signal generator 22, and then the data d (1) to d (N) are used as initial values. , The next reference signals r (N + 1), r (N + 2),... Are sequentially output in the forward direction, and are compared with the next N-bit data d (N + 1), d (N + 2),. Is done.

  Further, the N-bit data d (N + 1) to d (2N) are taken into the other shift register 23b of the forward reference signal generator 22, as shown in FIG. As forward reference signals r (2N + 1), r (2N + 2),... Are sequentially output and compared with the next N-bit data d (2N + 1), d (2N + 2),.

  Hereinafter, the data detected from the payload portion is alternately fetched into the two shift registers 23a and 23b in units of N bits, and the forward reference signal Rf having the initial value is output, and the fetched N bits It will be compared with the data that follows the data. This process is repeated until the N-bit data is initially set and the forward comparison unit 27 determines that N bits are continuously matched, that is, until synchronization is determined.

  In the operation example of FIG. 4, the reference signals r (4N + 1) to r (5N) generated in the forward direction with the N-bit data d (3N + 1) to d (4N) taken in the fourth time as initial values and the next N-bit data This is a case where d (4N + 1) to d (5N) coincide with all bits and a synchronization confirmation signal as shown in (d) of FIG. 4 is output to the arithmetic processing unit 45. Thereafter, the initial data is updated. The reference signal switching process is not performed, and the subsequent reference signal is continuously generated on the shift register side that has output the reference signal when synchronization is determined, and the comparison result of the forward comparison unit 27 for the reference signal is An error rate calculation process is performed by the calculation processing unit 45 as an effective determination result for data d (5N + 1) and thereafter.

  On the other hand, as shown in (e) and (f) of FIG. 4, the N-bit data captured by the forward signal generator 22 is sequentially input to the backward reference signal generator 30 and the data storage unit 35. Until the synchronization is determined, the output and the comparison result of the backward direction comparison unit 36 are ignored, and N-bit data (in this example, d (4N + 1) ˜) taken into the backward direction reference signal generation unit 30 when the synchronization is determined. The reference signals r (4N), r (4N−1),... generated in the reverse direction with d (5N) (which may be N-bit data before that) may be the initial value to the reverse direction comparison unit 36. Output as a valid signal.

  When the synchronization is confirmed, the backward direction comparing unit 36, as shown in FIG. 4 (f), data d N bits before the last data (in this case d (5N)) stored in the data storage unit 35. Read in the reverse direction from (4N) to the leading data d (1) and compare with the reference signal Rr.

  The comparison result of the backward comparison unit 36 is input to the arithmetic processing unit 45 as a correct bit error result for the data D input until the synchronization is determined, and is subjected to arithmetic processing.

  The arithmetic processing unit 45 compares the comparison result output after the synchronization is determined from the forward comparison unit 27 for the data after the data d (5N + 1) and the data before the data d (4N) among all the data from the first bit to the last bit of the payload portion. Based on the comparison result output after the synchronization is determined from the backward comparison unit 36, the number of errors for all bits is obtained, and the error rate E is calculated.

  Note that there is no error in principle for the N-bit data d (4N + 1) to d (5N) fetched when the synchronization is confirmed in the above example, so the error calculation includes the N bits without the error. To do.

  In the above embodiment, the N-bit data is fetched as an initial value until synchronization is confirmed. However, the number of times of fetching is limited to a predetermined number of times (for example, twice), and the synchronization is not confirmed after the predetermined number of times of fetching. May discard the packet itself as being abnormal and perform error measurement processing on the next packet.

  Further, in the above-described embodiment, two shift registers 23a are used to cause the forward reference signal generation unit 22 to continuously generate the reference signal so that the data detected from the payload portion can be continuously captured by N bits. 23b are provided so that they are alternately fetched. However, it is not necessary to fetch N-bit data continuously until synchronization is established, and only one shift register is used, for example, data d (1) to d (N), d (2N + 1) to d (3N),...

Configuration diagram of an embodiment of the present invention The figure which shows the structural example of the forward direction reference signal generation part of embodiment. The figure which shows the structural example of the reverse direction reference signal generation part of embodiment. Operation explanatory diagram of the embodiment

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... Packet error measuring device, 21 ... Payload detection part, 22 ... Forward direction reference signal generation part, 27 ... Forward direction comparison part, 30 ... Reverse direction reference signal generation part, 35 ... Data storage part, 36 …… Reverse direction comparison unit, 40 …… Control unit, 45 …… Calculation processing unit

Claims (1)

A payload detector (21) that receives a packet signal transmitted by inserting a pseudo-random signal generated in accordance with an Nth generation polynomial into the payload portion and detects data in the payload portion of the packet signal;
A forward reference signal generator (22) that takes data detected by the payload detector in N-bit units in the order of input, uses the fetched N-bit data as an initial value, and generates a reference signal in the forward direction according to the generator polynomial. )When,
A forward comparison unit (27) for comparing a reference signal output from the forward reference signal generation unit with data following the N-bit data captured as the initial value;
A backward reference signal generator (30) for taking N-bit data taken as an initial value in the forward reference signal generator as an initial value, and generating a reference signal in the backward direction according to the generator polynomial;
A data storage unit (35) for storing data detected by the payload detection unit in the order of input;
The previous data of the N-bit data taken-as the initial value is read out in the order of incorporation opposite from said data storage unit, the reverse direction comparing unit for reference signal and comparison output from the backward reference signal generator ( 36)
It said forward reference signal generating portion and the backward reference until a match determination consecutively N bits Ru are output in the forward direction comparing unit from the new N-bit data in the forward direction reference signal generating section is initialized N-bit data initially set in the signal generation unit is updated, and when the coincidence determination continues for N bits, it is initialized in the forward reference signal generation unit and the reverse reference signal generation unit as being determined to be synchronized. A control unit (40) that regulates updating of N-bit data and continuously outputs a reference signal ;
An arithmetic processing unit (45) that performs an error operation on all data in the payload portion of the packet, using the comparison results of the forward comparison unit and the backward comparison unit after the synchronization is determined as an effective error determination result; ,
A packet error measurement apparatus, wherein a forward error determination process is performed on data input after the synchronization is confirmed, and a reverse error determination process is performed on data input before the synchronization is confirmed .

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