KR100735567B1 - Method and apparatus for io test of semiconductor device - Google Patents

Abstract

A method and a device for testing input/output of a semiconductor device are provided to carry out an input/output test of the semiconductor device in a loop back test method by using test data, thereby excluding a complex logic for aligning phases. A method for generating test data for testing input/output of a semiconductor device is composed of steps for aligning plural parallel data(501,510,520,530) of N bits in series by inputting or outputting the data in advance; generating the N number of parity codes(540) for the parallel data of N bits in a direction of a time axis; and serially aligning the N number of parity codes generated after serialized data(511,521,531). Each parallel data of N bits is pseudo random data and the size of the N number of parity codes corresponds to one bit.

Description

I / O test method and device for semiconductor device {Method and apparatus for IO test of semiconductor device}

1 is a diagram illustrating a serial communication environment of a semiconductor device.

2 is a waveform diagram illustrating a conventional test data generation process.

3 is a waveform diagram illustrating a case where phases are well aligned at a receiving side.

4 is a waveform diagram illustrating a case in which phases are misaligned at a receiving side.

5 is a waveform diagram illustrating a test data generation process in an input / output test according to an embodiment of the present invention.

6 is a waveform diagram illustrating a case where phase alignment is misaligned in an input / output test according to an embodiment of the present invention.

7 is a block diagram illustrating a semiconductor device including an input / output tester according to an embodiment of the present invention.

8 is a circuit diagram illustrating a CRC generator for explaining a CRC generation and check process according to an embodiment of the present invention.

9 is a block diagram illustrating a serialization process according to an embodiment of the present invention.

The present invention relates to an input / output test of a semiconductor device, and more particularly, to an input / output test and a test data generation for an input / output test of a semiconductor device that transmits and receives data in series.

Data transfer rates between semiconductor chips are getting faster. As the data transmission speed increases, signal interference between transmission lines increases. Therefore, a parallel data communication method that requires many transmission lines for data transmission is not suitable for high speed data transmission between semiconductor chips.

Recently, serial communication schemes have been studied for high speed data transfer between semiconductor chips. In a serial communication method, a semiconductor chip serializes parallel data therein and transmits the serialized data to another chip. Various schemes have been proposed for detecting errors that may occur in high speed data transmission. For example, the transmitting apparatus transmits the data to be transmitted by attaching surplus data such as a parity code or CRC code, and the receiving apparatus transmits data through parity check or CRC check on the received data including the parity code or CRC code. Determine if an error occurred in the process.

1 is a diagram illustrating a serial communication environment of a semiconductor device.

The transmitter 110 includes a core circuit 111, a serializer 112, a CRC calculator 113, and a transmitter 114, and the receiver 120 includes a core circuit 124 and a parallelizer 122. It includes a CRC checker 123, a phase aligner 121, and a receiver 121. In a communication between two semiconductor chips, a transmitting device 110 may be included in a first semiconductor chip and a receiving device 121 may be included in a second semiconductor chip. In addition, both the first semiconductor chip and the second semiconductor chip may include a transmission and reception device for transmission and reception.

The transmitter 110 provides the parallel data provided by the core circuit 111 to the serializer 112 and the CRC calculator 113. The CRC calculator 113 calculates a parity code for parallel data. The serializer 112 serializes the parallel data and the parity code. The transmitter 114 transmits serial data. For example, when the parallel data is 8-bit parallel data, the parity code may be 2-bit parallel data.

The receiving device 120 receives serial data transmitted through the receiving unit 121. Serial data is parallelized through the parallelizing unit 122. The parallelizer 122 provides the parallelized data to the CRC checker 123. The CRC checker 123 checks whether an error has occurred in the parallelized data. The parallelization unit 122 provides parallel data excluding the parity code to the core 124 when no error occurs in the parallelized data. For example, when the parallelized data is 10-bit parallel data, the parallel data without the parity code may be 8-bit qdufuf data.

The phase aligner 125 determines the phase of the received serial data and the sampling clock. That is, the phase determiner 125 determines a sampling start time of the received data. The receiving device 120 may determine whether an error occurs in the received data if the sampling starts at the correct position, but cannot determine whether an error occurs if the sampling starts at the incorrect position.

A test data generation process for checking whether an input / output error has occurred in such a conventional communication environment, and a case where phases are well aligned and incorrectly aligned at a receiving side will be described with reference to FIGS. 2 to 4. For convenience of description, a description will be given based on a case of generating 10-bit test data including a 2-bit parity code for 8-bit parallel data.

Referring to FIG. 2, the test data generator generates first to third parity codes 211, 221, and 231 for the first to third parallel data 210, 220, and 230. Then, the first parallel data 210, the first parity code 211, the second parallel data 220, the second parity code 221, the third parallel data 230, and the third parity code 231 are ordered. Serialize to The first to third serial test data 212, 222, and 232 for the first to third parallel data 210, 220, and 230 are transmitted to the receiving device.

Referring to FIG. 3, the receiving device receives first to third serial test data 212, 222, and 232. The sampling start point is where the first serial test data begins. When the sampling start time point is exactly aligned with the position at which the first serial test data 212 that is valid data starts, the receiving device parallelizes the first to third serial test data 212, 222, and 232 to obtain the correct first data. The first to third parallel test data 310, 320, 330 may be generated. When no data transmission error occurs, no CRC error is generated for the first to third parallel test data 310, 320, and 330. However, a CRC error occurs when a data transmission error occurs. Therefore, the receiving device may determine whether a data transmission error occurs.

Referring to FIG. 4, the receiving device receives first to third serial test data 212, 222, and 232. If the sampling start time point is not exactly aligned with the position where the first serial test data 212, which is valid data, is started, the receiving device parallelizes the first to third serial test data 212, 222, and 232 to correct it. It is not possible to generate the first to third parallel test data 310, 320, 330. Even when no error occurs during the transmission process, CRC errors for the first to third parallel test data 310, 320, and 330 are generated. Therefore, the receiving device cannot determine whether a data transmission error occurs.

Typically, microprocessors or controllers contain blocks for phase alignment. The phase aligner 125 included in the receiving device 120 of FIG. 1 accurately aligns the sampling start time point with the position where the first serial test data 212 starts. As such, the semiconductor device including the phase alignment unit may perform an input / output test in a loopback test method.

The loopback test is performed as follows. The semiconductor device generates test data and outputs the generated test data to a transmission path. The semiconductor device receives test data transmitted through the transmission path and checks whether an error occurs with respect to the input test data. This loopback test is a very inexpensive test method and is useful for reducing the test cost of semiconductor devices. However, DRAM or flash memory does not include such phase alignment. As described above, input / output tests may not be performed on a semiconductor device that does not include a phase alignment unit using an inexpensive loopback test.

Therefore, there is a need for a test data generation method and an input / output test method of a semiconductor device that can perform a loopback test on the semiconductor device without including a separate complicated logic circuit such as a phase alignment unit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a test data generation method for performing an input / output test of a semiconductor device without a phase alignment process.

Another object of the present invention is to provide a method for testing input and output of a semiconductor device without a phase alignment process.

Another object of the present invention is to provide a test data generator for performing an input / output test of a semiconductor device without a phase alignment process.

Another object of the present invention is to provide a test apparatus for testing input and output of a semiconductor device without a phase alignment process.

However, the above objects are exemplary and the present invention is not limited thereto.

In order to achieve the above object, a test data generation method for an input / output test of a semiconductor device according to an embodiment of the present invention comprises the steps of serializing a plurality of N-bit parallel data on a first-in, first-out basis; Generating N parity codes in the time axis direction with respect to the time axis, and serializing the N parity codes following the serialized data. Each of the N bit parallel data may be pseudo random data. The N parity codes may have a 1 bit size.

In order to achieve the above object, the input and output test method of a semiconductor device according to an embodiment of the present invention comprises the steps of generating serial test data from a plurality of N-bit parallel data, and outputs the serial test data to an external transmission line And receiving the serial test data transmitted through the external transmission line, and checking whether an input / output error occurs based on the serial test data.

The generating of the serial test data may include serializing the N bit parallel data on a first in, first out basis, generating N parity codes in a time axis direction with respect to the N bit parallel data, and generating the N parity codes. And serializing the serialized data. Each of the N bit parallel data may be pseudo random data. The N parity codes may have a 1 bit size.

The checking of whether an input / output error occurs may include: parallelizing the serial test data and checking parity of at least one test bit string among N test bit strings in a time axis direction included in the parallelized test data. This includes steps.

In order to achieve the above object, a test data generator for input / output testing of a semiconductor device according to an embodiment of the present invention is a data provider for providing a plurality of N-bit parallel data, and a time axis for the N-bit parallel data A parity code generator for generating N parity codes in a direction, and a serializer for serializing the N bit parallel data by first-in first-out, and then serializing the N parity codes.

Each of the N bit parallel data provided by the data provider may be pseudo random data. The N parity codes may have a 1 bit size.

In order to achieve the above object, a test apparatus for input and output testing of a semiconductor device according to an embodiment of the present invention includes a test data generator for generating serial test data based on a plurality of N-bit parallel data, the serial test An output unit for outputting data to an external transmission line, an input unit for receiving the serial test data transmitted through the external transmission line, and an input / output error detector for checking whether an input / output error occurs based on the serial test data. .

The test data generator includes a data provider for providing the plurality of N-bit parallel data, a parity code generator for generating N parity codes in a time axis direction with respect to the N-bit parallel data, and the N-bit parallel data. And serialize first-in-first-out, and then serialize the N parity codes.

Each of the N bit parallel data provided by the data provider may be pseudo random data. The N parity codes may have a 1 bit size.

The input / output error detector may include a parallelizer configured to parallelize the serial test data, and a parity checker configured to check parity of at least one test bitstream among N test bitstreams in a time axis direction included in the parallelized test data. Include.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, the same reference numerals are used for the same components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

5 is a waveform diagram illustrating a test data generation process in an input / output test according to an embodiment of the present invention. For convenience of description, each data is 8-bit parallel data, and each parity code will be described on the basis of 1-bit odd or even parity bit.

Referring to FIG. 5, the input / output test apparatus generates parity codes 540 in a time axis (horizontal) direction with respect to the plurality of parallel data 501. In other words, the input / output test apparatus does not generate a parity code for each of the first to third parallel data 510, 520, and 530, but instead generates eight parity codes 540 in the time axis direction. In more detail, the I / O test apparatus generates a parity code 0 for MSB bits (bits 0) of the first to third parallel data 510, 520, and 530, and generates a parity code for the first bit. Create (1). Similarly, the input / output test apparatus generates codes 2 to 7 for bits 2 to 7 of the first to third parallel data 510, 520, and 530.

The input / output test apparatus serializes the first parallel data 510 inputted first to the first to third parallel data 510, 520, and 530, serializes the second parallel data 520 next, and finally The third parallel data 530 is serialized. The input / output test apparatus then serializes the parity codes 540.

As a result, the input / output test apparatus performs the first serial data 511 and the second serial data 521, the third serial data 531, and the serial parity code with respect to the first to third parallel data 510, 520, and 530. Generate serial test data 502 including column 541.

6 is a waveform diagram illustrating a case where phase alignment is misaligned in an input / output test according to an embodiment of the present invention.

The input / output test apparatus receives serial test data 502 through a transmission line. The received serial test data 502 includes a first serial data 511, a second serial data 521, a third serial data 531, and a serial parity code string 541.

The input / output test apparatus parallelizes the serial test data 502 in 8-bit units. The parallelized test data is well aligned in the time axis direction even when the sampling start position is not aligned with the 0 bit of the first serial data 511. The input / output test apparatus determines whether an input / output error occurs by performing parity check on at least one test bit string among the eight test bit strings in the time axis direction.

Hereinafter, a semiconductor device including an input / output tester for generating test data in the time axis direction and detecting an input / output error will be described.

7 is a block diagram illustrating a semiconductor device including an input / output tester according to an embodiment of the present invention.

The semiconductor device 700 includes a memory core 710, an input / output controller 720, a CRC calculator 730, a serializer 731, a parallelizer 741, a transmitter 732, and a receiver 742 that perform memory operations. ), A CRC checker 740, a test mode controller 750, and a command register 760.

The memory core 710 includes a cell array for storing data and a decoder for writing data to or outputting data stored in the cell array.

The input / output controller 720 performs input control of data to be recorded in the memory core 710 and output control of data output from the memory core 710.

The test mode controller 750 controls the semiconductor device to operate the semiconductor device 700 in the test mode. The test mode controller 750 is activated when the command value stored in the command register 760 of the semiconductor device means performing the test mode, and is deactivated in the normal mode. The test mode controller 750 provides a plurality of N (N is a natural number of two or more) bit parallel data for the input / output test when in the test mode. In one embodiment, each of the N bit parallel data provided by test mode controller 750 is pseudo random data.

The CRC calculator 730 and the CRC checker 740 generate parity codes in the time axis (horizontal) direction in the test mode and perform parity check on the test data in the time axis direction. In the normal mode instead of the test mode, the CRC calculator 730 and the CRC checker 740 may generate parity codes for individual parallel data, serialize the parallel data and the parity code, and transmit the serial data.

The CRC calculator 730 generates N parity codes in the time axis direction for the plurality of N bit parallel data, and provides the generated parity codes to the serializer 731. Serializer 731 serializes the N bit parallel data in a first-in first-out manner, then serializes the N parity codes. The output unit 732 transmits serial test data provided by the serializer 731 to an external transmission line. The test mode controller 750, the CRC calculator 730, the serializer 731, and the output unit 732 for input / output testing serve as serial test data generators.

The receiver 742 receives serial test data transmitted through a transmission line. The received data is provided to the parallelizer 741. The parallelizer 741 outputs parallel test data by parallelizing the received data. The parallel test data is provided to the CRC checker 740, and the N bit parallel data from which parity codes are removed from the parallel test data is provided to the input / output controller 720. The CRC checker 740 performs a parity check on at least one test bit string among N test bit strings in the time axis direction included in the parallel test data. The CRC checker 740 notifies the input / output controller 720 that no error is detected in the parity check when no error is detected in the parity check, and informs the input / output controller 720 when the error is detected in the parity check. Signals that is detected. The receiver 742, the parallelizer 741, and the CRC checker 740 serve as an input / output error detector for checking whether an input / output error occurs. An error may occur in a portion of the received serial test data. When an error occurs, the semiconductor device 700 is determined to be defective.

The CRC calculator 730 and CRC checker 740 of FIG. 7 are both based on the same CRC circuit structure. In the above embodiment, the CRC calculator 730 and the CRC checker 740 are based on a CRC circuit that generates a 1-bit parity code. However, this is merely an example, and the input / output test of the semiconductor device may be performed using a larger parity code size.

Hereinafter, a CRC circuit for generating a 4-bit parity code will be described.

8 is a circuit diagram illustrating a CRC generator for explaining a CRC generation and check process according to an embodiment of the present invention.

  The CRC generation circuit receives a message block M having a predetermined size and generates a parity code for the message block M. The message block (M) is treated as one binary number and divided by the CRC-generated polynomial. To this end, the CRC generation circuit may be implemented with XOR gates 820 and 821 and D flip-flops 810, 811, 812 and 813. The D flip-flops 810, 811, 812, and 813 operate in synchronization with a clock and are initialized by a clear signal CLR. The number and connection of CRC generation circuits may vary according to the CRC polynomial.

The CRC generation polynomial of the CRC generation circuit of FIG. 8 is represented by Equation 1 below.

[Equation 1]

Here, G (X) means a CRC generation polynomial, which is 10011 when expressed as a bit string.

Assuming that the message block M is 1011001, which is a 6-bit value, the parity code is 1010, which is the remainder of dividing 1011001 by 10011. The CRC calculation process sets the value of the message block M to 1011001 and inputs it to the CRC generation circuit of FIG. 8.

In the initial stage, the values of the first to fourth D flip-flops 810, 811, 812, and 813 are 0, 0, 0, and 0, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the first clock are 1, 0, 0, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the second clock are 0, 1, 0, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the third clock are 1, 0, 1, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the fourth clock are 1, 1, 0, and 1 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the fifth clock are 1, 0, 1, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the sixth clock are 0, 1, 0, and 1 in the clock, respectively. Since all values of the message block M are input, 0 is input to the input terminal of the first XOR gate 820 in a later step.

The values of the first through fourth D flip-flops 810, 811, 812, and 813 in the seventh clock are 0, 1, 1, and 0 in the clock, respectively.

The values of the first through fourth D flip-flops 810, 811, 812, and 813 in the eighth clock are 0, 0, 1, and 1 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the ninth clock are 1, 1, 0, and 1 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the tenth clock are 1, 0, 1, and 0 in the clock, respectively. At this time, 1010 is a parity code, which is a value obtained by dividing 1011001 by 10011.

Therefore, the test bit string in which the message block M and the parity code are combined becomes 10110011010 in which 1011001 and 1010 are combined.

Parity codes for the plurality of N-bit parallel data may be obtained for N bit strings in the time axis (horizontal) direction, respectively.

The parity check process is as follows.

When the test bit string 10110011010 is input, the values of the first to fourth D flip-flops 810, 811, 812, and 813 are all in an initial state of zero.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the first clock are 1, 0, 0, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the second clock are 0, 1, 0, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the third clock are 1, 0, 1, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the fourth clock are 1, 1, 0, and 1 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the fifth clock are 1, 0, 1, and 0 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the sixth clock are 0, 1, 0, and 1 in the clock, respectively.

The values of the first through fourth D flip-flops 810, 811, 812, and 813 in the seventh clock are 0, 1, 1, and 0 in the clock, respectively.

The values of the first through fourth D flip-flops 810, 811, 812, and 813 in the eighth clock are 0, 0, 1, and 1 in the clock, respectively.

The values of the first to fourth D flip-flops 810, 811, 812, and 813 in the ninth clock are 1, 1, 0, and 1 in the clock, respectively.

At the tenth clock, the values of the first to fourth D flip-flops 810, 811, 812, and 813 are all zero. In this case, it means that no error occurred in the test bit string during the transmission process. However, if any one bit is changed in the test bit string 10110011010, at least one of the first to fourth D flip-flops 810, 811, 812, and 813 is 1 in the tenth clock.

The CRC generation circuit can be used when generating the parity code in the time axis direction. N CRC generation circuits are needed to generate N codes for the plurality of N bit parallel data.

9 is a block diagram illustrating a serialization process according to an embodiment of the present invention.

When the N bit parallel message block M is input, the CRC calculator 730 generates N parity codes C in the time axis direction. The first and second switches 910 and 920 are selectively opened and closed by the control signal Ctr. For example, when the first switch 910 is closed, the second switch 920 is opened. Likewise, when the first switch 910 is opened, the second switch 920 is closed.

The first switch 910 is closed first, and when the first switch 910 is closed, the N bit parallel message block M is first serialized by the serializer 731 in a first-in first-out manner. Then, when the second switch 920 is closed, N parity codes are parallelized.

According to an embodiment of the present invention, test data for performing an input / output test of a semiconductor device may be generated without a phase alignment process. In addition, the input / output test of the semiconductor device may be performed by the loopback test method using the test data.

Therefore, according to the embodiment of the present invention, it is not necessary to implement complicated logic for phase alignment in the semiconductor device for the loopback test. In addition, according to an exemplary embodiment of the present invention, an input / output test may be performed through a loopback test even for a semiconductor device having no logic for phase alignment.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (14)

Serializing a plurality of N-bit parallel data on a first in, first out basis; Generating N parity codes in the time axis direction for the N bit parallel data; And And serializing the generated N parity codes after the serialized data. The test data generation method of claim 1, wherein each of the N bit parallel data is pseudo random data. The method of claim 1, wherein the N parity codes have a size of 1 bit. Generating serial test data from the plurality of N bit parallel data; Outputting the serial test data to an external transmission line; Receiving the serial test data transmitted through the external transmission line; And Checking whether an input / output error occurs based on the serial test data; Generating the serial test data includes: Serializing the N bit parallel data on a first in, first out basis; Generating N parity codes in the time axis direction for the N bit parallel data; And And serializing the generated N parity codes after the serialized data. The method of claim 4, wherein each of the N bit parallel data is pseudo random data. The method of claim 4, wherein the N parity codes have a size of 1 bit. The method of claim 4, wherein the checking of the input / output error has occurred. Parallelizing the serial test data; And checking parity of at least one test bit string among N test bit strings in a time axis direction included in the parallelized test data. A data provider for providing a plurality of N-bit parallel data; A parity code generation unit which receives the N bit parallel data and generates N parity codes in a time axis direction; And And a serializer to serialize the N-bit parallel data by first-in first-out, and serialize the generated N parity codes after the serialized data. The test data generator of claim 8, wherein the data providing unit provides the N bit parallel data as pseudo random data. The test data generator of claim 8, wherein the parity code generator provides the N parity codes in a size of 1 bit. A test data generator for generating serial test data based on the plurality of N bit parallel data; An output unit for outputting the serial test data to an external transmission line; An input unit configured to receive the serial test data transmitted through the external transmission line; And And an input / output error detector for checking whether an input / output error occurs based on the serial test data. The test data generator is: A data provider for providing the plurality of N-bit parallel data; A parity code generation unit generating N parity codes in the time axis direction with respect to the N bit parallel data; And And serializing the N bit parallel data on a first-in, first-out basis, and serializing the generated N parity codes after the serialized data. The input / output test apparatus of claim 11, wherein the data providing unit provides the N-bit parallel data as pseudo random data. The input / output test apparatus of claim 11, wherein the parity code generator provides the N parity codes in one bit size. The method of claim 11, wherein the input and output error detector A parallelizer for parallelizing the serial test data; And a parity check unit configured to check parity of at least one test bit string among N test bit strings in the time axis direction included in the parallelized test data.

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