JP2004153592A - Device and method for pattern synchronization pull-in - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pattern synchronization pull-in device and method for conducting synchronization detection and accurately counting bit errors, even if there are many errors in received data. <P>SOLUTION: A PRBS (Pseudo Random Bit Sequence) pattern pull-in circuit comprises a plurality of PRBS pattern generating circuits 8-11, a comparison circuit 12, and a synchronization detecting circuit 13. The PRBS pattern generating circuits 8-11 input partial data taken out from received data at a position different from each other, and generate pattern data based on the partial data. The comparison circuit 12 acquires a plurality of pattern data generated by the PRBS pattern generating circuits 8-11 and inputs the received data, and compares each of the plurality of pattern data with the received data. The synchronization detecting circuit 13 inputs the result of the comparison made by the comparison circuit 12, and detects the pattern data synchronized to the received data using the comparison result. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bit error detection device, and in particular, compares a pseudo random pattern sent from a transmission device to a reception device with a reference pseudo random pattern generated by a pseudo random pattern generation circuit in the reception device. The present invention relates to a pseudo random pattern synchronization pull-in apparatus and method.
[0002]
[Prior art]
A pseudo random pattern (Pseudo Random Bit Sequence pattern; hereinafter, referred to as a “PRBS pattern”) is often used for testing a communication device, a transmission device, a transmission line, and the like. The following procedure is taken in a test apparatus that performs a test by transmitting and receiving a PRBS pattern. The receiving device (1) synchronizes the received signal with an internally generated reference signal, (2) compares the received data with the reference signal, (3) counts the number of erroneous bits, (4) Evaluate the received data.
[0003]
That is, in this type of test, the PRBS pattern generated by the transmission device is received by the reception device via a device or a transmission device, and is used as a reference PRBS pattern generated by a PRBS pattern generation circuit included in the reception device. Be compared. Then, the PRBS pattern generated in the transmission device is compared with a reference PRBS pattern output (generated) by a PRBS pattern generation circuit in the reception device, and the number of occurrences of bit errors in the reception data is counted and output.
[0004]
An example of a conventional error measurement circuit will be described with reference to FIG.
FIG. 6 is a block diagram of an error measuring circuit according to the related art.
The synchronization detection circuit 3 determines the synchronization between the received data and the reference data output from the PRBS pattern generation circuit 1 based on the detection pulse of the comparison circuit 2.
When correct data without error is input to the received data, the PRBS pattern generation circuit 1 outputs a reference PRBS pattern using the received data as an initial value. The comparison circuit 2 compares the next received data with the reference data output from the PRBS pattern generation circuit 1. The synchronization detection circuit 3 detects synchronization based on the comparison result.
[0005]
With reference to FIG. 6, a prior art of an error measuring circuit that counts the number of occurrences of bit errors in received data when a PRBS pattern is generated when synchronization is detected will be described.
6 is a PRBS pattern generation circuit for outputting reference data in the receiving apparatus, 2 is a comparison circuit, 3 is a synchronization detection circuit that determines synchronization between reference data and received data, 4 is a count circuit, 5 is PRBS. In the pattern generation circuit, a selector circuit for loading an initial value, 6 is an FF (Flip Flop), and 7 is a Pseudo-random Noise (hereinafter referred to as "PN") operation circuit for generating a PRBS pattern.
[0006]
In FIG. 6, received data input by the receiving apparatus is input to the PRBS pattern generation circuit 1 and the comparison circuit 2. The PRBS pattern generation circuit 1 outputs a PRBS pattern serving as reference data based on the last a bit of the received data until the synchronization is detected by the synchronization detection circuit 3. After the synchronization is detected by the synchronization detection circuit 3, the PRBS pattern serving as the next reference data is output based on the generated reference data. Here, n is the number of bits for parallel processing, a is the number of bits for generating a PRBS pattern, and a ≦ n.
[0007]
The comparison circuit 2 compares the input received data with the reference data output by the PRBS pattern generation circuit 1, and outputs a detection pulse each time they differ. The count circuit 4 counts the number of the pulses and outputs a count value.
The PRBS pattern generation circuit 1 outputs a PRBS pattern to be the next reference data based on the reference data generated until the synchronization is lost thereafter. If there is an error in the received data, since the received data is different from the reference PRBS pattern, the comparison circuit 2 outputs a pulse at that time. The count circuit 4 counts this pulse and outputs it.
[0008]
[Patent Document 1]
JP-A-9-46323
[0009]
[Problems to be solved by the invention]
In a conventional error measuring circuit, if there is a large amount of error in received data in a state where synchronization is not detected, the PRBS pattern generation circuit 1 outputs a PRBS pattern generated based on erroneous received data. There was a problem that could not be done.
As described above, in the conventional error measuring circuit, the received data must not have an erroneous pattern until the synchronization is detected. At least, incorrect data must not continue to exist at the data position used for generating the PRBS pattern. When erroneous received data is received, the PRBS pattern generation circuit 1 cannot output a PRBS pattern synchronized with the received data because the erroneous data is used, so that synchronization cannot be detected. Was.
[0010]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a PRBS pattern synchronization pull-in apparatus and method capable of detecting synchronization and accurately counting bit errors even when received data has many errors.
[0011]
[Means for Solving the Problems]
A pattern synchronization pull-in device according to the present invention includes: a plurality of pattern generating circuits that receive partial data extracted from received data and generate pattern data based on the partial data;
A plurality of pattern data generated by the plurality of pattern generation circuits, a plurality of pattern data is input, the received data is input, and a comparison unit that compares the plurality of pattern data with the received data,
A synchronization detection unit that inputs the comparison result compared by the comparison unit and detects the pattern data synchronized with the reception data using the comparison result.
It is characterized by having.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
The PRBS pattern synchronization pull-in method and PRBS pattern synchronization pull-in device according to the present invention are characterized in that when detecting synchronization, a plurality (m) of PRBS pattern generation circuits having different positions for receiving n parallel received data are provided. In this way, there is provided means for avoiding errors in received data and enabling synchronization detection. “N-parallel received data” means “n-bit parallel received data”, and means that the number of bits processed at one time is n bits.
[0013]
FIG. 1 is a conceptual explanatory diagram using four PRBS pattern generation circuits (m = 4) as an example of the present invention.
In FIG. 1, reference numerals 8, 9, 10, and 11 are PRBS pattern generation circuits. 8, 9, 10, and 11 generate the next PRBS pattern by inputting the PRBS pattern generated by itself in the normal operation state, and generate the next PRBS pattern by inputting the received data in the out-of-sync state. The four PRBS pattern generation circuits have different bit positions when inputting a bit out of n parallel received data.
[0014]
When processing the received data in units of n bits using m pieces of PRBS pattern generation circuits, m pieces of partial data (a bits) are extracted from the received data as follows.
Of the received data, n bits are determined (hereinafter referred to as “n-bit received data”), and m pieces of partial data (a bits) are extracted from different positions of the n-bit received data.
Each of the m PRBS pattern generation circuits receives different partial data (a bits) and generates a PRBS pattern (pattern data) using the partial data. In the example of FIG. 1, the PRBS pattern is shown to be b bits. The b bits may be the same as the n bits, or may be a bit number smaller than the n bits. b can take a numerical value in the range of b ≦ n.
[0015]
FIG. 2 shows a relationship between the received data, the n-parallel received data (nbit), and the a-bit (abit) of the n-parallel received data.
In the received data, each of the portions indicated as n bits is the number of PRBS data generated at a time and the number of bits to be compared with the received data at the same time.
The part indicated as abit indicates an example of a plurality of a bits input to the PRBS pattern generation circuits 8, 9, 10, and 11 among the n bits. m corresponds to the number of PRBS pattern generation circuits, and the examples of FIGS. 1 and 2 show a case where m is 4. The four a-bits shown in FIG. 2 indicate a-bit partial data extracted from different positions, but this does not exclude that they are the same.
FIG. 2 shows two examples in which a-bit partial data different from each other is extracted from n bits of the received data. Once the position of the a bit input to the PRBS pattern generation circuit is determined, it is not changed thereafter.
Further, although not shown in FIG. 2, the a bit input to each of the PRBS pattern generation circuits 8, 9, 10, and 11 is obtained by dividing n bits into m equal parts (m is the number of PRBS pattern generation circuits). It may be a case where one is input.
Further, a part of the four (m) a-bit partial data may be overlapped.
[0016]
A comparison circuit 12 compares the PRBS patterns generated by the four PRBS pattern generation circuits with the received data.
Reference numeral 13 denotes a synchronization detection circuit which detects synchronization based on the result of the comparison.
[0017]
When received data without errors is input, the PRBS pattern generation circuits 8, 9, 10, and 11 generate correct PRBS patterns. When the received data including the error is input, the PRBS pattern generating circuits 8, 9, 10, and 11 generate the PRBS pattern based on the correct received data portion because different bit positions are input. A PRBS pattern generation circuit may be present. If the PRBS pattern generation circuits 8, 9, 10, and 11 receive error-containing reception data portions and the PRBS pattern generation circuit 9 receives error-free reception data portions, the synchronization detection circuit generates PRBS pattern generation circuits 9 and 9. Can be detected based on the result of comparison between the generated PRBS pattern and the received data.
[0018]
The internal configuration of the PRBS pattern generation circuit is the same as that of the pattern generation circuit 1 of FIG. Therefore, it includes the components of the selector circuit, the FF, and the PN operation circuit. The PRBS pattern generation circuits 8, 9, 10, and 11 select either the PRBS pattern (normal operation state) generated by themselves or the received data (out-of-synchronization state) by the selector circuit, and based on the selected result. , Generate the next PRBS pattern.
“Correct data” refers to data transmitted to the receiving device without error (when there is no error) when data is transmitted from the transmitting device to the receiving device.
The “normal operation state” is a state in which synchronization is established. Specifically, the state in which the received data and the generated PRBS pattern data are synchronized, or the PRBS pattern generation circuit generates the next PRBS pattern based on the data generated (generated or generated) by itself. This refers to a state in which pattern data is being generated.
The out-of-synchronization state refers to a state in which the received data and the generated PRBS pattern data are not synchronized. Specifically, this means that the PRBS pattern generation circuit is generating the next PRBS pattern data based on the received data.
[0019]
Here, the description has been given by taking m = 4 as an example, but it goes without saying that the object of the present invention is similarly achieved when m is other than 4.
[0020]
As described above, the pattern synchronization pull-in device (PRBS pattern synchronization pull-in device) extracts partial data (a bits) extracted from received data (n-parallel received data of received data, that is, n-bit received data). A plurality of pattern generation circuits 8 to 11 for inputting and generating pattern data (PRBS pattern data, b bits (b ≦ n)) based on the partial data, and a plurality of pattern generation circuits 8 to 11 A comparison circuit (comparator) 12 that acquires a plurality of pattern data, inputs received data (n bits), and compares each of the plurality of pattern data with the received data (n bits), and a comparison circuit 12 A synchronization detection circuit for inputting a result and detecting the pattern data synchronized with the received data using the comparison result. Explained that anda (synchronization detection unit) 13. The comparison circuit 12 is an example of a comparison unit, and the synchronization detection circuit 13 is an example of a synchronization detection unit.
[0021]
In addition, the pattern synchronization pull-in apparatus and method input received data, extract a plurality of partial data different from each other from the input received data, and generate the plurality of pattern data based on each of the extracted plurality of partial data. And comparing each of the generated plurality of pattern data with the received data, and detecting at least one pattern data synchronized with the received data using the comparison result. did.
[0022]
Embodiment 1 FIG.
Hereinafter, specific embodiments according to the present invention will be described in detail with reference to the drawings.
FIG. 3 shows an embodiment of a bit error measuring circuit to which the present invention is applied. FIG. 3 shows, as an example, a case in which four PRBS pattern generation circuits are used (m = 4) and the number of PRBS pattern generation bits (b) of each of the four PRBS pattern generation circuits is n (b = n). .
3, the bit error measuring circuit includes a PRBS pattern generating circuit 8, a PRBS pattern generating circuit 9, a PRBS pattern generating circuit 10, a PRBS pattern generating circuit 11, a comparing circuit 12, a synchronization detecting circuit 13, a count circuit 14, and a selector circuit 15. It consists of.
[0023]
The PRBS pattern generation circuit 8, the PRBS pattern generation circuit 9, the PRBS pattern generation circuit 10, and the PRBS pattern generation circuit 11 transmit a bit out of n bits (n-parallel reception data) of the reception data to a partial data in an out-of-synchronization state. And generates (outputs) the next n-parallel PRBS pattern based on the value (the a-bit partial data). Here, the bit position of the received data taken in by each PRBS pattern generating circuit is changed, but when the received data is each PRBS pattern having no error, the PRBS pattern generated by each PRBS pattern generating circuit is the same. . That is, as shown in FIG. 2, when a partial data of any a bit (consecutive a bit) of n bits (n parallel) of the received data is input to the PRBS pattern generation circuit (any of 8 to 11). , The same PRBS pattern will be generated.
[0024]
In the synchronized state, the PRBS pattern generation circuit 8, PRBS pattern generation circuit 9, PRBS pattern generation circuit 10, and PRBS pattern generation circuit 11 continuously generate PRBS patterns based on the PRBS patterns generated by themselves.
[0025]
The comparison circuit 12 compares the received data with the PRBS pattern input from each of the PRBS pattern generation circuits 8, 9, 10, and 11 for each corresponding bit, and outputs the result. Specifically, the comparison circuit 121 in the comparison circuit 12 compares the PRBS pattern input from the PRBS pattern generation circuit 8 with the reception data, and compares the PRBS pattern input from the PRBS pattern generation circuit 9 with the reception data. The comparison circuit 122 inside the comparison circuit 12 compares the PRBS pattern input from the PRBS pattern generation circuit 10 with the received data. The comparison circuit 123 inside the comparison circuit 12 compares the PRBS pattern input from the PRBS pattern generation circuit 11 The comparison circuit 124 in the comparison circuit 12 compares the data with the received data independently for each corresponding bit, and outputs the result.
[0026]
The synchronization detection circuit 13 detects whether the outputs of the four PRBS pattern generation circuits 8, 9, 10, and 11 are synchronized with the received data based on the output of the comparison circuit 12. Specifically, a synchronization detection circuit 131 in the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 8 with the reception data, and a synchronization detection circuit in the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 9 with the reception data. 132, a synchronization detection circuit 133 inside the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 10 with the reception data, and a synchronization detection circuit 134 inside the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 11 with the reception data. , And performs synchronization detection independently.
The result detected by the synchronization detection circuit 13 is notified to the PRBS pattern generation circuits 8, 9, 10, and 11.
[0027]
When notified of the synchronization state from the synchronization detection circuit 13, the PRBS pattern generation circuits 8, 9, 10, and 11 generate the next PRBS pattern using the PRBS pattern generated by themselves. Whether to use the own PRBS pattern is selected by the selector circuit 5 shown in FIG. The selector circuit 5 selects one of its own PRBS pattern and a-bit partial data based on the notification from the synchronization detection circuit 13.
[0028]
The selector circuit 15 selects the output of the comparison circuit 12 corresponding to the output of the PRBS pattern generation circuit, if any of the PRBS pattern generation circuits 8, 9, 10, 11 is in a synchronized state. Output. The selector circuit 15 maintains the selected state until the selected PRBS pattern generation circuit is out of synchronization. If two or more PRBS pattern generation circuits are synchronized, priority processing is performed and one is selected.
The count circuit 14 counts errors in the synchronous state selected by the selector circuit 15.
[0029]
As described above, in this embodiment, the pattern synchronization pull-in device includes a plurality of pattern generation circuits (PRBS pattern generation circuits), and as an example of the comparison circuit (comparison unit) 12, the plurality of pattern generation circuits. As an example of the synchronization detection circuit (synchronization detection unit) 13, a plurality of comparison circuits 121 to 124 corresponding to each of the plurality of comparison circuits 121 to 124 are provided. Indicated.
Each of the plurality of pattern generation circuits 8 to 11 outputs the generated pattern data to each of the corresponding comparison circuits 121 to 124, and each of the plurality of comparison circuits 121 to 124 selects one of the plurality of pattern generation circuits 8 to 11. The pattern data is input from one of them, and the comparison result is output to the corresponding synchronization detection circuits 131 to 134 respectively.
Each of the plurality of synchronization detection circuits 131 to 134 receives the comparison result from any one of the plurality of comparison circuits 121 to 124, and uses the comparison result to synchronize the pattern data synchronized with the reception data. Has been described.
[0030]
As described above, in the out-of-synchronization state, the PRBS pattern is generated by taking in the initial pattern at a plurality of positions from the erroneous received data, thereby enabling synchronization detection while avoiding error bits.
[0031]
As described above, in this embodiment, at the time of loss of synchronization, pseudo-random pattern generation circuits (PRBS pattern generation circuits 8, 9, 10, 11) that take in different bit positions of parallel received data and generate pseudo-random pattern data A comparison circuit for comparing received data with pseudo-random pattern data generated by the pseudo-random pattern generation circuit; and a synchronization detection circuit for detecting synchronization between the pseudo-random pattern generation circuit and received data. In the pseudo random pattern synchronization pull-in device, a pseudo random pattern synchronization pull-in device characterized by comprising a plurality of the pseudo random pattern generation circuits in which bit positions of data taken from received data are changed in order to synchronize with received data. explained.
[0032]
Embodiment 2 FIG.
FIG. 4 shows an embodiment of a bit error measuring circuit to which the present invention is applied. FIG. 4 shows, as an example, a case where four PRBS pattern generation circuits are used (m = 4) and the number of PRBS pattern generation bits of each of the four PRBS pattern generation circuits is n / 4 (b = n / 4). I have.
4, the bit error measuring circuit includes a PRBS pattern generating circuit 8b, a PRBS pattern generating circuit 9b, a PRBS pattern generating circuit 10b, a PRBS pattern generating circuit 11b, a comparing circuit 12b, a synchronization detecting circuit 13b, and a counting circuit 14. You.
[0033]
The PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b perform the following operations in an out-of-synchronization state.
Each of the PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b captures a bit of the reception data (n / 4 bits) divided into four, and stores the value. Based on this, a corresponding n / 4-bit PRBS pattern in the next n parallel is generated (output).
[0034]
FIG. 5 is a diagram showing an example of partial data of abit input to the PRBS pattern generation circuit. The PRBS pattern generation circuit 8b takes in a bit of n / 4 from the MSB side. Similarly, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b also take in a bit of n / 4 bits. The bit position may be a bit array at any position as long as it is within the range of n / 4 bits. However, in the example of FIG. 5, the four bits do not overlap. This is because abit is extracted from each range divided into n / 4. Further, once the position of the abit is determined, it is not changed. Further, the abit partial data may be the n / 4-bit received data itself (all). a can take a value in the range of a ≦ (n / m).
[0035]
At this time, the PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b take in data from another PRBS pattern generation circuit as shown in FIG. Specifically, the PRBS pattern generation circuit 8b generates the circuit 1 data 1 generated by the PRBS pattern generation circuit 9b, the circuit 1 data 2 generated by the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b. The data 3 for the circuit 1 is taken in. However, in an out-of-synchronization state, the PRBS pattern generation circuit 8b uses the input abit, but does not use the data 1 for the circuit 1, the data 2 for the circuit 1, and the data 3 for the circuit 1.
[0036]
The PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b use the fetched abit to generate n / 4 PRBS patterns and data for other PRBS pattern generation circuits (PRBS pattern generation data). In the case of the generating circuit 8b, data 1 for the circuit 2, data 1 for the circuit 3, and data 1 for the circuit 4) are generated, and n-bit data is output together with the n / 4 PRBS pattern. Of the output data, the generated n / 4 PRBS pattern is input to the comparison circuit 12b.
[0037]
In addition, it determines whether the PRBS pattern generated by itself is used as an initial value when transitioning from the out-of-synchronization state to the synchronization state, or whether an initial value pattern generated by another PRBS pattern generation circuit is used as an initial value. Thereafter, a PRBS pattern is generated using the determined pattern (either the self-generated PRBS pattern or the initial value pattern generated by another PRBS pattern generation circuit), and then the self-generated PRBS pattern is generated. The PRBS pattern is continuously generated based on the pattern. Whether to select the PRBS pattern generated by itself or the initial value pattern generated by another PRBS pattern generation circuit is output from a circuit capable of detecting synchronization based on the result of the synchronization detection circuit 13b. Select data.
[0038]
The comparison circuit 12b compares a PRBS pattern (n / 4-bit data) input from each PRBS pattern generation circuit with received data (n / 4 bits of n parallel received data) for each corresponding bit. And output the result.
Specifically, the comparison circuit 121 in the comparison circuit 12b compares the PRBS pattern input from the PRBS pattern generation circuit 8b with the MSB (Most Significant Bit) side data of the reception data divided into four, and the PRBS pattern generation is performed. The comparison circuit 122 in the comparison circuit 12b compares the PRBS pattern input from the circuit 9b with the second data from the MSB side of the reception data divided into four parts, and compares the PRBS pattern input from the PRBS pattern generation circuit 10b with the PRBS pattern input from the PRBS pattern generation circuit 10b. The comparison circuit 123 inside the comparison circuit 12b compares the received data divided into four with the third data from the MSB side by using the LSB of the received data divided into four with the PRBS pattern input from the PRBS pattern generation circuit 11b. (Least Significant Bit) side ratio The comparison circuit 124 in the comparison circuit 12b independently compares each of the corresponding bits and outputs the result.
[0039]
The synchronization detection circuit 13b detects whether the outputs of the four PRBS pattern generation circuits are synchronized with the received data based on the output of the comparison circuit 12b. Specifically, the synchronization detection circuit 131 in the synchronization detection circuit 13b synchronizes the PRBS pattern generation circuit 8b with the reception data, and the synchronization detection circuit 131 in the synchronization detection circuit 13b synchronizes the PRBS pattern generation circuit 9b with the reception data. Reference numeral 132 designates a synchronization between the PRBS pattern generation circuit 10b and the reception data, a synchronization detection circuit 133 inside the synchronization detection circuit 13b, and a synchronization between the PRBS pattern generation circuit 11b and the reception data using the synchronization detection circuit 134 inside the synchronization detection circuit 13b. , And performs synchronization detection independently.
[0040]
The synchronization control circuit 135 in the synchronization detection circuit 13b sets the synchronization state to the PRBS pattern generation circuit if there is a PRBS pattern generation circuit in the synchronization state, and sets the synchronization state to the other PRBS pattern generation circuits. At the same time, an instruction to select a corresponding pattern as an initial value is output from the output of the synchronized PRBS pattern generation circuit. When the synchronization state is not detected, the synchronization control circuit 135 outputs an instruction to select the partial data (a bit) extracted from the received data as an initial value. The initial value is data used as a reference when generating PRBS pattern data.
The synchronization control circuit 135 notifies the PRBS pattern generation circuit of the selected initial value (outputs an instruction).
If two or more PRBS pattern generation circuits are synchronized, the synchronization control circuit 135 responds to the out-of-synchronization state of the PRBS pattern generation circuit from the output of the PRBS pattern generation circuit that has been synchronized. An instruction to select a pattern as an initial value is output. Which output of the PRBS pattern generating circuit is to be used is selected by performing priority processing.
[0041]
The count circuit 14 outputs an error by counting the output of the comparison circuit 12b.
[0042]
The PRBS pattern generation circuit selects an initial value based on the notification (instruction) from the synchronization control circuit 135, and generates the next PRBS pattern data using the selected initial value. As described with reference to FIG. 6, the PRBS pattern generation circuit includes the selector circuit 5 therein, and the selector circuit 5 selects an initial value.
That is, based on the notification (instruction) from the synchronization control circuit 135, the PRBS pattern generation circuit initializes the PRBS pattern (pattern data) generated by itself and the PRBS pattern generated by another pattern generation circuit based on the notification (instruction). Then, the next PRBS pattern (pattern data) is generated using any one of the partial data and the partial data.
[0043]
Further, FIG. 4 illustrates an example in which the comparison circuit 12b includes four (m) comparison circuits of the comparison circuits 121 to 124, but this may be a single comparison circuit. . The comparison circuit 12b may be a circuit capable of comparing n bits (m times n / m bits).
Similarly, the example in which the synchronization detection circuit 13b includes four (m) synchronization detection circuits of the synchronization detection circuits 131 to 134 is shown, but a single comparison circuit may be used.
In the example of FIG. 4, unlike the example of FIG. 3, the synchronization control circuit 135 is an essential component. The synchronization control circuit 135 instructs the PRBS pattern generation circuit which data is to be an initial value.
[0044]
As described above, in this embodiment, the pattern synchronization pull-in device includes a plurality of PRBS pattern generation circuits (pattern generation circuits) 8b to 11b, a comparison circuit (comparison unit) 12b, and a synchronization detection circuit (synchronization detection unit) 135, and further selects any of the received data and the pattern data generated by the pattern generation circuit detected by the synchronization detection unit as an initial value, and selects the selected initial value for each of the plurality of pattern generation circuits. It has been described that a synchronization control circuit (synchronization control unit) 135 for notifying the user is provided.
Further, each of the plurality of PRBS pattern generation circuits 8b to 11b inputs the pattern data generated by itself, the pattern data generated by the other PRBS pattern generation circuits 8b to 11b, and the partial data, and Based on the initial value notified by the synchronization control circuit 135, the pattern data generated by itself, the pattern data generated by another pattern generation circuit, and the partial data are used to perform the following. It is characterized by generating pattern data.
[0045]
Further, assuming that the parallel number of the received data is n and the number of the plurality of pattern generating circuits is m, n is equally divided by m, and each of the received data having a length of n / m is divided into the plurality of patterns. Each of the plurality of pattern generating circuits 8b to 11b is assigned to a generating circuit, and generates pattern data having a length of n / m using the received data having a length of n / m.
[0046]
As described above, in an out-of-synchronization state, a PRBS pattern is generated by fetching as an initial pattern at a plurality of positions from erroneous received data, and a synchronized PRBS pattern generation circuit outputs to a non-synchronized PRBS pattern generation circuit. By capturing the PRBS pattern to be performed as an initial pattern, synchronization detection can be performed while avoiding error bits.
[0047]
As described above, in this embodiment, in the pseudo-random pattern synchronization pull-in device, in order to synchronize with the received data, the bit position of the data to be fetched from the received data is changed, and the initial positions of the plurality of prepared pseudo-random pattern generation circuits are changed. A pseudo-random pattern synchronization pull-in device comprising a plurality of pseudo-random pattern generation circuits capable of generating data and taking in initial data from another pseudo-random pattern generation circuit has been described.
[0048]
Embodiment 3 FIG.
Although FIGS. 1, 3, and 4 show circuits using a PRBS pattern generation circuit, a comparison circuit, a synchronization detection circuit, a count circuit, a selector circuit, a synchronization control circuit, and the like, the invention is not limited to circuits. For example, it may be realized using software, firmware, or the like other than the circuit. Therefore, the above components include a PRBS pattern generation circuit for a PRBS pattern generation circuit, a comparison circuit for a comparison circuit, a synchronization detection circuit for a synchronization detection circuit, a counter circuit for a count circuit, a selector circuit for a selector circuit, and a synchronization control circuit for a synchronization control circuit. Can be shown as
[0049]
Embodiment 4 FIG.
In the first to third embodiments, the PRBS synchronization pull-in device and method using the PRBS pattern generation circuit have been described. However, a case where pattern data other than the PRBS pattern is used may be used.
Further, “pull-in” of the PRBS pattern synchronization pull-in device refers to an operation that makes it difficult to synchronize patterns.
[0050]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the pattern synchronization pull-in apparatus and method of this invention, even if received data has many errors, it becomes possible to perform synchronization detection avoiding error bits, and to perform accurate bit error counting.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a relationship between received data n-bit data and abit data.
FIG. 3 is a configuration diagram showing Embodiment 1 of the error measurement circuit according to the present invention.
FIG. 4 is a configuration diagram showing a second embodiment of the error measurement circuit according to the present invention.
FIG. 5 is a diagram illustrating an example of an abit input to a PRBS pattern generation circuit.
FIG. 6 is a configuration diagram illustrating an example of an error measurement circuit according to the related art.
[Explanation of symbols]
Reference Signs List 1 PRBS pattern generation circuit, 2 comparison circuit, 3 synchronization detection circuit, 4 count circuit, 5 selector circuit, 6 FF (Flip Flop), 7 PN operation circuit, 8, 8b PRBS pattern generation circuit, 9, 9b PRBS pattern generation circuit , 10, 10b PRBS pattern generation circuit, 11, 11b PRBS pattern generation circuit, 12, 12b comparison circuit, 13, 13b synchronization detection circuit, 14 count circuit, 15 selector circuit, 121 comparison circuit, 122 comparison circuit, 123 comparison circuit, 124 comparison circuit, 131 synchronization detection circuit, 132 synchronization detection circuit, 133 synchronization detection circuit, 134 synchronization detection circuit, 135 synchronization control circuit.

Claims (7)

A plurality of pattern generating circuits for inputting partial data extracted from the received data and generating pattern data based on the partial data,
A plurality of pattern data generated by the plurality of pattern generation circuits, a plurality of pattern data is input, the received data is input, and a comparison unit that compares the plurality of pattern data with the received data,
A pattern synchronization pull-in device, comprising: a synchronization detection unit that inputs a comparison result compared by the comparison unit and detects the pattern data synchronized with the reception data using the comparison result. 2. The pattern synchronization pull-in device according to claim 1, wherein the partial data input to each of the plurality of pattern generation circuits is extracted from different positions. The comparison unit has a plurality of comparison circuits corresponding to each of the plurality of pattern generation circuits,
The synchronization detection unit has a plurality of synchronization detection circuits corresponding to each of the plurality of comparison circuits,
Each of the plurality of pattern generation circuits outputs the generated pattern data to a corresponding comparison circuit,
Each of the plurality of comparison circuits receives the pattern data from any one of the plurality of pattern generation circuits, and outputs the comparison result to a corresponding synchronization detection circuit,
Each of the plurality of synchronization detection circuits receives the comparison result from any one of the plurality of comparison circuits, and detects the pattern data synchronized with the reception data using the comparison result. 3. The pattern synchronization pull-in device according to claim 1, wherein: The pattern synchronization pull-in device further selects one of the partial data and the pattern data generated by the pattern generation circuit detected by the synchronization detection unit as an initial value, and sets the selected initial value to the plurality of patterns. A synchronization control unit that notifies each of the generation circuits,
Each of the plurality of pattern generation circuits inputs pattern data generated by itself, pattern data generated by another pattern generation circuit, and the partial data, and based on an initial value notified by the synchronization control unit. The next pattern data is generated by using one of the pattern data generated by itself, the pattern data generated by another pattern generation circuit, and the partial data. Item 4. The pattern synchronization pull-in device according to any one of Items 1 to 3. When the length of the reception data is n and the number of the plurality of pattern generation circuits is m, the pattern synchronization pull-in device divides n equally by m, and divides the reception data having a length of n / m equally. Is assigned to each of the plurality of pattern generation circuits,
5. The method according to claim 1, wherein the plurality of pattern generating circuits generate pattern data having a length of n / m using the reception data having a length of n / m. Pattern synchronization pull-in device. The pattern synchronization pull-in device according to any one of claims 1 to 5, wherein the plurality of pattern generation units generate a pseudo random pattern. Enter the received data,
Extract multiple different partial data from the input received data,
Based on each of the plurality of extracted partial data, the plurality of pattern data is generated,
By comparing each of the plurality of generated pattern data with the received data,
A pattern synchronization pull-in method, wherein at least one pattern data synchronized with the received data is detected using a result of the comparison.

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