JP2021145215A - Pattern synchronizing circuit, error rate measuring device employing the same, and pattern synchronizing method - Google Patents

Abstract

To provide a pattern synchronizing circuit capable of easily detecting a head of patterns of any out-of-standard measured signal including SKP OS, an error rate measuring device employing the same, and a pattern synchronizing method.SOLUTION: A pattern synchronizing circuit includes: an SKP detection unit 31 for detecting SKP OS successively from a measured signal in which a tail pattern including SKP OS is repeated (b) times after a head pattern including SKP OS; an SKP OS head flag output unit 32 for outputting an SKP head flag synchronized to a symbol in a head of SKP OS; a tail pattern detection flag output unit 34 for outputting a detection flag indicating that the tail pattern is detected in the case where the number of symbols of the measured signal from a certain SKP head flag to the next SKP head flag coincides with the number of symbols of the tail pattern; and a synchronization completion signal output unit 35 for outputting a synchronization completion signal synchronized to the symbol of the head of SKP OS at the timing when the detection flag is output continuously (b) times.SELECTED DRAWING: Figure 5

Description

The present invention relates to a pattern synchronization circuit, an error rate measuring device using the pattern synchronization circuit, and a pattern synchronization method. In particular, a pattern synchronization circuit for detecting the beginning of a pattern of a signal to be measured, an error rate measuring device using the pattern synchronization circuit, and a pattern. Regarding the synchronization method.

In recent years, with the spread of IoT and cloud computing, communication systems have come to handle a huge amount of data, and the interfaces of various communication devices constituting the communication systems are becoming faster and serial transmission is progressing. In the high speed serial bus (High Speed Serial Bus) standards such as USB (registered trademark) (Universal Serial Bus) and PCIe (registered trademark) (Peripheral Component Interconnect Express) adopted in such communication devices, LTSSM ( A state machine called Link Training and Status State Machine (hereinafter referred to as "link status management mechanism") manages the initialization of communication between devices and the adjustment of link speed.

Then, as one of the indexes for evaluating the quality of signals in communication equipment, the Bit Error Rate (BER), which is defined as a comparison between the number of received data in which bit errors occur and the total number of received data, is known. (See, for example, Patent Document 1). A conventional error rate measuring device that measures BER switches a specific pattern defined by a standard from a pulse pattern generator (PPG) at high speed and outputs it, thereby linking such as PCIe Gen1 to 4 or USB3.1. It has a function (sequence pattern function) that controls the state management mechanism and transitions to a specific state (transition state). The pattern for state transition of the test object (Device Under Test: DUT) is defined by the standard, and the error rate measuring device combines the output order of these patterns with the sequence pattern function and outputs the pattern from PPG. It is designed to do.

For example, in PCIe, the state transition diagram of the link state management mechanism is as shown in FIG. 7, and the states are L0, L0s, L1, L2, Detect, Polling, Configuration, Disabled, Hot Reset, Loopback, and Recovery. It is defined.

In the pattern of transitioning the link state management mechanism to a specific state, the SKP OS (Skip Ordered Set) is inserted between the data patterns at regular intervals in order to prevent data loss or duplication. In order to confirm whether the pattern in which the SKP OS is inserted is correctly transmitted from the DUT in this way, BER measurement is performed. At this time, if the pattern is defined by the standard, the SKP OS interval is uniquely determined, so that the BER measurement can be performed by expanding the pattern in the memory.

In recent years, there has been a demand for a DUT compatible with a high-speed serial bus to perform a state transition of the DUT by forming an arbitrary pattern. The error rate measuring device disclosed in Patent Document 1 is not limited to the pattern defined by the standard, but transmits an arbitrary pattern arbitrarily set by the user to the DUT as a test signal pattern, and receives the object via the DUT. It measures the BER of the pattern of the measurement signal.

Japanese Patent No. 5290213

However, the total pattern length may exceed, for example, 100 Gbit, depending on the setting of the pattern length of the data pattern, the insertion interval and the length of the SKP OS in any pattern for DUT corresponding to the high-speed serial bus. The conventional error rate measuring device as disclosed in Patent Document 1 has a problem that such a long arbitrary pattern cannot be expanded in a memory to perform BER measurement.

In order to perform BER measurement, it is necessary to capture the beginning of the pattern of the signal to be measured. Conventionally, pattern synchronization has been performed by searching the first 64 bits of the data pattern included in the pattern of the signal to be measured. Since the SKP OS is usually a pattern unnecessary for BER measurement, it is not a target for BER measurement. However, when trying to confirm whether the SKP OS is also correctly transmitted from the DUT in an arbitrary pattern, if the insertion interval of the SKP OS is arbitrarily set, the insertion interval is set so that the SKP OS is not inserted in the middle of the data pattern. Is averaged.

As a result, the same pattern including the SKP OS exists in the pattern of the signal to be measured. Therefore, in the method of searching the first 64 bits of the data pattern as in the past, there is a high possibility that the beginning of the pattern is erroneously detected, and there is a problem that BER measurement for an arbitrary pattern becomes impossible.

The present invention has been made to solve such a conventional problem, and is a pattern synchronization circuit capable of easily detecting the beginning of a pattern of any nonstandard measured signal including SKP OS. It is an object of the present invention to provide an error rate measuring device using the same, and a pattern synchronization method.

In order to solve the above problems, the pattern synchronization circuit according to the present invention has a SKP OS (Skip) output from the test object in a state where the link state management mechanism mounted on the test target has transitioned to an arbitrary state. A pattern synchronization circuit that receives a test signal including an Ordered Set) as a signal to be measured and detects the beginning of a pattern of the signal to be measured. In the pattern of the test signal, n SKP OSs are followed by n. After the first pattern followed by the data pattern is repeated a times, the tail pattern followed by m data patterns is repeated b times after one SKP OS, and the SKP OS is sequentially detected from the input signal to be measured. The detection unit, the SKP head flag output unit that outputs the SKP head flag synchronized with the head symbol of the SKP OS detected by the SKP detection unit, and the SKP head flag output unit that outputs the SKP head flag at the first timing. The count unit that counts the number of symbols of the signal under test from the time it is output until the SKP head flag is output at the next second timing, and the number of counts by the count unit are the number of symbols in the tail pattern. When they match, a detection flag indicating that the tail pattern has been detected is output, and when the number of counts by the counting unit does not match the number of symbols of the tail pattern, the tail pattern has not been detected. To the first symbol of the SKP OS at the second timing when the detection flag is output b times in succession from the tail pattern detection flag output unit that outputs the non-detection flag indicating The configuration includes a synchronization completion signal output unit that outputs a synchronized synchronization completion signal.

With this configuration, the pattern synchronization circuit according to the present invention identifies a head pattern in which n data patterns follow the SKP OS and b tail patterns in which m data patterns follow the SKP OS. By detecting the end of the b-th tail pattern, the beginning of the pattern next to the signal to be measured is detected. In this way, the pattern synchronization circuit according to the present invention can easily detect the beginning of the pattern of any nonstandard signal to be measured including the SKP OS.

Further, in the pattern synchronization circuit according to the present invention, the total number of symbols Nh of the data patterns included in the head pattern is a value obtained by multiplying the number Nd of the symbols constituting the data pattern by n, and is included in the tail pattern. The total number of symbols Nt of the data pattern is a value obtained by multiplying the number of symbols Nd constituting the data pattern by m, m is equal to n-1, and the number of symbols Nint indicating the average interval of SKP OS in the test signal is , The value is smaller than the number of symbols Nh and larger than the number of symbols Nt, and the number of repetitions a of the first pattern and the number of repetitions b of the tail pattern in the pattern of the test signal are (Nh-Nint) × a. = (Nint-Nt) × b is the smallest natural number that satisfies.

With this configuration, the pattern synchronization circuit according to the present invention has a pattern of a signal to be measured in which the insertion position of the SKP OS is uniquely determined according to the number of symbols Nd constituting the data pattern and the number of symbols Nint indicating the average interval of the SKP OS. The beginning of the can be easily detected.

Further, the error rate measuring device according to the present invention is an error rate measuring device including any of the above pattern synchronization circuits and an error rate measuring unit for measuring the bit error rate of the signal to be measured. The error rate measuring unit is configured to measure the bit error rate of the pattern of the measured signal synchronized with the synchronization completion signal output from the synchronization completion signal output unit.

With this configuration, the error rate measuring device according to the present invention can measure the BER of the pattern of any nonstandard measured signal including the SKP OS, which is synchronized with the synchronization completion signal output from the pattern synchronization circuit. can. Thereby, the error rate measuring device according to the present invention can measure the operation margin of whether or not the DUT can process an arbitrary nonstandard pattern.

Further, the error rate measuring device according to the present invention has a reference generation circuit that generates a reference pattern that is the same as the pattern of the test signal by using the synchronization completion signal as a trigger, and the measured signal that is synchronized with the synchronization completion signal. A delay circuit that delays the pattern and synchronizes it with the reference pattern output from the reference generation circuit is further provided, and the error rate measuring unit uses the reference pattern output from the reference generation circuit and the delay circuit. By sequentially comparing the output pattern of the signal to be measured, an error bit in the pattern of the signal to be measured may be detected, and the bit error rate of the pattern of the signal to be measured may be calculated. ..

With this configuration, the error rate measuring apparatus according to the present invention generates a reference pattern synchronized with the pattern of the signal to be measured, and compares the pattern of the signal to be measured with the reference pattern to obtain the pattern of the signal to be measured. BER can be measured.

Further, the error rate measuring device according to the present invention further includes a pulse pattern generator for generating the test signal and an operation unit for receiving an operation input, and the number of symbols Nd constituting the data pattern in the test signal. , The number of symbols constituting the SKP OS Nskp, and the number of symbols Nint indicating the average interval of the SKP OS may be set by the operation input to the operation unit.

With this configuration, in the error rate measuring device according to the present invention, the user arbitrarily sets the number of symbols Nd constituting the data pattern, the number of symbols Nskp constituting the SKP OS, and the number of symbols Nint indicating the average interval of the SKP OS. Therefore, it is possible to generate a test signal in which the SKP OS is evenly inserted.

Further, the pattern synchronization method according to the present invention includes a test including a SKP OS (Skip Ordered Set) output from the test target in a state where the link state management mechanism mounted on the test target has transitioned to an arbitrary state. It is a pattern synchronization method that receives a signal as a signal to be measured and detects the head of the pattern of the signal to be measured. In the pattern of the test signal, a head pattern in which n data patterns follow one SKP OS. Is repeated a times, and then the tail pattern in which m data patterns follow one SKP OS is repeated b times, and the SKP detection step of sequentially detecting the SKP OS from the input signal to be measured and the SKP After the SKP head flag output step that outputs the SKP head flag synchronized with the head symbol of the SKP OS detected by the detection step and the SKP head flag output step output the SKP head flag at the first timing, the next When the count step for counting the number of symbols of the signal to be measured until the SKP head flag is output at the second timing and the count number by the count step match the number of symbols of the tail pattern, the said A detection flag indicating that the tail pattern has been detected is output, and when the number of counts by the count step does not match the number of symbols of the tail pattern, a non-detection flag indicating that the tail pattern has not been detected is set. A synchronization completion signal synchronized with the first symbol of the SKP OS at the second timing when the detection flag is continuously output b times from the tail pattern detection flag output step and the tail pattern detection flag output step to be output. The configuration includes a synchronization completion signal output step to be output.

With this configuration, the pattern synchronization method according to the present invention identifies a head pattern in which n data patterns follow SKP OS and b tail patterns in which m data patterns follow SKP OS. By detecting the end of the b-th tail pattern, the beginning of the pattern next to the signal to be measured is detected. In this way, the pattern synchronization method according to the present invention can easily detect the beginning of the pattern of any nonstandard signal to be measured including the SKP OS.

The present invention provides a pattern synchronization circuit that can easily detect the beginning of a pattern of any nonstandard signal to be measured including SKP OS, an error rate measuring device using the pattern synchronization circuit, and a pattern synchronization method. be.

It is a block diagram which shows the structure of the error rate measuring apparatus which concerns on embodiment of this invention. It is a block diagram which shows the structure of PPG provided in the error rate measuring apparatus which concerns on embodiment of this invention. It is a table which shows an example of the correspondence relation between a standard and an encoding type. It is a figure for demonstrating the structure of the test signal output from PPG provided in the error rate measuring apparatus which concerns on embodiment of this invention, and (a) shows the insertion position of SKP OS between the data patterns of a test signal. (B) shows the pattern of the test signal including the head pattern and the tail pattern. It is a block diagram which shows the structure of the pattern synchronization circuit and the reference generation circuit which concerns on embodiment of this invention. It is a flowchart which shows the process of the pattern synchronization method using the pattern synchronization circuit which concerns on embodiment of this invention. It is a figure which shows the state transition of the link state management mechanism.

Hereinafter, a pattern synchronization circuit according to the present invention, an error rate measuring device using the pattern synchronization circuit, and an embodiment of a pattern synchronization method will be described with reference to the drawings.

As shown in FIG. 1, the error rate measuring device 100 according to the present embodiment is an error rate measuring device (Error Detector:) that measures the PPG 10 that outputs a test signal to the DUT 200 and the BER of the signal to be measured output from the DUT 200. ED) 20, a display unit 60, an operation unit 61, and a control unit 62 are provided.

The DUT 200 is equipped with a link state management mechanism, and outputs a test signal input from the PPG 10 as a measured signal of the ED 20 in a state where the link state management mechanism has transitioned to an arbitrary state as shown in FIG. 7, for example. It is designed to (fold back). Examples of the standards supported by the DUT200 include PCIe Gen1 to 4, USB3.1, CEI (Common Electrical Interface), Ethernet (registered trademark), InfiniBand, and the like.

The PPG 10 is designed to generate a test signal to be input to the DUT 200, and has a data storage unit 11, a SKP addition circuit 12, and an encoding circuit 13 as shown in FIG. The data storage unit 11 stores, for example, a data pattern consisting of 4 to 128 symbols, and outputs a plurality of the same data patterns to the SKP addition circuit 12 in sequence. The SKP addition circuit 12 is adapted to generate a pattern in which the SKP OS is inserted between the data patterns sequentially output from the data storage unit 11 according to the control information from the PPG control unit 50 described later.

The encoding circuit 13 encodes the pattern generated by the SKP addition circuit 12 according to the standard. FIG. 3 shows an example of the correspondence between the standard and the type of encoding. One symbol after 8b / 10b encoding is composed of 10 bits, and one symbol after 128b / 130b or 128b / 132b encoding is composed of 8 bits.

Hereinafter, the configuration of the test signal generated by the PPG 10 will be described. In the test signal pattern, the leading pattern in which n data patterns follow one SKP OS is repeated a times, and then the tail pattern in which m data patterns follow one SKP OS is repeated b times. .. For example, when the number of symbols Nd constituting the data pattern is 16 symbols and the number of symbols Nint indicating the average interval of the SKP OS is 36 symbols, the SKP OS is inserted at the SKP insertion position shown in FIG. 4 (a). Then, a pattern of the test signal as shown in FIG. 4 (b) is generated.

The number of symbols Nint is smaller than the total number of symbols Nh of the data patterns included in the head pattern and larger than the total number of symbols Nt of the data patterns included in the tail pattern. In the example of FIG. 4B, the number of symbols Nh and the number of symbols Nt are given by the following equations (1) and (2). Further, the relationship of the following equations (3) to (5) is established.

The number of repetitions a and b is uniquely obtained as the smallest natural number satisfying the equation (4). That is, in the case of the example of FIG. 4 (b), a = 1 and b = 3 from the equation (5). As a result, as shown in FIG. 4B, the SKP OS is inserted between the data patterns once at 48 symbol intervals and three times at 32 symbol intervals.

That is, as in the example of FIG. 4B, when the number of symbols Nint indicating the average interval of the SKP OS in the test signal is not an integral multiple of the number of symbols Nd of the data pattern, the data pattern included in the head pattern The total number of symbols Nh is the value obtained by multiplying the number of symbols Nd by n = ceil (Nint / Nd). Further, the total number of symbols Nt of the data patterns included in the tail pattern is a value obtained by multiplying the number of symbols Nd by m (= n-1).

As shown in FIG. 1, the ED 20 includes a pattern synchronization circuit 30, a reference generation circuit 40, a PPG control unit 50, a delay circuit 51, and an error rate measurement unit 52. For example, in the conventional method of detecting the beginning 64 bits of a data pattern, since there are nine identical data patterns in the pattern of the test signal shown in FIG. 4 (b), the probability that the beginning of the pattern can be correctly captured is simply simple. It is 1/9. On the other hand, the pattern synchronization circuit 30 of the present embodiment is intended to reliably detect the beginning of the pattern of the signal to be measured.

The pattern synchronization circuit 30 receives a test signal including the SKP OS output (folded back) from the DUT 200 as a measured signal in a state where the link state management mechanism mounted on the DUT 200 has transitioned to an arbitrary state, and is measured. The beginning of the signal pattern is detected. As shown in FIG. 5, the pattern synchronization circuit 30 includes a SKP detection unit 31, a SKP head flag output unit 32, a count unit 33, a tail pattern detection flag output unit 34, and a synchronization completion signal output unit 35. include.

The SKP detection unit 31 sequentially detects the SKP OS from the measured signal input from the DUT 200. The SKP OS has a unique pattern and can be searched.

As shown in FIG. 4B, the SKP head flag output unit 32 outputs the SKP head flag synchronized with the head symbol of the SKP OS detected by the SKP detection unit 31.

In the counting unit 33, the SKP head flag output unit 32 outputs the SKP head flag at a certain timing (first timing) until the SKP head flag is output at the next timing (second timing). The number of symbols of the signal under test is counted. Here, the counting unit 33 may count the operating clock of the pattern synchronization circuit 30. For example, when one clock of the operating clock corresponds to one symbol, counting the operating clock is equivalent to counting the number of symbols.

The tail pattern detection flag output unit 34 outputs a detection flag indicating that the tail pattern has been detected when the number of counts by the count unit 33 matches the number of symbols of the tail pattern. For example, in the example of FIG. 4B, when one clock corresponds to one symbol, the counting unit 33 is one before the SKP head flag of the second timing from the symbol of the SKP head flag of the first timing. When 36 clocks are counted up to the symbol of, the tail pattern detection flag output unit 34 outputs the detection flag at the second timing. On the other hand, the tail pattern detection flag output unit 34 outputs a non-detection flag indicating that the tail pattern has not been detected when the number of counts by the count unit 33 does not match the number of symbols of the tail pattern. ing.

The synchronization completion signal output unit 35 uses a synchronization completion signal synchronized with the first symbol of the SKP OS at the second timing when the detection flag is continuously output b times from the tail pattern detection flag output unit 34 as a reference generation circuit. It is designed to output to 40. At the same time, the synchronization completion signal output unit 35 outputs the pattern of the signal to be measured synchronized with the synchronization completion signal to the delay circuit 51. For example, in the example of FIG. 4B, when the tail pattern detection flag output unit 34 outputs the detection flag three times in succession, the synchronization completion signal output unit 35 outputs the synchronization completion signal.

The reference generation circuit 40 uses the synchronization completion signal output from the synchronization completion signal output unit 35 as a trigger to generate a reference pattern that is the same as the pattern of the test signal. That is, the reference generation circuit 40 has the same configuration as the PPG 10, and has a data storage unit 41, a SKP addition circuit 42, and an encoding circuit 43. The data storage unit 41 stores the same data pattern as the data pattern stored in the data storage unit 11 of the PPG 10, and a plurality of the same data patterns are sequentially output to the SKP addition circuit 42. The SKP addition circuit 42 is adapted to generate a pattern in which the SKP OS is inserted between the data patterns sequentially output from the data storage unit 41 according to the control information from the PPG control unit 50 described later. The encoding circuit 43 encodes the pattern generated by the SKP addition circuit 42 according to the standard as shown in FIG.

The PPG control unit 50 instructs the PPG 10 and the reference generation circuit 40 to generate a test signal and a reference pattern, respectively. At this time, the PPG control unit 50 responds to the operation of the operation unit 61 by the user, such as the number of symbols Nd constituting the data pattern, the number of symbols Nskp constituting the SKP OS, and the number of symbols Nint indicating the average interval of the SKP OS. The values are set in PPG 10 and the reference generation circuit 40. For example, Nd can be set in the range of 4 to 128 symbols, and Nskp can be set in the range of 2 to 12 symbols.

The delay circuit 51 delays the pattern of the signal to be measured synchronized with the synchronization completion signal output from the synchronization completion signal output unit 35, and synchronizes it with the reference pattern output from the reference generation circuit 40. The delay amount of the delay circuit 51 is variably set according to values such as the number of symbols Nd constituting the data pattern, the number of symbols Nskp constituting the SKP OS, and the number of symbols Nint indicating the average interval of the SKP OS.

The error rate measuring unit 52 detects an error bit in the pattern of the signal to be measured by sequentially comparing the reference pattern output from the reference generation circuit 40 with the pattern of the signal to be measured output from the delay circuit 51. At the same time, the BER of the pattern of the signal to be measured is calculated.

The display unit 60 is composed of a display device such as an LCD or a CRT, and has an error bit, a BER, or the like of a pattern of the signal to be measured measured by the error rate measuring unit 52 according to the control signal output from the control unit 62. It is designed to display various display contents of. Further, the display unit 60 displays operation targets such as buttons, soft keys, pull-down menus, and text boxes for setting various conditions according to the control signal output from the control unit 62. ..

The operation unit 61 is for receiving an operation input by the user, and is composed of, for example, a touch panel provided on the display unit 60. Alternatively, the operating unit 61 may be configured to include an input device such as a keyboard or mouse. Further, the operation unit 61 may be configured by an external control device that performs remote control by a remote command or the like. The operation input to the operation unit 61 is detected by the control unit 62. For example, the operation unit 61 arbitrarily sets values such as a test signal standard, the number of symbols Nd constituting the data pattern, the number of symbols Nskp constituting the SKP OS, and the number of symbols Nint indicating the average interval of the SKP OS. It is possible to do things like that.

The control unit 62 is composed of, for example, a microcomputer or a personal computer including a CPU, ROM, RAM, HDD, etc., and controls the operation of each of the above units constituting the error rate measuring device 100. Further, the control unit 62 can configure at least a part of the pattern synchronization circuit 30 and the error rate measurement unit 52 by software by transferring a predetermined program stored in the ROM or the like to the RAM and executing the program. be. At least a part of the pattern synchronization circuit 30 and the error rate measuring unit 52 can be configured by a digital circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). Alternatively, at least a part of the pattern synchronization circuit 30 and the error rate measuring unit 52 can be configured by appropriately combining hardware processing by a digital circuit and software processing by a predetermined program.

Hereinafter, an example of the processing of the pattern synchronization method using the pattern synchronization circuit 30 of the present embodiment will be described with reference to the flowchart of FIG.

First, the SKP detection unit 31 sequentially detects the SKP OS from the measured signal input from the DUT 200 (SKP detection step S1).

Next, the SKP head flag output unit 32 outputs the SKP head flag synchronized with the head symbol of the SKP OS detected in the SKP detection step S1 (SKP head flag output step S2).

Next, the counting unit 33 receives the measured signal from the time when the SKP head flag is output at the first timing in the SKP head flag output step S2 until the SKP head flag is output at the next second timing. The number of symbols is counted (count step S3).

Next, the control unit 62 determines whether or not the number of counts in the count step S3 matches the number of symbols in the tail pattern (step S4). If the number of counts in the count step S3 does not match the number of symbols in the tail pattern, the process of step S5 is executed next. On the other hand, when the number of counts in the count step S3 matches the number of symbols in the tail pattern, the process of step S6 is executed next.

In step S5, the tail pattern detection flag output unit 34 outputs a non-detection flag indicating that the tail pattern has not been detected (tail pattern detection flag output step S5). When the process of step S5 is completed, the SKP head flag of interest is shifted by one, and the processes of step S3 and subsequent steps are executed again.

In step S6, the tail pattern detection flag output unit 34 outputs a detection flag indicating that the tail pattern has been detected (tail pattern detection flag output step S6).

Next, the control unit 62 determines whether or not the detection flag is continuously output b times from the tail pattern detection flag output step S6 (step S7). When the detection flag is continuously output b times from the tail pattern detection flag output step S6, the process of step S8 is executed next. On the other hand, when the detection flag is not continuously output b times from the tail pattern detection flag output step S6, the SKP head flag of interest is shifted by one and the processing after step S3 is executed again.

In step S8, the synchronization completion signal output unit 35 outputs a synchronization completion signal synchronized with the first symbol of the SKP OS at the second timing when the detection flag is continuously output b times from the tail pattern detection flag output step S6. Output to the reference generation circuit 40. At the same time, the synchronization completion signal output unit 35 outputs the pattern of the signal to be measured synchronized with the synchronization completion signal to the delay circuit 51 (synchronization completion signal output step S8).

As described above, the insertion position of the SKP OS in the pattern of the signal to be measured is uniquely determined from the number of symbols Nd constituting the data pattern and the number of symbols Nint indicating the average interval of the SKP OS. The pattern synchronization circuit 30 according to the present embodiment identifies a head pattern in which n data patterns follow the SKP OS and b tail patterns in which m data patterns follow the SKP OS. By detecting the end of the third tail pattern, the beginning of the next pattern of the signal to be measured is detected. In this way, the pattern synchronization circuit 30 according to the present embodiment can easily detect the beginning of the pattern of any nonstandard signal to be measured including the SKP OS.

Further, the error rate measuring device 100 according to the present embodiment measures the BER of the pattern of any nonstandard measured signal including the SKP OS, which is synchronized with the synchronization completion signal output from the pattern synchronization circuit 30. Can be done. As a result, the error rate measuring device 100 can measure the operation margin to see if the DUT 200 can process any nonstandard pattern. Conventionally, the BER measurement is usually performed in the Loopback state, but the error rate measuring device 100 according to the present embodiment can perform the BER measurement not only in the loopback state but also in other states.

Further, the error rate measuring device 100 according to the present embodiment generates a reference pattern synchronized with the pattern of the signal to be measured, and compares the pattern of the signal to be measured with the reference pattern to obtain a pattern of the signal to be measured. BER can be measured.

Further, in the error rate measuring device 100 according to the present embodiment, the user arbitrarily sets the number of symbols Nd constituting the data pattern, the number of symbols Nskp constituting the SKP OS, and the number of symbols Nint indicating the average interval of the SKP OS. Therefore, it is possible to generate a test signal in which the SKP OS is evenly inserted.

10 PPG
11,41 Data storage unit 12,42 SKP additional circuit 13,43 Encode circuit 20 ED
30 Pattern synchronization circuit 31 SKP detection unit 32 SKP head flag output unit 33 Count unit 34 Tail pattern detection flag output unit 35 Synchronization completion signal output unit 40 Reference generation circuit 50 PPG control unit 51 Delay circuit 52 Error rate measurement unit 60 Display unit 61 Operation unit 62 Control unit 100 Error rate measuring device 200 DUT

Claims (6)

In a state where the link state management mechanism mounted on the test target has transitioned to an arbitrary state, a test signal including the SKP OS (Skip Ordered Set) output from the test target is received as a test signal, and the test target is tested. A pattern synchronization circuit (30) that detects the beginning of a pattern of a measurement signal.
In the test signal pattern, the leading pattern in which n data patterns follow one SKP OS is repeated a times, and then the tail pattern in which m data patterns follow one SKP OS is repeated b times. NS,
The SKP detection unit (31) that sequentially detects the SKP OS from the input signal to be measured, and
The SKP head flag output unit (32) that outputs the SKP head flag synchronized with the head symbol of the SKP OS detected by the SKP detection unit, and
A counting unit that counts the number of symbols of the signal to be measured between the time when the SKP head flag is output by the SKP head flag output unit at the first timing and the time when the SKP head flag is output at the next second timing. (33) and
When the number of counts by the counting unit matches the number of symbols of the tail pattern, a detection flag indicating that the tail pattern has been detected is output, and the number of counts by the counting unit matches the number of symbols of the tail pattern. A tail pattern detection flag output unit (34) that outputs a non-detection flag indicating that the tail pattern was not detected when the tail pattern is not detected, and a tail pattern detection flag output unit (34).
A synchronization completion signal output unit (35) that outputs a synchronization completion signal synchronized with the first symbol of the SKP OS at the second timing when the detection flag is continuously output b times from the tail pattern detection flag output unit. A pattern synchronization circuit characterized by including. The total number of symbols Nh of the data patterns included in the first pattern is a value obtained by multiplying the number of symbols Nd constituting the data pattern by n.
The total number of symbols Nt of the data patterns included in the tail pattern is a value obtained by multiplying the number of symbols Nd constituting the data pattern by m, and m is equal to n-1.
The number of symbols Nint indicating the average interval of the SKP OS in the test signal is a value smaller than the number of symbols Nh and larger than the number of symbols Nt.
The number of repetitions a of the leading pattern and the number of repetitions b of the tail pattern in the pattern of the test signal are the minimum natural numbers satisfying (Nh-Nint) x a = (Nint-Nt) x b. The pattern synchronization circuit according to claim 1. The pattern synchronization circuit according to claim 1 or 2,
An error rate measuring device (100) including an error rate measuring unit (52) for measuring the bit error rate of the signal to be measured.
The error rate measuring unit is an error rate measuring device that measures the bit error rate of a pattern of the signal to be measured synchronized with the synchronization completion signal output from the synchronization completion signal output unit. A reference generation circuit (40) that generates a reference pattern that is the same as the pattern of the test signal by using the synchronization completion signal as a trigger.
A delay circuit (51) that delays the pattern of the signal to be measured synchronized with the synchronization completion signal and synchronizes with the reference pattern output from the reference generation circuit is further provided.
The error rate measuring unit sequentially compares the reference pattern output from the reference generation circuit with the pattern of the measured signal output from the delay circuit to obtain an error bit in the pattern of the measured signal. The error rate measuring device according to claim 3, further comprising detecting and calculating the bit error rate of the pattern of the signal to be measured. The pulse pattern generator (10) that generates the test signal and
Further equipped with an operation unit (61) for receiving operation input,
The test signal is characterized in that the number of symbols Nd constituting the data pattern, the number of symbols Nskp constituting the SKP OS, and the number of symbols Nint indicating the average interval of the SKP OS are set by an operation input to the operation unit. The error rate measuring device according to claim 3 or 4. In a state where the link state management mechanism mounted on the test target has transitioned to an arbitrary state, a test signal including the SKP OS (Skip Ordered Set) output from the test target is received as a test signal, and the test target is tested. It is a pattern synchronization method that detects the beginning of the pattern of the measurement signal.
In the test signal pattern, the leading pattern in which n data patterns follow one SKP OS is repeated a times, and then the tail pattern in which m data patterns follow one SKP OS is repeated b times. NS,
The SKP detection step (S1) for sequentially detecting the SKP OS from the input signal to be measured, and
The SKP head flag output step (S2) that outputs the SKP head flag synchronized with the head symbol of the SKP OS detected by the SKP detection step, and
A count step for counting the number of symbols of the signal to be measured from the time when the SKP head flag is output at the first timing to the time when the SKP head flag is output at the next second timing by the SKP head flag output step. (S3) and
When the number of counts by the count step matches the number of symbols of the tail pattern, a detection flag indicating that the tail pattern has been detected is output, and the number of counts by the count step matches the number of symbols of the tail pattern. In the tail pattern detection flag output step (S5, S6), which outputs a non-detection flag indicating that the tail pattern was not detected when the tail pattern is not detected,
A synchronization completion signal output step (S8) that outputs a synchronization completion signal synchronized with the first symbol of the SKP OS at the second timing when the detection flag is continuously output b times from the tail pattern detection flag output step (S8). And, a pattern synchronization method characterized by including.

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