JP4558004B2 - Electronic components, shield covers, mother boards for multi-cavity, wiring boards and electronic equipment - Google Patents

Electronic components, shield covers, mother boards for multi-cavity, wiring boards and electronic equipment Download PDF

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JP4558004B2
JP4558004B2 JP2007136291A JP2007136291A JP4558004B2 JP 4558004 B2 JP4558004 B2 JP 4558004B2 JP 2007136291 A JP2007136291 A JP 2007136291A JP 2007136291 A JP2007136291 A JP 2007136291A JP 4558004 B2 JP4558004 B2 JP 4558004B2
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hole
shield cover
electronic component
board
substrate
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JP2007258741A (en
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修一 立和名
宏三 松川
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Kyocera Corp
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本発明は、携帯電話機やパーソナルコンピュータ等の通信機器、電子機器に組み込まれて使用される電子部品及びその製造方法に関するものである。   The present invention relates to a communication device such as a mobile phone or a personal computer, an electronic component used by being incorporated in an electronic device, and a manufacturing method thereof.

従来より、携帯電話機等の通信機器、電子機器等に種々の電気回路を備えた電子部品が用いられている。   2. Description of the Related Art Conventionally, electronic components including various electric circuits have been used in communication devices such as mobile phones, electronic devices, and the like.

かかる従来の電子部品としては、例えば図8に示す如く、複数個の絶縁層を積層してなる略矩形状の多層配線基板51の内部にストリップ線路やグランド配線等の内部配線導体(図示せず)を埋設するとともに、多層配線基板51の上面にチップコンデンサやダイオード等の各種電子部品素子(図示せず)を搭載し、これらを金属製のシールドカバー52で被覆した構造のものが知られている。   As such a conventional electronic component, for example, as shown in FIG. 8, an internal wiring conductor (not shown) such as a strip line or a ground wiring is formed inside a substantially rectangular multilayer wiring board 51 formed by laminating a plurality of insulating layers. ) Is embedded, and various electronic component elements (not shown) such as chip capacitors and diodes are mounted on the upper surface of the multilayer wiring board 51, and these are covered with a metal shield cover 52. Yes.

前記シールドカバー52は、矩形状の天板52aと天板52aの外周部に設けられた側壁52bと、天板52aの各辺の中心位置に対応して配され側壁52bの下端部に立設される4個の接合脚部52cとから構成されている。   The shield cover 52 has a rectangular top plate 52a, a side wall 52b provided on the outer periphery of the top plate 52a, and is arranged corresponding to the center position of each side of the top plate 52a. And four joint legs 52c.

そして、シールドカバー52の多層配線基板51への取り付けは、多層配線基板51の側面に形成された複数個の端面スルーホール54のうち、多層配線基板51の各辺の中心位置に形成された4個の各端面スルーホール54に前記4個の接合脚部52cを1個ずつ収容した上、接合脚部52cと端面スルーホール54の内面に被着された端面電極導体55とを半田を介して接合させることにより行われる。   Then, the shield cover 52 is attached to the multilayer wiring board 51 at the center position of each side of the multilayer wiring board 51 among the plurality of end surface through holes 54 formed on the side surface of the multilayer wiring board 51. The four joint legs 52c are accommodated one by one in each end face through hole 54, and the joint leg 52c and the end face electrode conductor 55 attached to the inner surface of the end face through hole 54 are connected via solder. This is done by bonding.

前記端面スルーホール54は、多層配線基板51の上面から下面にかけて多層配線基板51の側面を貫くようにして形成されており、その内面には全体にわたって端面電極導体55が被着されている。これらの端面電極導体55は、電子部品50をマザーボードに実装する際、マザーボード側の接続パッドと半田を介して接続されるようになっている。   The end surface through hole 54 is formed so as to penetrate the side surface of the multilayer wiring substrate 51 from the upper surface to the lower surface of the multilayer wiring substrate 51, and the end surface electrode conductor 55 is deposited on the entire inner surface. These end face electrode conductors 55 are connected to connection pads on the motherboard side via solder when the electronic component 50 is mounted on the motherboard.

尚、接合脚部52cが収容される4個の端面スルーホール54に被着された端面電極導体55はグランド端子として機能し、電子部品の使用時、シールドカバー52がグランド電位に保持されるようになっている。 Note that the end surface electrode conductor 55 attached to the four end surface through holes 54 in which the joint legs 52c are accommodated functions as a ground terminal so that the shield cover 52 is held at the ground potential when the electronic component is used. It has become.

これによって、外部からの電磁波を遮蔽して回路を安定して動作させることができる。 Thus, the circuit can be stably operated by shielding electromagnetic waves from the outside.

次に上述した従来の電子部品の製造方法について説明する。   Next, a method for manufacturing the above-described conventional electronic component will be described.

かかる従来の電子部品の製造方法としては、複数個の基板領域に区画された大型の母基板を分割することにより個々の電子部品を得る多数個取りの手法が用いられており、以下に示すように、基板領域間に捨代領域を設ける場合と捨代領域を設けない場合とがある。 As a method for manufacturing such a conventional electronic component, a multi-cavity method is used in which individual electronic components are obtained by dividing a large mother board partitioned into a plurality of substrate regions, as shown below. In addition, there is a case where a margin area is provided between the substrate areas and a case where a margin area is not provided.

まず、基板領域間に捨代領域を設ける場合ついて図9を用いて説明する。   First, a case where a marginal area is provided between the substrate areas will be described with reference to FIG.

図9の(a)は、母基板100にシールドカバー52を載置した状態の平面図、(b)は図9(a)のa‐a’線における断面図である。 9A is a plan view of a state in which the shield cover 52 is placed on the mother board 100, and FIG. 9B is a cross-sectional view taken along the line a-a 'of FIG. 9A.

尚、図9の(a)では、母基板の一部にシールドカバー52を載置した状態を示してある。 9A shows a state where the shield cover 52 is placed on a part of the mother board.

かかる電子部品の製造方法は、まず、間に捨代領域102を挟んでマトリクス状に配列された基板領域を有する母基板100を準備し、基板領域外周辺の中心部に、基板領域と捨代領域間の境界103を跨ぐようにして貫通孔101を形成した後、貫通孔内面にメッキ処理を施すことにより導体膜104を被着させる。次に、貫通孔101の内部にクリーム半田106を充填するとともに、各基板領域に電子部品素子105を搭載する。その後、シールドカバー52を複数個準備し、各貫通孔101にシールドカバー52の接合脚部52cを1個ずつ挿入するとともにクリーム半田105を溶融して硬化することにより接合脚部52cを貫通孔内面に被着した導体膜104に接合する。最後に境界103に沿って母基板100を切断することにより、図8に示すような個々の電子部品が得られる(例えば、特許文献1参照。)。   In this method of manufacturing an electronic component, first, a mother board 100 having a substrate area arranged in a matrix with a marginal area 102 interposed therebetween is prepared, and the substrate area is abandoned at the center outside the substrate area. After the through hole 101 is formed so as to straddle the boundary 103 between the regions, the conductor film 104 is deposited by plating the inner surface of the through hole. Next, cream solder 106 is filled into the through hole 101 and the electronic component element 105 is mounted on each substrate region. After that, a plurality of shield covers 52 are prepared, and one joint leg 52c of the shield cover 52 is inserted into each through hole 101 one by one, and the solder paste 105 is melted and hardened to form the joint leg 52c inside the through hole. Bonded to the conductor film 104 deposited on the substrate. Finally, the mother board 100 is cut along the boundary 103 to obtain individual electronic components as shown in FIG. 8 (see, for example, Patent Document 1).

次に、基板領域間に捨代領域を設けない場合について図10を用いて説明する。図10の(a)は、母基板100にシールドカバー52を載置した状態の平面図、(b)は図10(a)のa‐a’線における断面図である。尚、図10の(a)では、母基板の一部にシールドカバー52を載置した状態を示してある。   Next, a case where no surplus area is provided between the substrate areas will be described with reference to FIG. FIG. 10A is a plan view of a state in which the shield cover 52 is placed on the mother board 100, and FIG. 10B is a cross-sectional view taken along the line a-a 'in FIG. FIG. 10A shows a state where the shield cover 52 is placed on a part of the mother board.

かかる電子部品の製造方法は、まず、間に捨代領域を設けることなく基板領域間を近接配置させた複数個の基板領域を有する母基板100を準備した後、基板領域外周辺の中心部に、隣接する基板領域間の境界103を跨ぐようにして貫通孔101を形成する。次に、貫通孔101の内部にクリーム半田106を充填するとともに、各基板領域に電子部品素子105を搭載する。次に、上述したシールドカバー52を複数個準備し、これらのシールドカバー52を母基板100の対応する基板領域上に載置した上、隣り合うシールドカバー52の隣接する接合脚部同士を同一の貫通孔101に挿入し、しかる後、クリーム半田106を溶融して硬化することにより接合脚部52cを貫通孔内面に被着した導体膜104に半田接合する。最後に境界103に沿って母基板100を切断することにより、個々の電子部品が得られる(例えば、特許文献2参照。)。
特開平10−13078号公報 特開平11−31893号公報
In such an electronic component manufacturing method, first, a mother substrate 100 having a plurality of substrate regions in which substrate regions are arranged close to each other without providing a marginal region therebetween is prepared, and then is formed at a central portion outside the substrate region. The through hole 101 is formed so as to straddle the boundary 103 between the adjacent substrate regions. Next, the solder paste 106 is filled in the through hole 101 and the electronic component element 105 is mounted on each substrate region. Next, a plurality of the shield covers 52 described above are prepared, and these shield covers 52 are placed on the corresponding substrate regions of the mother board 100, and the adjacent joint legs of the adjacent shield covers 52 are made the same. After inserting into the through hole 101 and then melting and hardening the cream solder 106, the joint leg 52c is soldered to the conductor film 104 attached to the inner surface of the through hole. Finally, by cutting the mother board 100 along the boundary 103, individual electronic components are obtained (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 10-13078 Japanese Patent Laid-Open No. 11-31893

ところで上述した従来の電子部品は、シールドカバー52の側壁52bの下端部に立設される接合脚部52cが、天板52aの各辺の中心に配されるようにして設けられている。従って、接合脚部52cが収容される多層配線基板側面に形成される端面スルーホール54は、多層配線基板51の各辺の中心位置に形成されることになる。このような電子部品では、複数の基板領域を有する母基板100を用いて電子部品を多数個取りする際、以下のような問題が発生する。   By the way, the conventional electronic component described above is provided such that the joint leg portion 52c standing at the lower end portion of the side wall 52b of the shield cover 52 is arranged at the center of each side of the top plate 52a. Therefore, the end surface through hole 54 formed on the side surface of the multilayer wiring board in which the joining leg portion 52 c is accommodated is formed at the center position of each side of the multilayer wiring board 51. In such an electronic component, the following problems occur when a large number of electronic components are taken using the mother board 100 having a plurality of substrate regions.

まず、母基板100の基板領域間に捨代領域102を設ける場合は、シールドカバー52の接合脚部52cが収容される端面スルーホール54が多層配線基板51の各辺の中心位置に形成されていると、隣接する貫通孔同士が母基板100の一辺に対し平行に並んで配置されることになる。この場合、捨代領域102の幅dを狭めると隣接する貫通孔部同士が接触してしまうことになるため、貫通孔部同士が接触しないように捨代領域の幅dを広げて捨代領域内にある2個の貫通孔間に充分な間隔を設けなければならない。その結果、母基板100に占める捨代領域102の割合が増加し、1つの母基板から取得できる電子部品の個数が減ってしまうため電子部品の生産効率が低下してしまうという問題が起こる。   First, in the case where the separation region 102 is provided between the substrate regions of the mother substrate 100, the end surface through hole 54 that accommodates the joining leg portion 52 c of the shield cover 52 is formed at the center position of each side of the multilayer wiring substrate 51. If so, the adjacent through holes are arranged in parallel to one side of the mother board 100. In this case, if the width d of the marginal area 102 is narrowed, adjacent through-hole portions will come into contact with each other. Therefore, the width d of the marginalization region is widened so that the through-hole portions do not contact each other. A sufficient space must be provided between the two through holes inside. As a result, the ratio of the abandoned area 102 occupying the mother board 100 is increased, and the number of electronic components that can be acquired from one mother board is reduced, resulting in a problem that the production efficiency of the electronic parts is lowered.

一方、母基板100の基板領域間に捨代領域102を設けない場合、母基板100により多くの基板領域を確保することができるので、上述した基板領域に捨代領域を設けた場合に起こる問題は解消される。しかしながら、この場合、基板領域間の境界103を跨ぐようにして形成された1個の貫通孔101に対し、隣接するシールドカバー52の接合脚部同士が挿入されることになる。このように1個の貫通孔101に対して、別々のシールドカバー52の接合脚部52cが挿入されると、貫通孔101に充填されたクリーム半田を溶融した際、シールドカバー間の半田濡れ性の違いによって接合脚部52cに付着する半田の量に違いが生じる。その結果、隣接するシールドカバー52のうち半田濡れ性の低いシールドカバー側では、接合脚部52cに付着する半田の量が不足し、シールドカバー52の接続強度が低下してしまう。その結果、電子部品に衝撃が加わった際や熱応力が印加された際にシールドカバー52が簡単にはずれる等して電子部品の信頼性が低下してしまうという問題が発生する。また、隣接するシールドカバー52のうち半田濡れ性の高いシールドカバー側では、接合脚部52cに付着する半田が過剰に供給されることになる。従って、適量を超える余分な半田によって多層配線基板上の配線間、或いは、シールドカバー52と他の配線との間で短絡を起こす等して電子部品の生産性が低下するという問題が発生する。 On the other hand, when the replacement area 102 is not provided between the substrate areas of the mother board 100, a larger number of board areas can be secured in the mother board 100. Therefore, a problem that occurs when the above-described board area is provided with a replacement area. Is resolved. However, in this case, the joining leg portions of adjacent shield covers 52 are inserted into one through hole 101 formed so as to straddle the boundary 103 between the substrate regions. Thus with respect to one through-hole 101, the joint leg 5 2c separate shield cover 52 is inserted, when the molten solder paste filled in the through hole 101, solder wetting between the shield cover Differences in the amount of solder adhering to the joining leg portion 52c occur due to differences in properties. As a result, on the shield cover side having low solder wettability among the adjacent shield covers 52, the amount of solder adhering to the joint leg 52c is insufficient, and the connection strength of the shield cover 52 is reduced. As a result, there arises a problem that the reliability of the electronic component is lowered due to the shield cover 52 being easily removed when an impact is applied to the electronic component or when a thermal stress is applied. Further, on the shield cover side having high solder wettability among the adjacent shield covers 52, the solder adhering to the joining leg portion 52c is excessively supplied. Therefore, there arises a problem that the productivity of the electronic component is lowered by causing a short circuit between the wirings on the multilayer wiring board or between the shield cover 52 and the other wirings by an excessive amount of solder.

本発明は上記問題に鑑み案出されたもので、その目的は、電子部品を多数個取りする際、基板領域間に捨代領域を設ける設けないにかかわらず、シールドカバーの接続信頼性を高く維持することができるとともに、生産性にも優れた電子部品及びその製造方法を提供することにある。   The present invention has been devised in view of the above problems. The purpose of the present invention is to increase the connection reliability of the shield cover regardless of whether or not to provide a spare area between board areas when a large number of electronic components are taken. An object of the present invention is to provide an electronic component that can be maintained and that is excellent in productivity and a method for manufacturing the same.

本発明の多数個取り用母基板は、電子部品を多数個取りするためのものであって、列状に配置された矩形状をなす複数の基板領域を有し、隣接する基板領域の境界部には、少なくとも一方の基板領域の外周辺を跨ぐようにして形成された円形状の一方の孔部と、少なくとも他方の基板領域の外周辺を跨ぐようにして形成された円形状の他方の孔部とが独立して形成されており、前記一方の孔部と前記他方の孔部とが、前記境界部の中央点に対し略点対称の位置に配されており、前記境界部を挟んで隣接している基板領域の外周辺には、前記一方の孔部および前記他方の孔部の配置箇所の各々と対向する位置に孔部が存在しないことを特徴とする。 The multi-chip mother board of the present invention is for picking up a large number of electronic components, and has a plurality of rectangular substrate areas arranged in a row, and a boundary portion between adjacent board areas. Includes one circular hole formed so as to straddle the outer periphery of at least one substrate region, and the other circular hole formed so as to straddle the outer periphery of at least the other substrate region. Are formed independently of each other, and the one hole and the other hole are arranged at a substantially point-symmetrical position with respect to the center point of the boundary, and sandwich the boundary In the outer periphery of the adjacent substrate region, no hole is present at a position facing each of the arrangement positions of the one hole and the other hole.

本発明の多数個取り用母基板は、前記一方の孔部と前記他方の孔部との中心間の距離が、これらの孔部の直径よりも大きいこと特徴とする請求項1に記載多数個取り用母基板。 Multi-piece for the mother board of the present invention, the distance between the centers of the said one of the holes and the other hole portion, according to claim 1, characterized in that larger than the diameter of these holes Mother board for multi-cavity .

本発明によれば、シールドカバーを構成する矩形状の天板の対向辺に設けられた一対の脚部を、天板を平面視した際の図心に対し略点対称で、且つ前記対向辺の各中心より所定方向にずらした位置に配していることから、電子部品を多数個取りする際、母基板の基板領域間に捨代領域を有する場合には、従来と比し捨代領域の幅dを大幅に縮小させることが可能となる。すなわち、隣接する基板領域間で一方の孔部と他方の孔部とが、境界部の中央点に対し略点対称に位置するように配されていることから、両孔部が接触することなく捨代領域の幅dを狭めることができるようになる。その結果、母基板に占める捨代領域の割合を減らして、その分基板領域を多く確保できるので、1個の母基板から取得できる電子部品の個数を増加させて、電子部品の生産性を向上させることができるようになる。また、基板領域間に捨代領域を有しない場合には、シールドカバーの取り付けにあたって、隣接するシールドカバーの脚部を別個の貫通孔に挿入することができる。   According to the present invention, the pair of legs provided on the opposing sides of the rectangular top plate constituting the shield cover is substantially point-symmetric with respect to the centroid when the top plate is viewed in plan, and the opposing sides Since there is a spare area between the board areas of the mother board when picking up a large number of electronic components, the spare area is smaller than the conventional area. Width d can be greatly reduced. That is, between the adjacent substrate regions, one hole and the other hole are arranged so as to be substantially point-symmetric with respect to the center point of the boundary portion, so that both holes do not contact each other. The width d of the abandonment area can be reduced. As a result, the ratio of the abandoned area to the mother board is reduced, and as a result, a larger board area can be secured, thereby increasing the number of electronic parts that can be acquired from one mother board and improving the productivity of electronic parts. To be able to. Moreover, when there is no surplus area between board | substrate area | regions, when attaching a shield cover, the leg part of an adjacent shield cover can be inserted in a separate through-hole.

以下、本発明を添付図面に基づいて詳細に説明する。尚、本実施形態においては電子部品として電圧制御型発振器を例に説明する。   Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the present embodiment, a voltage controlled oscillator will be described as an example of the electronic component.

図1は、本発明の電子部品の斜視図であり、図2の(a)、(b)はそれぞれ、図1に示す電子部品をA方向、B方向から見たときの側面図、図3は図1に示す電子部品のC‐C’線の断面図である。同図に示す電子部品は、大略的に多層配線基板1とシールドカバー2とで構成されている。   FIG. 1 is a perspective view of an electronic component according to the present invention. FIGS. 2A and 2B are side views of the electronic component shown in FIG. 1 when viewed from the A direction and the B direction, respectively. FIG. 2 is a cross-sectional view taken along line CC ′ of the electronic component shown in FIG. 1. The electronic component shown in the figure is generally composed of a multilayer wiring board 1 and a shield cover 2.

前記多層配線基板1は、図3に示す如く、複数個の絶縁層1a〜1cを厚み方向に積層してなる略矩形状の積層体により構成されており、これらの絶縁層間にはグランド配線やストリップ線路、内部配線導体等、多数の内部配線導体5が介在され、これらの内部配線導体5を絶縁層中に埋設されるビアホール導体6等を介して相互に電気的に接続させている。   As shown in FIG. 3, the multilayer wiring board 1 is constituted by a substantially rectangular laminated body in which a plurality of insulating layers 1a to 1c are laminated in the thickness direction. Between these insulating layers, ground wiring or A number of internal wiring conductors 5 such as strip lines and internal wiring conductors are interposed, and these internal wiring conductors 5 are electrically connected to each other through via-hole conductors 6 embedded in an insulating layer.

また多層配線基板1の上面には、チップコンデンサ、ダイオード、トランジスタ等の電圧制御型発振器の回路を構成する各種電子部品素子7が搭載されている。これらの電子部品素子7は半田等の導電性接着剤や金属細線等のボンディング材を介して多層配線基板上面に形成された表面配線導体(図示せず)と電気的に接続されている。更に表面配線導体と内部配線導体5とがビアホール導体等を介して電気的に接続されることにより所定の電気回路が構成されている。   On the upper surface of the multilayer wiring board 1, various electronic component elements 7 constituting a voltage-controlled oscillator circuit such as a chip capacitor, a diode, and a transistor are mounted. These electronic component elements 7 are electrically connected to a surface wiring conductor (not shown) formed on the upper surface of the multilayer wiring board via a conductive adhesive such as solder or a bonding material such as a fine metal wire. Furthermore, a predetermined electric circuit is configured by electrically connecting the surface wiring conductor and the internal wiring conductor 5 via a via-hole conductor or the like.

このような多層配線基板1を構成する絶縁層1を構成する絶縁層1a〜1cの材料としては、例えばガラスセラミック等のセラミック材料が用いられ、個々の絶縁層の厚みは例えば50μm〜300μmに設定される。   As a material of the insulating layers 1a to 1c constituting the insulating layer 1 constituting such a multilayer wiring substrate 1, a ceramic material such as glass ceramic is used, and the thickness of each insulating layer is set to 50 μm to 300 μm, for example. Is done.

尚、前記多層配線基板1は、絶縁層がセラミック材料からなる場合、セラミック原料の粉末に適当な有機溶剤、有機溶媒等を添加・混合して得たセラミックグリーンシートを所定枚数だけ積層した上、これをプレス成形し、しかる後、この積層体を高温で焼成し、外形加工することによって製作される。   In addition, when the insulating layer is made of a ceramic material, the multilayer wiring board 1 is obtained by laminating a predetermined number of ceramic green sheets obtained by adding and mixing an appropriate organic solvent, an organic solvent, etc. to the ceramic raw material powder. It is manufactured by press-molding this, and then firing the laminate at a high temperature and processing the outer shape.

また、多層回路基板1に設けられる内部配線導体5や表面配線導体等は銀や銅等の導電材料から成り、その厚みは、例えば5μm〜30μmに設定される。尚、ビアホール導体も同様に銀や銅等の導電材料から成り、その直径は、例えば20μm〜100μmに設定される。   The internal wiring conductor 5 and the surface wiring conductor provided on the multilayer circuit board 1 are made of a conductive material such as silver or copper, and the thickness thereof is set to, for example, 5 μm to 30 μm. The via-hole conductor is similarly made of a conductive material such as silver or copper, and its diameter is set to 20 μm to 100 μm, for example.

これら内部配線導体5や表面配線導体は、多層配線基板1を製作する際、セラミックグリーンシートを積層する前に、銀等の導電材粉末を含む導体ペーストを従来周知のスクリーン印刷によって各セラミックグリーンシートの表面に所定パターンに印刷・塗布しておき、これをセラミックグリーンシートの焼成時に同時焼成することにより形成される。   When the multilayer wiring board 1 is manufactured, the internal wiring conductors 5 and the surface wiring conductors are formed by applying a conductive paste containing conductive material powder such as silver or the like by conventional screen printing before the ceramic green sheets are laminated. It is formed by printing / coating a predetermined pattern on the surface of the ceramic and simultaneously firing the ceramic green sheet.

尚、ビアホール導体6は、セラミックグリーンシートに予め設けておいた貫通孔の内部にスクリーン印刷等によって導電ペーストを塗布・充填しておき、これをセラミックグリーンシートの焼成時に同時焼成することにより形成される。   The via-hole conductor 6 is formed by applying and filling a conductive paste by screen printing or the like in a through-hole previously provided in the ceramic green sheet, and simultaneously firing the ceramic green sheet at the time of firing. The

一方、多層配線基板1の下面には、各種端子電極8が設けられている。本実施形態においては、8個の端子電極が設けられており、下面の各辺中央部にはグランド端子として機能する4個の端子電極が、下面四隅部には、入力端子、出力端子、電源端子、信号制御端子として機能する端子電極が形成されている。これらの端子電極8は、例えば、銀や銅等の導電性材料からなり、個々の端子電極8の厚みは、例えば5μm〜20μmに設定される。   On the other hand, various terminal electrodes 8 are provided on the lower surface of the multilayer wiring board 1. In the present embodiment, eight terminal electrodes are provided, four terminal electrodes functioning as ground terminals are provided at the center of each side of the lower surface, and input terminals, output terminals, power supplies are provided at the lower four corners. Terminal electrodes functioning as terminals and signal control terminals are formed. These terminal electrodes 8 are made of, for example, a conductive material such as silver or copper, and the thickness of each terminal electrode 8 is set to, for example, 5 μm to 20 μm.

このような多層配線基板1の側面には、後述するシールドカバー2に設けられている接合脚部2bを収容するための切り欠き部4が形成されている。この切り欠き部4は、多層配線基板の最上層に配置された絶縁層1aの端面にスルーホールを設け、2層目の絶縁層1bの上面を露出させることによって形成されている。すなわち、この切り欠き部4は、積層方向の深さが絶縁層1aの厚み分に相当し、その上端が多層配線基板1の上面に開口するとともに、下端が絶縁層1bの上面と対応する高さに位置することになる。このようにして切り欠き部4を形成しておけば、切り欠き部4を多層配線基板の側面を貫くようにして形成した場合に比し、絶縁層1b、1cの切り欠き部4の下方領域にも内部配線導体やビアホール導体等を設けるスペースを確保できるため、多層配線基板1の内部を配線の引き回しのために有効利用することができる。   On the side surface of the multilayer wiring board 1, a notch 4 is formed for accommodating a joint leg 2 b provided on a shield cover 2 described later. The notch 4 is formed by providing a through hole in the end surface of the insulating layer 1a disposed on the uppermost layer of the multilayer wiring board and exposing the upper surface of the second insulating layer 1b. That is, the notch 4 has a depth in the stacking direction corresponding to the thickness of the insulating layer 1a, the upper end of which opens on the upper surface of the multilayer wiring board 1, and the lower end of the notch 4 corresponds to the upper surface of the insulating layer 1b. Will be located. If the notch 4 is formed in this way, the region below the notch 4 of the insulating layers 1b and 1c is compared with the case where the notch 4 is formed so as to penetrate the side surface of the multilayer wiring board. In addition, since a space for providing an internal wiring conductor, a via-hole conductor, and the like can be secured, the inside of the multilayer wiring board 1 can be effectively used for wiring.

また、切り欠き部4によって露出する絶縁層2bの上面には接合用導体5aが導出されている。この接合用導体5aは、シールドカバー2を多層配線基板1に機械的・電気的に接続するためのもので、シールドカバー2の接合脚部2bと半田3を介して接続されるようになっており、この接合用導体5aを多層配線基板1の下面に設けたグランド端子にビアホール導体等を介して電気的に接続しておくことにより、電子部品の使用時、シールドカバー2をグランド電位に保持することができるようになる。このようにシールドカバー2の接合脚部2bを接続するための導体を、メッキ処理等の煩雑な工程を行うことなく、多層配線基板内部に埋設した接合用導体5aを切り欠き部4から露出させることにより簡単に形成することができるため、電子部品の生産性を向上させること可能となる。   A bonding conductor 5a is led out on the upper surface of the insulating layer 2b exposed by the notch 4. The bonding conductor 5a is for mechanically and electrically connecting the shield cover 2 to the multilayer wiring board 1, and is connected to the bonding leg 2b of the shield cover 2 via the solder 3. The bonding conductor 5a is electrically connected to a ground terminal provided on the lower surface of the multilayer wiring board 1 via a via-hole conductor or the like so that the shield cover 2 is held at the ground potential when the electronic component is used. Will be able to. Thus, the conductor for connecting the joining leg 2b of the shield cover 2 is exposed from the cutout portion 4 without being subjected to a complicated process such as plating. Therefore, the productivity of electronic parts can be improved.

尚、切り欠き部4は、例えば半円柱状をなし、その横幅は切り欠き部4が形成される多層配線基板側面の横幅の半分以下に設定される。   The notch 4 has, for example, a semi-cylindrical shape, and its lateral width is set to be equal to or less than half the lateral width of the side surface of the multilayer wiring board on which the notch 4 is formed.

一方、多層配線基板上には電子部品素子7を覆うようにしてシールドカバー2が載置されている。このシールドカバー2は、矩形状の平板から成る天板2aと、天板2aの外周部に立設される一対の接合脚部2b及び一対の当接脚部2cとから構成される。   On the other hand, the shield cover 2 is placed on the multilayer wiring board so as to cover the electronic component element 7. The shield cover 2 includes a top plate 2a made of a rectangular flat plate, and a pair of joining leg portions 2b and a pair of contact leg portions 2c that are erected on the outer peripheral portion of the top plate 2a.

図4はシールドカバー2を多層配線基板への載置面側から見た平面図であり、前記一対の接合脚部2bは、天板2aの二組の対向辺のうち一方の対向辺にのみ配されており、一対の接合脚部2b同士が、天板2aを平面視した際の図心Gの中心に対し略点対称で、且つ対向辺の各中心M1〜M4より所定方向にずらすようにして配置されている。ここで、平板2aを平面視した際の図心とは天板2aの対角線の交点を指す。   FIG. 4 is a plan view of the shield cover 2 as viewed from the surface on which the multilayer wiring board is placed, and the pair of joint legs 2b are only on one of the two opposing sides of the top plate 2a. The pair of joint legs 2b are substantially point-symmetric with respect to the center of the centroid G when the top plate 2a is viewed in plan, and are shifted in a predetermined direction from the centers M1 to M4 of the opposite sides. Are arranged. Here, the centroid when the flat plate 2a is viewed in plan refers to the intersection of diagonal lines of the top plate 2a.

このように接合脚部2bを天板2aの二組の対向辺のうち一方の対向辺にのみ配していることから、接合脚部2を収容するための切り欠き部4を多層配線基板1の一対の側面にのみ形成すればよく、多層配線基板1に形成する切り欠き部4の個数を減らして、多層配線基板1の内部や上面に配線導体を形成するためのスペースや電子部品素子を搭載するためのスペースが充分に確保され、電子部品を小型化することができる。 Because it is coordinated only such bonded leg 2b to the one of the opposing sides of the two pairs of opposing sides of the top plate 2a, a multilayer wiring board notches 4 for accommodating the joint leg 2 b The number of notches 4 formed in the multilayer wiring board 1 is reduced, and a space or an electronic component element for forming a wiring conductor inside or on the upper surface of the multilayer wiring board 1 is sufficient. The space for mounting is sufficiently secured, and the electronic component can be miniaturized.

また、接合脚部2bの配されていない他の対向辺には、多層配線基板1の上面に当接される一対の当接脚部2cが立設されている。この当接脚部2cは、天板2aの図心に対し略点対称に配されており、シールドカバー2を取り付ける際、シールドカバー2が傾くのを有効に防止して、シールドカバー2を安定した状態で多層配線基板1に取着させることができる。   In addition, a pair of contact legs 2 c that are in contact with the upper surface of the multilayer wiring board 1 are provided upright on the other opposing side where the joining legs 2 b are not arranged. The contact legs 2c are arranged substantially symmetrically with respect to the centroid of the top plate 2a, and when the shield cover 2 is attached, the shield cover 2 is effectively prevented from being tilted to stabilize the shield cover 2. In this state, it can be attached to the multilayer wiring board 1.

更に、前記一対の接合脚部2b及び一対の当接脚部2cを、天板2aの各辺の中点から天板2aの外周辺に沿って反時計回りに略等距離tだけずらした位置に配しておくことにより、シールドカバー2をより安定した状態で多層配線基板1に取着させることができる。   Further, the position where the pair of joint legs 2b and the pair of contact legs 2c are shifted by a substantially equal distance t from the midpoint of each side of the top plate 2a counterclockwise along the outer periphery of the top plate 2a. The shield cover 2 can be attached to the multilayer wiring board 1 in a more stable state.

このようなシールドカバー2は、例えば42アロイやコバール、リン青銅、鉄等の金属材料によって、天板2aが多層配線基板1の外形より若干小さめの矩形状をなすように、従来周知の金属加工法にて製作される。   Such a shield cover 2 is made of a known metal processing so that the top plate 2a has a rectangular shape slightly smaller than the outer shape of the multilayer wiring board 1 by using a metal material such as 42 alloy, Kovar, phosphor bronze, or iron. Produced by the law.

また、シールドカバー2の多層配線基板1への取り付けは、まず、接合用導体5aが導出されている切り欠き部4の形成領域内に、クリーム半田をディスペンサ等を用いて塗布・充填し、次に、シールドカバー2を当接脚部2cが多層配線基板上面に当接した状態で多層配線基板上に載置させるとともに、接合脚部2bを切り欠き部4に収容した後、クリーム半田を溶融して硬化させることによって接合脚部2bと接合用導体5aとを半田を介して接合することによって行われ、同時にグランド端子とシールドカバー2とが電気的に接続される。   The shield cover 2 is attached to the multilayer wiring board 1 by first applying and filling cream solder with a dispenser or the like in the formation region of the cutout portion 4 where the bonding conductor 5a is led out. In addition, the shield cover 2 is placed on the multilayer wiring board in a state where the contact leg 2c is in contact with the upper surface of the multilayer wiring board, and the joint leg 2b is accommodated in the notch 4, and the cream solder is melted. Then, the bonding leg 2b and the bonding conductor 5a are bonded to each other through solder, and at the same time, the ground terminal and the shield cover 2 are electrically connected.

かくして上述した電子部品は、その使用時、シールドカバー2がグランド電位に保持されるようになっており、外部からの電磁波をシールドカバー2によって良好に遮蔽し、電子部品を安定して動作させることができるようになる。尚、本実施形態においては図2に示す如く、電子部品素子の側面側がシールドカバー2で覆われていない部分も存在するが、電子部品素子の上面が天板2aで覆われていれば、外部からの電磁波を充分に遮蔽することができる。またこの場合、平板状の天板2aに接合脚部2bと当接脚部2cとを立設するだけで簡単にシールドケース2を製作することができる。   Thus, when the electronic component described above is used, the shield cover 2 is held at the ground potential, and the electromagnetic wave from the outside is well shielded by the shield cover 2 so that the electronic component can be operated stably. Will be able to. In this embodiment, as shown in FIG. 2, there is a portion where the side surface side of the electronic component element is not covered by the shield cover 2, but if the upper surface of the electronic component element is covered by the top plate 2a, The electromagnetic wave from the can be sufficiently shielded. Further, in this case, the shield case 2 can be easily manufactured only by erecting the joint leg 2b and the contact leg 2c on the flat top plate 2a.

次に、上述した電子部品の製造方法について図5を用いて説明する。図5の(a)は、母基板20にシールドカバー2を載置した状態の平面図、(b)は図5(a)のa‐a’線断面図である。尚、図5の(a)では、母基板20の一部にシールドカバー2を載置した状態を示してある。   Next, a method for manufacturing the electronic component described above will be described with reference to FIG. 5A is a plan view of the state in which the shield cover 2 is placed on the mother board 20, and FIG. 5B is a cross-sectional view taken along the line aa ′ in FIG. 5A. 5A shows a state where the shield cover 2 is placed on a part of the mother board 20. FIG.

(工程A)
まず、矩形状を成す複数個の基板領域を一列状に配置させるとともに、隣接する基板領域の境界部に、少なくとも一方の基板領域の外周辺を跨ぐようにして一方の孔部21aを、少なくとも他方の基板領域の外周辺を跨ぐようにして他方の孔部21bを、両孔部が境界部の中央点に対し略点対称で、且つ前記中央点より所定方向にずれた位置に配されるようにして形成した母基板20を準備する。
(Process A)
First, a plurality of rectangular substrate regions are arranged in a line, and at least one other hole 21a is formed at the boundary between adjacent substrate regions so as to straddle the outer periphery of at least one substrate region. The other hole 21b is arranged so as to straddle the outer periphery of the substrate area at a position where both the holes are substantially point-symmetric with respect to the center point of the boundary part and deviated from the center point in a predetermined direction. A mother substrate 20 formed as described above is prepared.

前記母基板20は、例えば、ガラス‐セラミック、アルミナセラミックス等のセラミック材料からなる複数の絶縁シート20a〜20cを間に内部配線導体となる導体パターンを介して積層することによって形成されており、母基板上面の各基板領域には表面配線導体となる導体パターンが被着・形成されている。   The mother board 20 is formed, for example, by laminating a plurality of insulating sheets 20a to 20c made of a ceramic material such as glass-ceramic or alumina ceramic via a conductor pattern serving as an internal wiring conductor. A conductor pattern to be a surface wiring conductor is deposited and formed on each substrate region on the upper surface of the substrate.

このような母基板20を構成する絶縁シート20a〜20cは、例えば、セラミック材料粉末に適当な有機バインダー、有機溶剤等を添加・混合して得たスラリーを従来周知のドクターブレード法等によって、所定厚みにテープ成型して半硬化状態のセラミックグリーンシートとなし、これらを積層してプレス成形した後、高温で焼成することによって製作される。   The insulating sheets 20a to 20c constituting the mother substrate 20 are, for example, a predetermined slurry by a conventionally known doctor blade method or the like obtained by adding and mixing an appropriate organic binder, organic solvent or the like to ceramic material powder. The tape is molded into a thickness to form a semi-cured ceramic green sheet, which is laminated and press-molded, and then fired at a high temperature.

また、内部配線導体や表面配線導体となる導体パターンは、セラミックグリーンシートの表面に導体ペーストを所定パターンに印刷・塗布するとともに、絶縁シートとともに高温で焼成することによって製作される。尚、前記導体ペーストとしては、例えば、Ag、Ag−Pd、Ag−Pt等のAg系粉末、ホウ珪酸系低融点ガラスフリット、エチルセルロース等の有機バインダー、有機溶剤を均質混合したものが用いられる。   In addition, a conductor pattern to be an internal wiring conductor or a surface wiring conductor is manufactured by printing and applying a conductive paste in a predetermined pattern on the surface of a ceramic green sheet and firing it at a high temperature with an insulating sheet. As the conductive paste, for example, an Ag-based powder such as Ag, Ag-Pd, or Ag-Pt, a borosilicate low-melting glass frit, an organic binder such as ethyl cellulose, and an organic solvent are used.

このようにして得られた母基板20の隣接する基板領域の境界部に、一方の基板領域を跨ぐようにして一方の孔部21aを、他方の基板領域を跨ぐようにして他方の孔部21bを、一方の孔部21aと他方の孔部21bとが境界部の中央点に対し略点対称に位置するようにして形成する。ここで境界部とは、隣接する基板領域に挟まれた矩形状の捨代領域22を指し、境界部の中央点とは捨代領域22の対角線が交差する点を指す。また、1つの基板領域を見たときに、基板領域を介して配置されている一対の孔部同士は、前記基板領域を平面視した際の図心に対し略点対称で、且つ孔部21が形成される基板領域外周辺の中点から外周辺に沿って逆方向にずれるようにして位置させてある。   One hole 21a is formed so as to straddle one substrate region and the other hole 21b is formed so as to straddle the other substrate region at the boundary between adjacent substrate regions of the mother substrate 20 thus obtained. Is formed so that one hole 21a and the other hole 21b are positioned substantially symmetrically with respect to the center point of the boundary. Here, the boundary portion refers to a rectangular marginal region 22 sandwiched between adjacent substrate regions, and the center point of the boundary portion refers to a point where diagonal lines of the marginal region 22 intersect. In addition, when one substrate region is viewed, the pair of hole portions arranged through the substrate region are substantially point-symmetric with respect to the centroid when the substrate region is viewed in plan, and the hole portion 21. Is positioned so as to be shifted in the opposite direction along the outer periphery from the midpoint of the outer periphery of the substrate region where the substrate is formed.

尚、一方の孔部21aと他方の孔部21bとの中心間距離xは、孔部21の直径よりも大きくなるように設定される。   The center-to-center distance x between the one hole 21a and the other hole 21b is set to be larger than the diameter of the hole 21.

このようにして孔部21を位置させることにより、捨代領域22の幅dを大幅に縮小させることが可能となる。すなわち、一方の孔部21aと他方の孔部21bとが、境界部の中央点に対し略点対称に位置するように配されているため、捨代領域22の幅dを狭めても両孔部が接触することはない。これによって、母基板20に占める捨代領域22の割合を減らして、その分、母基板20から取得できる電子部品の個数を増加させることができるので、電子部品の生産性を向上させることができるようになる。   By positioning the hole 21 in this manner, the width d of the marginal region 22 can be greatly reduced. That is, since the one hole portion 21a and the other hole portion 21b are arranged so as to be substantially point-symmetric with respect to the center point of the boundary portion, both holes are formed even if the width d of the marginal region 22 is reduced. The parts never touch. As a result, the proportion of the abandoned area 22 occupying the mother board 20 can be reduced, and the number of electronic components that can be acquired from the mother board 20 can be increased correspondingly, so that the productivity of the electronic parts can be improved. It becomes like this.

このような孔部21は、絶縁シート20a〜20cを積層する前に、最上層に配される絶縁シート20aの上述したような所定の位置に、予めパンチングやレーザー等により貫通孔を形成しておき、この絶縁シート20aを、2層目の絶縁シート20bの上面に設けられている接合用導体5aが前記貫通孔から露出するようにして、絶縁シート20b上に載置することによって形成される。   Prior to laminating the insulating sheets 20a to 20c, such a hole 21 is formed by previously forming a through hole by punching, laser or the like at a predetermined position as described above of the insulating sheet 20a disposed in the uppermost layer. The insulating sheet 20a is formed by placing the insulating sheet 20a on the insulating sheet 20b so that the bonding conductor 5a provided on the upper surface of the second insulating sheet 20b is exposed from the through hole. .

(工程B)
次に、前記母基板20の各基板領域に電子部品素子7を搭載する。かかる電子部品素子7の搭載は、まず、母基板上面に設けられた電子部品素子搭載用の表面配線導体に、クリーム半田等の導電性接着剤を従来周知のスクリーン印刷等によって塗布した後、チップコンデンサ、ダイオード、トランジスタ等の各種電子部品素子を、導電性接着剤が塗布された表面配線導体上に載置させ、最後にクリーム半田を溶融して硬化させることにより行われる。
(Process B)
Next, the electronic component element 7 is mounted on each board region of the mother board 20. The mounting of the electronic component element 7 is performed by first applying a conductive adhesive such as cream solder to the surface wiring conductor for mounting the electronic component element provided on the upper surface of the mother board by screen printing or the like. Various electronic component elements such as capacitors, diodes, and transistors are placed on a surface wiring conductor coated with a conductive adhesive, and finally cream solder is melted and cured.

(工程C)
次に、矩形状を成し、対向する辺に一対の接合脚部2bを設けた複数個のシールドカバー2を、対応する基板領域上に載置させるとともに、隣接するシールドカバーのうち、一方のシールドカバー2の接合脚部2bを前記一方の孔部21に、他方のシールドカバー2の接合脚部2bを他方の孔部21にそれぞれ挿入する。
(Process C)
Next, a plurality of shield covers 2 each having a rectangular shape and provided with a pair of joint legs 2b on opposite sides are placed on the corresponding substrate region, and one of the adjacent shield covers The joining leg 2b of the shield cover 2 is inserted into the one hole 21, and the joining leg 2b of the other shield cover 2 is inserted into the other hole 21, respectively.

前記シールドカバー2は、矩形状の天板2aと、天板2aの外周部に立設された接合脚部2b及び当接脚部2cとから成る。接合脚部2bは、天板2aの二組の対向辺のうち一方の対向辺にのみ配されており、一対の接合脚部2b同士が、天板2aを平面視した際の図心の中心に対し略点対称で、且つ対向辺の各中心より所定方向にずらすようにして配置されている。   The shield cover 2 includes a rectangular top plate 2a, and a joining leg portion 2b and a contact leg portion 2c provided upright on the outer periphery of the top plate 2a. The joint leg 2b is disposed only on one of the two opposing sides of the top plate 2a, and the pair of joint legs 2b is the center of the centroid when the top plate 2a is viewed in plan view. Are arranged symmetrically with respect to each other and shifted in a predetermined direction from the centers of the opposite sides.

また、接合脚部2bの配されていない他の対向辺には、多層配線基板1の上面に当接される一対の当接脚部2cが立設されている。この当接脚部2cは、天板2aの図心に対し略点対称に配されており、シールドカバー2を取り付ける際、シールドカバー2が傾くのを有効に防止して、シールドカバー2を安定した状態で多層配線基板に取着させることができる。   In addition, a pair of contact legs 2 c that are in contact with the upper surface of the multilayer wiring board 1 are provided upright on the other opposing side where the joining legs 2 b are not arranged. The contact legs 2c are arranged substantially symmetrically with respect to the centroid of the top plate 2a, and when the shield cover 2 is attached, the shield cover 2 is effectively prevented from being tilted to stabilize the shield cover 2. In this state, it can be attached to the multilayer wiring board.

このようなシールドカバー2は、例えば42アロイやコバール、リン青銅、鉄等の金属材料によって、天板2aが基板領域より若干小さめの矩形状をなすように、従来周知の金属加工法にて製作される。   Such a shield cover 2 is manufactured by a conventionally well-known metal processing method so that the top plate 2a has a slightly smaller rectangular shape than the substrate region by using a metal material such as 42 alloy, Kovar, phosphor bronze, or iron. Is done.

(工程D)
次に、接合脚部2bと孔部21の内面に設けられている接合用導体5aとを半田を介して接合する。
(Process D)
Next, the joining leg 2b and the joining conductor 5a provided on the inner surface of the hole 21 are joined via solder.

シールドカバー2を多層配線基板1へ取り付けるには、まず、接合用導体5aが導出されている孔部21の形成領域内に、クリーム半田23をディスペンサ等を用いて塗布・充填する。次に、シールドカバー2を、当接脚部2cが母基板上面の基板領域に当接した状態で多層配線基板上に載置させるとともに、各接合脚部2bを孔部21に1個ずつ挿入する。最後に、クリーム半田23を溶融して硬化させることによって接合脚部2bが接合用導体5aに半田を介して機械的・電気的に接続されることになる。 In order to attach the shield cover 2 to the multilayer wiring board 1, first, cream solder 23 is applied and filled into the formation region of the hole 21 from which the bonding conductor 5a is led out using a dispenser or the like. Next, the shield cover 2 is placed on the multilayer wiring board in a state where the contact leg 2c is in contact with the board area on the upper surface of the mother board, and each joining leg 2b is inserted into the hole 21 one by one. To do. Finally, so that the joining legs 2b by the curing by melting the cream solder 23 is mechanically and electrically connected via the solder bonding conductor 5a.

(工程E)
最後に、母基板20を各基板領域の外周に沿って一括的に切断することにより複数個の電子部品に分割する。
(Process E)
Finally, the mother board 20 is divided into a plurality of electronic components by collectively cutting along the outer periphery of each board area.

かかる母基板20の切断は、母基板外周部に付けられたマーキングを画像認識装置により読み取ることにより切断位置を認識し、しかる後、ダイサー等を用いて各基板領域の外周に沿ってマトリクス状に切断することにより行われ、これによって図1に示すような電子部品を同時に複数個得ることができる。   The mother substrate 20 is cut by recognizing the cutting position by reading the marking on the outer periphery of the mother substrate with an image recognition device, and then using a dicer or the like in a matrix form along the outer periphery of each substrate region. A plurality of electronic components as shown in FIG. 1 can be obtained at the same time.

尚、本発明は上述の実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良等が可能である。   In addition, this invention is not limited to the above-mentioned embodiment, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

上述した実施形態においては、切り欠き部4の上端が多層配線基板1の上面に開口するとともに、下端が多層配線基板1の2層目に位置する絶縁層1bの上面と対応する高さに位置させるようにして形成したが、切り欠き部4を、その下端が最下層に位置する絶縁層1cの上面と対応する高さに位置させるようにして形成しても良いし、切り欠き部4の下端が多層配線基板1の下面に開口するように、すなわち、多層配線基板1の上面から下面にかけて貫通するように形成しても良い。   In the embodiment described above, the upper end of the notch 4 is opened at the upper surface of the multilayer wiring board 1 and the lower end is positioned at a height corresponding to the upper surface of the insulating layer 1b located at the second layer of the multilayer wiring board 1. However, the notch portion 4 may be formed so that the lower end thereof is positioned at a height corresponding to the upper surface of the insulating layer 1c located at the lowermost layer. You may form so that a lower end may open to the lower surface of the multilayer wiring board 1, ie, it may penetrate from the upper surface of the multilayer wiring board 1 to a lower surface.

また上述した実施形態においては、シールドカバー2を平板状の天板2aと天板2aに直接立設した接合脚部2b及び当接脚部2cとで形成したが、図6に示す如く、天板2aの外周部に側壁10を設けた上、該側壁10の下端に接合脚部2b及び当接脚部2cを立設するようにしても良い。この場合、電子部品素子7の側面側もシールドカバー2で覆われるため、外部からの電磁波をより効果的に遮蔽することができるようになる。   Further, in the embodiment described above, the shield cover 2 is formed by the flat top plate 2a and the joining leg portion 2b and the contact leg portion 2c which are erected directly on the top plate 2a. However, as shown in FIG. The side wall 10 may be provided on the outer periphery of the plate 2a, and the joint leg 2b and the contact leg 2c may be erected on the lower end of the side wall 10. In this case, since the side surface side of the electronic component element 7 is also covered with the shield cover 2, electromagnetic waves from the outside can be shielded more effectively.

更に上述した実施形態においては、切り欠き部4を半円柱状をなすようにして形成したが、切り欠き部4の形状はこれに限らず、例えば、四角柱状等他の形状で形成するようにしても構わない。   Furthermore, in the embodiment described above, the cutout portion 4 is formed so as to have a semi-cylindrical shape, but the shape of the cutout portion 4 is not limited to this, and may be formed in other shapes such as a quadrangular prism shape, for example. It doesn't matter.

また上述した実施形態においては、母基板20の基板領域間に捨代領域を設けるようにしたが、図7に示す如く、間に捨代領域を設けることなく基板領域同士を近接させて配置するようにしても構わない。この場合の境界部とは、基板領域の外周辺を指し、境界部の中央点とは、外周辺の中点を指すものとする。従って、一方の孔部21a及び他方の孔部21bは、隣接する基板領域の両方を跨ぎ、両孔部が基板領域外周辺の中点に対し対称位置に配されるようにして形成される。このような孔部21が形成された母基板20を準備した後(工程)、上述した実施形態と同様の工程〜工程を行うことにより複数個の電子部品が得られる。このように捨代領域を設けない場合であっても、隣接するシールドカバー2のうち一方のシールドカバー2の接合脚部2bを一方の孔部21aに、他方のシールドカバー2の接合脚部2bを他方の孔部21bにそれぞれ挿入することにより、各接合脚部2bに所定量の半田を均一に付着させることができるようになり、シールドカバー2の接続信頼性及び電子部品の生産性を向上させることが可能となる。また、この場合、捨代領域が殆どなくなるため、母基板20により多くの基板領域を確保することができるようになり、これによっても電子部品の生産性を向上させることが可能となる。 Further, in the above-described embodiment, the separation region is provided between the substrate regions of the mother substrate 20, but as shown in FIG. 7, the substrate regions are arranged close to each other without providing any separation region. It doesn't matter if you do. In this case, the boundary portion indicates the outer periphery of the substrate region, and the center point of the boundary portion indicates the middle point of the outer periphery. Accordingly, the one hole portion 21a and the other hole portion 21b are formed so as to straddle both of the adjacent substrate regions, and the both hole portions are arranged symmetrically with respect to the midpoint of the periphery outside the substrate region. After preparing the mother board 20 in which such holes 21 are formed (process A ), a plurality of electronic components can be obtained by performing processes B to E similar to those in the above-described embodiment. Even in the case where the abandoned area is not provided as described above, the joint leg 2b of one shield cover 2 of the adjacent shield covers 2 is used as one hole 21a and the joint leg 2b of the other shield cover 2 is used. By inserting each into the other hole 21b, a predetermined amount of solder can be uniformly attached to each joint leg 2b, improving the connection reliability of the shield cover 2 and the productivity of electronic parts. It becomes possible to make it. Further, in this case, since there is almost no marginal area, it becomes possible to secure a larger board area on the mother board 20, thereby improving the productivity of electronic components.

本発明の一実施形態に係る電子部品の斜視図である。It is a perspective view of the electronic component which concerns on one Embodiment of this invention. (a)は図1の電子部品をA方向から見たときの側面図であり、(b)は図1の電子部品をB方向から見たときの側面図である。(A) is a side view when the electronic component in FIG. 1 is viewed from the A direction, and (b) is a side view when the electronic component in FIG. 1 is viewed from the B direction. 図1の電子部品をC‐C’線で切断したときの断面図である。It is sectional drawing when the electronic component of FIG. 1 is cut | disconnected by the C-C 'line | wire. 図1の電子部品のシールドカバーを多層配線基板への載置面側から見たときの平面図である。It is a top view when the shield cover of the electronic component of FIG. 1 is seen from the mounting surface side on the multilayer wiring board. 本発明の一実施形態に係る電子部品の製造方法を説明するための図であり、(a)は母基板にシールドカバーを載置した状態を示す平面図であり、(b)はa‐a’線の断面図である。It is a figure for demonstrating the manufacturing method of the electronic component which concerns on one Embodiment of this invention, (a) is a top view which shows the state which mounted the shield cover in the mother board, (b) is aa It is sectional drawing of a line. 本発明の他の実施形態に係る電子部品の斜視図である。It is a perspective view of the electronic component which concerns on other embodiment of this invention. 本発明の他の実施形態に係る電子部品の製造方法を説明するための図であり、(a)は母基板にシールドカバーを載置した状態を示す平面図であり、(b)はa‐a’線の断面図である。It is a figure for demonstrating the manufacturing method of the electronic component which concerns on other embodiment of this invention, (a) is a top view which shows the state which mounted the shield cover in the mother board, (b) is a- It is sectional drawing of a 'line. 従来の電子部品の分解斜視図である。It is a disassembled perspective view of the conventional electronic component. 従来の電子部品の製造方法を説明するための図であり、(a)は母基板にシールドカバーを載置した状態を示す平面図であり、(b)はa‐a’線の断面図である。It is a figure for demonstrating the manufacturing method of the conventional electronic component, (a) is a top view which shows the state which mounted the shield cover in the mother board, (b) is sectional drawing of aa 'line. is there. 従来の電子部品の製造方法を説明するための図であり、(a)は母基板にシールドカバーを載置した状態を示す平面図であり、(b)はa‐a’線の断面図である。It is a figure for demonstrating the manufacturing method of the conventional electronic component, (a) is a top view which shows the state which mounted the shield cover in the mother board, (b) is sectional drawing of aa 'line. is there.

符号の説明Explanation of symbols

1・・・・多層配線基板
2・・・・シールドカバー
3・・・・半田
4・・・・切り欠き部
7・・・・電子部品素子
20・・・母基板
21・・・孔部
DESCRIPTION OF SYMBOLS 1 ... multilayer wiring board 2 ... shield cover 3 ... solder 4 ... notch part 7 ... electronic component element 20 ... mother board 21 ... hole

Claims (2)

電子部品を多数個取りするための母基板であって、列状に配置された矩形状をなす複数の基板領域を有し、隣接する基板領域の境界部には、少なくとも一方の基板領域の外周辺を跨ぐようにして形成された円形状の一方の孔部と、少なくとも他方の基板領域の外周辺を跨ぐようにして形成された円形状の他方の孔部とが独立して形成されており、前記一方の孔部と前記他方の孔部とが、前記境界部の中央点に対し略点対称の位置に配されており、前記境界部を挟んで隣接している基板領域の外周辺には、前記一方の孔部および前記他方の孔部の配置箇所の各々と対向する位置に孔部が存在しないことを特徴とする多数個取り用母基板。
A mother board for taking a large number of electronic components, and has a plurality of rectangular board areas arranged in a row, and at the boundary between adjacent board areas, at least one of the board areas. One circular hole formed so as to straddle the periphery and the other circular hole formed so as to straddle the outer periphery of at least the other substrate region are formed independently. The one hole part and the other hole part are arranged at a substantially point-symmetrical position with respect to the center point of the boundary part, and on the outer periphery of the substrate region adjacent to the boundary part. Is a mother board for multi-piece production, wherein no hole is present at a position facing each of the arrangement positions of the one hole and the other hole.
前記一方の孔部と前記他方の孔部との中心間の距離がこれらの孔部の直径よりも大きいことを特徴とする請求項に記載の多数個取り用母基板。 Multi-piece for the mother substrate according to claim 1, the distance between the centers of and the one of the holes the other hole portion, being larger than the diameter of these holes.
JP2007136291A 2007-05-23 2007-05-23 Electronic components, shield covers, mother boards for multi-cavity, wiring boards and electronic equipment Expired - Fee Related JP4558004B2 (en)

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JP2003152287A (en) * 2001-11-15 2003-05-23 Murata Mfg Co Ltd Electronic part and collective electronic part, and method for manufacturing the electronic part
JP2003224336A (en) * 2001-11-26 2003-08-08 Murata Mfg Co Ltd Master substrate for modular substrate and method for forming edge electrode of modular substrate
JP2004022977A (en) * 2002-06-19 2004-01-22 Murata Mfg Co Ltd Aggregated substrate and method of manufacturing electronic component using the same
JP2005294697A (en) * 2004-04-02 2005-10-20 Kyocera Corp Electronic part and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
JPH09153696A (en) * 1995-11-30 1997-06-10 Kyocera Corp Electronic component having shield case and manufacture thereof
JPH1013078A (en) * 1996-06-24 1998-01-16 Sumitomo Metal Ind Ltd Electronic part and its manufacturing method
JP2003152287A (en) * 2001-11-15 2003-05-23 Murata Mfg Co Ltd Electronic part and collective electronic part, and method for manufacturing the electronic part
JP2003224336A (en) * 2001-11-26 2003-08-08 Murata Mfg Co Ltd Master substrate for modular substrate and method for forming edge electrode of modular substrate
JP2004022977A (en) * 2002-06-19 2004-01-22 Murata Mfg Co Ltd Aggregated substrate and method of manufacturing electronic component using the same
JP2005294697A (en) * 2004-04-02 2005-10-20 Kyocera Corp Electronic part and manufacturing method thereof

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