JP4553583B2 - Group III nitride compound semiconductor light emitting device - Google Patents

Group III nitride compound semiconductor light emitting device Download PDF

Info

Publication number
JP4553583B2
JP4553583B2 JP2003435410A JP2003435410A JP4553583B2 JP 4553583 B2 JP4553583 B2 JP 4553583B2 JP 2003435410 A JP2003435410 A JP 2003435410A JP 2003435410 A JP2003435410 A JP 2003435410A JP 4553583 B2 JP4553583 B2 JP 4553583B2
Authority
JP
Japan
Prior art keywords
layer
light emitting
quantum well
buffer layer
crystal growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003435410A
Other languages
Japanese (ja)
Other versions
JP2005197292A (en
Inventor
潤 伊藤
壽朗 佐藤
直樹 和田
士郎 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitride Semiconductors Co Ltd
Toyoda Gosei Co Ltd
Original Assignee
Nitride Semiconductors Co Ltd
Toyoda Gosei Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitride Semiconductors Co Ltd, Toyoda Gosei Co Ltd filed Critical Nitride Semiconductors Co Ltd
Priority to JP2003435410A priority Critical patent/JP4553583B2/en
Publication of JP2005197292A publication Critical patent/JP2005197292A/en
Application granted granted Critical
Publication of JP4553583B2 publication Critical patent/JP4553583B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Description

本発明は、紫外線発光のIII族窒化物系化合物半導体発光素子に関する。   The present invention relates to a group III nitride compound semiconductor light emitting device that emits ultraviolet light.

紫外線発光の半導体発光素子における半導体積層方法としては、例えば下記の特許文献１に記載されているものなどが公知である。特に、この特許文献１の発明は、一定の有用性を示すものであり、この発明の目的は、ＧａＮやＡｌＧａＮに転位が存在しても、発光特性を確保することができる窒化ガリウム系化合物半導体の製造方法を提供することであった。   As a semiconductor lamination method in an ultraviolet light emitting semiconductor light emitting device, for example, a method described in Patent Document 1 below is known. In particular, the invention of Patent Document 1 shows certain utility, and the object of the present invention is to provide a gallium nitride-based compound semiconductor that can ensure light emission characteristics even when dislocations exist in GaN or AlGaN. It was to provide a manufacturing method.

この発明は、強い紫外線発光を得るために量子井戸層をＡｌxＧａ1-xＮ（０≦ｘ＜１）から形成し、量子井戸層の直下に積層する下地層として、例えばＳｉＮなどから成る層を離散的に形成することにより、量子井戸層におけるバンドギャップの空間的ゆらぎ（キャリアの局在準位）を積極的に生成しようとするものであった。バンドギャップの空間的ゆらぎの生成が素子の発光強度に大きく寄与することは、従来より広く知られている。
特許第３２８５３４１号公報 In the present invention, a quantum well layer is formed of Al x Ga 1-x N (0 ≦ x <1) in order to obtain strong ultraviolet light emission, and an underlying layer stacked immediately below the quantum well layer is made of, for example, SiN. By forming the layers discretely, the band gap spatial fluctuation (localized level of carriers) in the quantum well layer was actively generated. It has been widely known that the generation of spatial fluctuation of the band gap greatly contributes to the light emission intensity of the device.
Japanese Patent No. 3285341

しかしながら、例えば上記の特許文献１などの様に紫外線発光の半導体発光素子の量子井戸層にインジウム（Ｉｎ）を用いない場合、上記の下地層の形成だけでは、量子井戸層中にバンドギャップの空間的ゆらぎ（キャリアの局在準位）を適度に生成することは必ずしも容易でなく、このため上記の従来技術の範疇では、必ずしも十分な発光強度が得られない。
また、半導体層のインジウムの混晶比を下げると、応力に対するその半導体層の柔軟性が低下するので、その半導体層には転位やクラックが生じ易くなる。特に、活性層や量子井戸層に転位やクラックが生じた場合には、内部量子効率や或いは素子の寿命にその悪影響が及ぶ。 However, in the case where indium (In) is not used in the quantum well layer of an ultraviolet light emitting semiconductor light emitting device as in, for example, the above-mentioned Patent Document 1, a band gap space is formed in the quantum well layer only by forming the base layer. It is not always easy to appropriately generate the target fluctuation (localized level of carriers), and therefore, sufficient light emission intensity is not always obtained in the above-described prior art category.
Further, when the mixed crystal ratio of indium in the semiconductor layer is lowered, the flexibility of the semiconductor layer with respect to stress is reduced, so that dislocations and cracks are likely to occur in the semiconductor layer. In particular, when dislocations or cracks occur in the active layer or the quantum well layer, the internal quantum efficiency or the lifetime of the device is adversely affected.

本発明は、上記の課題を解決するために成されたものであり、その目的は、紫外線発光のIII族窒化物系化合物半導体発光素子において、内部量子効率を向上させると共に、素子内部の応力を緩和して転位やクラックの発生を防止又は抑制することである。   The present invention has been made in order to solve the above-mentioned problems, and its purpose is to improve the internal quantum efficiency and reduce the stress inside the element in an ultraviolet-emitting Group III nitride compound semiconductor light-emitting device. It is to relax or prevent or suppress the occurrence of dislocations and cracks.

上記の課題を解決するためには、以下の手段が有効である。
即ち、本発明の第１の手段は、III族窒化物系化合物半導体を結晶成長によって複数層積層することにより形成される多重量子井戸構造の活性層を有する半導体発光素子において、結晶成長基板と、低温成長バッファ層と、下地層とを有し、低温成長バッファ層は、結晶成長基板の結晶成長面上に積層された窒化ケイ素から成る第１バッファ層と、第１バッファ層の上に積層されたＧａＮ層とから成り、下地層は、III族窒化物系化合物半導体から成る層と、窒化ケイ素から成る第２バッファ層と、III族窒化物系化合物半導体から成る層とが積層されており、これらの第１バッファ層と第２バッファ層をそれぞれ何れも、離散的に斑状または島状に積層し、活性層を構成する量子井戸層をＡｌzＩｎyＧａ1-z-yＮ（０≦ｚ＜１，０＜ｙ＜１，０＜ｚ＋ｙ≦１）から形成し、この量子井戸層にはそれぞれ何れもその直下に窒化ケイ素から成る堆積層を設け、かつ、少なくとも量子井戸層に生じる転位の平均発生周期よりも短い間隔又は周期で、この堆積層を離散的に斑状または島状に堆積することである。 In order to solve the above problems, the following means are effective.
That is, the first means of the present invention is a semiconductor light emitting device having an active layer having a multiple quantum well structure formed by laminating a plurality of Group III nitride compound semiconductors by crystal growth, and a crystal growth substrate; has a low-temperature growth buffer layer, and an underlying layer, the low-temperature growth buffer layer, a first buffer layer made of is silicon nitride stacked on the crystal growth surface of the crystal growth substrate, the product layer on the first buffer layer The underlayer is composed of a layer made of a group III nitride compound semiconductor, a second buffer layer made of silicon nitride, and a layer made of a group III nitride compound semiconductor. , none of these a first buffer layer and second buffer layer, respectively, discrete manner stacked in patchy or islands, the quantum well layer constituting the active layer Al z in y Ga 1-zy N (0 ≦ z <1, 0 <y <1, 0 < + Y ≦ 1) formed from, both each of the quantum well layer formed deposition layer made of silicon nitride immediately below, and at short intervals or period than the average generation period of dislocation occurring in at least a quantum well layer, This deposition layer is discretely deposited in the form of spots or islands .

また、本発明の第２の手段は、上記の第１の手段において、活性層における量子井戸層の積層数を３層以上１０層以下にすることである。
より望ましくは、活性層における量子井戸層の積層数は３層又は４層が良い。 The second means of the present invention is to make the number of stacked quantum well layers in the active layer from 3 to 10 in the first means.
More preferably, the number of quantum well layers in the active layer is three or four.

以上の本発明の手段により、前記の課題を効果的、或いは合理的に解決することができる。 By means of the present invention on the following, the above problems effectively, or can be reasonably resolved.

以上の本発明の手段によって得られる効果は以下の通りである。
即ち、本発明の第１の手段によれば、量子井戸層におけるバンドギャップの空間的ゆらぎ（キャリアの局在準位）を適度、かつ、確実に得ることができるため、発光素子の出力を大きく向上させることができる。
これは、量子井戸層の直下に形成した堆積層の上では、インジウム（Ｉｎ）やガリウム（Ｇａ）は拡散長（マイグレーション長）がアルミニウム（Ａｌ）よりも大幅に長いので、量子井戸層の結晶成長時に、インジウム（Ｉｎ）やガリウム（Ｇａ）がアルミニウム（Ａｌ）よりも堆積層の谷部又は孔部に入り込み易くなり、その結果、量子井戸層の内部では、組成の空間的均一性が積極的に乱されて、組成の空間的なゆらぎが良好に形成されるためである。 The effects obtained by the above-described means of the present invention are as follows.
That is, according to the first means of the present invention, the spatial fluctuation of the band gap (carrier localized level) in the quantum well layer can be obtained moderately and reliably, so that the output of the light emitting element is increased. Can be improved.
This is because the diffusion length (migration length) of indium (In) and gallium (Ga) is significantly longer than that of aluminum (Al) on the deposited layer formed immediately below the quantum well layer. During growth, indium (In) and gallium (Ga) are more likely to enter the valley or hole of the deposited layer than aluminum (Al), and as a result, the spatial uniformity of the composition is positive in the quantum well layer. This is because the spatial fluctuation of the composition is well formed.

また、上記の第１バッファ層は結晶成長を阻害する作用を奏するので、この第１バッファ層の積層により、このバッファ層の凹凸表面の谷部又は孔部の、まだ結晶成長基板が露出している部分から、次の結晶成長が開始されるが、その結晶成長はやがて横方向に進み、第１バッファ層の上方にまで回り込む。ここで、第１バッファ層は非晶質の状態であるので、第１バッファ層の上方にまで回り込んで形成される半導体結晶は、結晶成長基板及び第１バッファ層の影響を受けにくく、単結晶化し易い。したがって、第１バッファ層の上方にまで回り込んで形成される半導体層は、良質で転位密度の小さなものになる。   In addition, since the first buffer layer acts to inhibit crystal growth, the stacking of the first buffer layer still exposes the crystal growth substrate in the valley or hole of the uneven surface of the buffer layer. The next crystal growth starts from the portion where the crystal growth is present, but the crystal growth eventually proceeds in the lateral direction and reaches the upper portion of the first buffer layer. Here, since the first buffer layer is in an amorphous state, the semiconductor crystal formed so as to extend above the first buffer layer is not easily influenced by the crystal growth substrate and the first buffer layer, and is simply Easy to crystallize. Therefore, the semiconductor layer formed so as to wrap around above the first buffer layer has a high quality and a low dislocation density.

更に、上記の第２バッファ層によっても、半導体結晶の横方向の結晶成長が促される。これらの相乗効果のため、上記の構成に従えば、下地層の転位密度を大幅に低減することができる。この第２バッファ層や上記の第１バッファ層の材料は、結晶成長を阻害する作用を奏するものであれば任意で良く、結晶状態は不問である。即ち、非晶質の材料でも結晶状態の材料でも良い。アルミニウム混晶比や或いはガリウム混晶比が高い量子井戸層を形成する場合にも、それらの量子井戸層にはクラックが生じ難くなる。
即ち、本発明によれば、下地層やそれ以降に積層される半導体層の転位が効果的に低減されるため、紫外線発光の固い量子井戸層を積層しても、高い発光強度の紫外線発光を得ることができる。
また、量子井戸層の組成成分にインジウム（Ｉｎ）を含めることにより、量子井戸層の応力に対する柔軟性が向上するので、これらの相乗効果によっても、量子井戸層に転位やクラックが生じ難くなる。 Further, the second buffer layer also promotes the lateral crystal growth of the semiconductor crystal. Because of these synergistic effects, according to the above configuration, the dislocation density of the underlayer can be greatly reduced. Any material may be used for the second buffer layer and the first buffer layer as long as they have an effect of inhibiting crystal growth, and the crystal state is not limited. That is, an amorphous material or a crystalline material may be used. Even when quantum well layers having a high aluminum mixed crystal ratio or a gallium mixed crystal ratio are formed, cracks are unlikely to occur in these quantum well layers.
That is, according to the present invention, dislocations in the underlying layer and the semiconductor layer stacked thereafter are effectively reduced. Therefore, even when a hard quantum well layer that emits ultraviolet light is laminated, ultraviolet light emission with high emission intensity can be obtained. Obtainable.
In addition, by including indium (In) in the composition component of the quantum well layer, the flexibility of the quantum well layer with respect to stress is improved, so that dislocations and cracks are less likely to occur in the quantum well layer due to these synergistic effects.

なお、上記のインジウム組成比ｙは、０．０１以上であることがより望ましい。また、上記のインジウム組成比ｙは、０．０３以上であることが更に望ましいが、この値としては、発光波長などの素子の各種の仕様、特性などに応じて好適或いは最適な値を選択することができる。この値が小さすぎると、揺らぎを十分に確保することが難しくなり、また、この値を大きくし過ぎると、紫外線発光の半導体発光素子を製造することができなくなる。 Incidentally, the indium composition ratio y of the above, is more preferable and this is 0.01 or more. In addition, the indium composition ratio y is more preferably 0.03 or more. However, as this value, a suitable or optimal value is selected according to various specifications and characteristics of the element such as the emission wavelength. be able to. If this value is too small, it will be difficult to ensure sufficient fluctuations, and if this value is too large, a semiconductor light emitting device that emits ultraviolet light cannot be produced.

また、局在準位の極近傍に転位が存在すると、そこでは発光が起こり難いので、このゆらぎの密度（周期）は、少なくとも量子井戸層に生じる転位密度よりも高くする必要がある。この周期は、堆積層を離散的に堆積する際の、その離散的度合い（密度）を表しており、望ましくは、１ｎｍ〜１００ｎｍ程度が望ましいと考えられるが、少なくとも、転位密度の平均周期よりも短ければ、上記の作用・効果を得ることができる。なお、量子井戸層の組成の空間的なゆらぎの密度（周期）は、理論的には数ｎｍ程度が最も理想的であると考えられる。 Further, when dislocations are present in the very vicinity of the localized level, light emission is unlikely to occur there. Therefore, the density (period) of this fluctuation needs to be higher than at least the dislocation density generated in the quantum well layer. This period, when discretely deposited deposition layer, represents the discrete degree (density), preferably is believed 1nm~100nm extent is desired, at least, than the average period of the dislocation density If it is too short, the above-mentioned actions and effects can be obtained. The density (period) of the spatial fluctuation of the composition of the quantum well layer is theoretically considered to be about several nm.

また、上記の本発明の紫外線発光の半導体発光素子の発光強度に関するその他の最適化パラメータとしては、ｎ型クラッド層のキャリア濃度や、活性層の量子井戸層の積層数（本発明の第２の手段）や、活性層の量子障壁層の膜厚などがあり、これらのパラメータをそれぞれ、上記の様に好適化或いは最適化することにより、従来よりも高い発光強度の紫外線発光の半導体発光素子を得ることができる。 As the other optimization parameters related to the emission intensity of the semiconductor light-emitting device of the ultraviolet light emission of the invention described above, n-type cladding layer carrier concentration and number of stacked quantum well layer of the active layer (of the present invention the second means) and has etc. Do thickness of the active layer quantum barrier layer, these parameters respectively, by suitable reduction or optimized as described above, the semiconductor light-emitting of ultraviolet light of high luminous intensity than conventional An element can be obtained.

また、半導体発光素子の内部応力を緩和する手段としては、ｎ型／ｐ型クラッド層を超格子構造にするなどの構成も有効である。
また、第２バッファ層は、５００℃程度の低温で形成しても、１０００℃以上の高温で形成しても良い。第２バッファ層の結晶成長温度を１０５０℃以上１１００℃以下とし、第２バッファ層の結晶性長時間を６秒以上１８秒以下とすると、下地層の転位密度を効果的に低減できると共に、第２バッファ層の積層時間を効果的に削減することができる。 As a means to alleviate the internal stress of the semiconductor light emitting element, Ru configuration also effective der, such as the n-type / p-type cladding layer in super lattice structure.
The second buffer layer may be formed at a low temperature of about 500 ° C. or at a high temperature of 1000 ° C. or higher. When the crystal growth temperature of the second buffer layer is 1050 ° C. or more and 1100 ° C. or less and the crystallinity long time of the second buffer layer is 6 seconds or more and 18 seconds or less, the dislocation density of the underlayer can be effectively reduced, The stacking time of the two buffer layers can be effectively reduced.

尚、上記の本発明の紫外線発光の半導体発光素子の発光強度に関するその他の最適化パラメータとしては、ｐ型クラッド層をも超格子構造とした場合のアルミニウム（Ａｌ）組成比や、ｐ型クラッド層の結晶成長温度などがあり、これらのパラメータをそれぞれ、上記の様に好適化或いは最適化することにより、従来よりも高い発光強度の紫外線発光の半導体発光素子を得ることができる。 Other optimization parameters related to the emission intensity of the above-described ultraviolet light emitting semiconductor light emitting device of the present invention include an aluminum (Al) composition ratio when the p-type cladding layer also has a superlattice structure, and a p-type cladding layer. There is a crystal growth temperature, etc., these parameters respectively, by suitable reduction or optimized as described above, it is possible to obtain a semiconductor light-emitting element of ultraviolet emission with high luminous intensity than before.

また、堆積層、第１バッファ層、第２バッファ層等は何れも、ＳｉＮの他にも、ＳｉＮ2，多結晶シリコン、多結晶窒化物半導体等の多結晶半導体、酸化珪素(SiOx)、窒化珪素(SiNx)、酸化チタン(TiOX)、酸化ジルコニウム(ZrOX)等の酸化物や、また、所謂ＥＬＯマスクなどとして一般にも利用されている周知の適当な窒化物などからも形成することでき、或いはチタン(Ti)、タングステン(W)のような高融点金属や、更には、これらの多層膜などをも用いることが可能である。また、これらの成膜方法は、蒸着、スパッタ、ＶＰＥ等の気相成長法の他、任意である。 The deposited layer, the first buffer layer, the second buffer layer, etc. are all SiN 2 , polycrystalline semiconductors such as polycrystalline silicon and polycrystalline nitride semiconductor, silicon oxide (SiO x ), It is also formed from an oxide such as silicon nitride (SiN x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), or a well-known appropriate nitride that is generally used as a so-called ELO mask. Alternatively, a refractory metal such as titanium (Ti) or tungsten (W), or a multilayer film of these can also be used. In addition to these vapor deposition methods such as vapor deposition, sputtering, and VPE, these film forming methods are arbitrary.

以下、本発明を具体的な実施例に基づいて説明する。
ただし、本発明の実施形態は、以下に示す個々の実施例に限定されるものではない。 Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

図１に本実施例１の短波長発光ＬＥＤ１００の断面図を示す。この短波長発光ＬＥＤ１００は、ＭＯＶＰＥ法を用いて製造したものである。
サファイア基板１０の上には、窒化シリコンを５００℃で１００秒間積層した第１バッファ層２１と、同温で結晶成長させた膜厚２５ｎｍのＧａＮ層２２との２層から成る低温成長バッファ層２０が形成されている。その上の下地層３０は３層から成り、無添加のＧａＮを１０７５℃で約０．７μｍ結晶成長させたＧａＮ層３１と、窒化シリコン（ＳｉＮ）を１０７５℃で１２秒間結晶成長させた第２バッファ層３２と、無添加のＧａＮを１０７５℃で約３μｍ結晶成長させたＧａＮ層３３とから成る。
ただし、ＳｉＮから成る第２バッファ層３２を斑状或いは島状に離散的に形成する際には、シラン（ＳｉＨ4）の１０ｐｐｍ希釈ガスを１０ｓｃｃｍの割合で、アンモニア（ＮＨ3）ガスを１０ｓｌｍの割合でそれぞれ供給し、かつ、この第２バッファ層３２の積層時間は１２秒とした。 FIG. 1 shows a cross-sectional view of the short wavelength light emitting LED 100 of the first embodiment. This short wavelength light emitting LED 100 is manufactured using the MOVPE method.
On the sapphire substrate 10, a low-temperature growth buffer layer 20 comprising two layers of a first buffer layer 21 in which silicon nitride is laminated at 500 ° C. for 100 seconds and a GaN layer 22 having a film thickness of 25 nm grown at the same temperature. Is formed. The underlying layer 30 is formed of three layers, a GaN layer 31 obtained by crystal-growing about 0.75 μm of undoped GaN at 1075 ° C., and a second layer obtained by crystal-growing silicon nitride (SiN) at 1075 ° C. for 12 seconds. The buffer layer 32 and a GaN layer 33 in which undoped GaN is crystal-grown at 1075 ° C. by about 3 μm.
However, when the second buffer layer 32 made of SiN is discretely formed in spots or islands, a 10 ppm diluted gas of silane (SiH 4 ) is used at a rate of 10 sccm, and an ammonia (NH 3 ) gas is used at a rate of 10 slm. And the stacking time of the second buffer layer 32 was 12 seconds.

ｎ型コンタクト層４０とｎ型中間層５１とｎ型クラッド層５２とを順次積層して形成されたｎ型層においては、何れの半導体層も不純物としてシリコン（Ｓｉ）を添加して、成長温度１０７５℃で結晶成長した。このｎ型層の下から一層目のｎ型コンタクト層４０は、膜厚１．１μｍのＧａＮから成り、そのキャリア濃度は５×１０18ｃｍ-3である。次層の膜厚約１００ｎｍのｎ型中間層５１は、Ａｌ0.12Ｇａ0.88Ｎから成り、そのキャリア濃度は５×１０18ｃｍ-3である。
また、ｎ型クラッド層５２は、膜厚約１．５ｎｍのＡｌ0.15Ｇａ0.85Ｎと膜厚約１．５ｎｍのＡｌ0.04Ｇａ0.96Ｎとを交互に合計３８ペア（３８周期）積層した超格子構造を有し、このｎ型クラッド層５２の総膜厚は約１００ｎｍ、キャリア濃度は１×１０19ｃｍ-3である。 In the n-type layer formed by sequentially laminating the n-type contact layer 40, the n-type intermediate layer 51, and the n-type cladding layer 52, silicon (Si) is added as an impurity to any semiconductor layer, and the growth temperature is increased. Crystal growth occurred at 1075 ° C. The n-type contact layer 40 in the first layer from the bottom of the n-type layer is made of GaN having a thickness of 1.1 μm, and its carrier concentration is 5 × 10 18 cm −3 . The n-type intermediate layer 51 having a thickness of the next layer of about 100 nm is made of Al 0.12 Ga 0.88 N and has a carrier concentration of 5 × 10 18 cm −3 .
The n-type cladding layer 52 has a superlattice structure in which Al 0.15 Ga 0.85 N having a thickness of about 1.5 nm and Al 0.04 Ga 0.96 N having a thickness of about 1.5 nm are alternately stacked in total 38 pairs (38 periods). The n-type cladding layer 52 has a total film thickness of about 100 nm and a carrier concentration of 1 × 10 19 cm −3 .

無添加の各半導体層から成る活性層６０は、量子井戸層６ｂを３層有する多重量子井戸構造の活性層であり、中間層６１と多重層６２，６３，６４を何れも結晶成長温度８２５℃で順次積層して形成したものである。中間層６１は膜厚３５ｎｍのＡｌ0.12Ｇａ0.88Ｎから形成されている。
また、多重層（６２，６３，６４）はそれぞれ何れも、堆積層６ａと量子井戸層６ｂと量子障壁層６ｃとを順次積層して形成されている。更に、堆積層６ａはそれぞれ何れも、ＳｉＮから成る層で、堆積時間は１２秒とした。ただし、ＳｉＮから成る堆積層６ａを斑状或いは島状に離散的に形成する際に、シラン（ＳｉＨ4）の１０ｐｐｍ希釈ガスを１５ｓｃｃｍの割合で、アンモニア（ＮＨ3）ガスを１２ｓｌｍの割合で、それぞれ供給した。
また、量子井戸層６ｂはそれぞれ何れも、膜厚約２ｎｍのＡｌ0.005Ｉｎ0.045Ｇａ0.95Ｎから形成されている。量子障壁層６ｃはそれぞれ何れも、膜厚１７．５ｎｍのＡｌ0.12Ｇａ0.88Ｎから形成されている。 The active layer 60 made of each additive-free semiconductor layer is an active layer having a multiple quantum well structure having three quantum well layers 6b, and the intermediate layer 61 and the multiple layers 62, 63, 64 are both crystal growth temperatures of 825 ° C. Are sequentially stacked. The intermediate layer 61 is made of Al 0.12 Ga 0.88 N having a thickness of 35 nm.
Each of the multi-layers (62, 63, 64) is formed by sequentially laminating a deposition layer 6a, a quantum well layer 6b, and a quantum barrier layer 6c. Further, each of the deposited layers 6a is a layer made of SiN, and the deposition time was 12 seconds. However, when the deposited layer 6a made of SiN is discretely formed in spots or islands, a 10 ppm diluted gas of silane (SiH 4 ) is added at a rate of 15 sccm, and ammonia (NH 3 ) gas is added at a rate of 12 slm, respectively. Supplied.
Each of the quantum well layers 6b is formed of Al 0.005 In 0.045 Ga 0.95 N having a thickness of about 2 nm. Each of the quantum barrier layers 6c is made of Al 0.12 Ga 0.88 N having a thickness of 17.5 nm.

活性層６０の上には、ｐ型ブロック層７１とｐ型クラッド層７２とｐ型コンタクト層８０とを順次積層して形成されたｐ型層があり、このｐ型層においては、何れの半導体層も、成長温度を１０２５℃とし、不純物としてマグネシウム（Ｍｇ）を添加して結晶成長したものである。このｐ型層の下から一層目のｐ型ブロック層７１は、膜厚４０ｎｍのＡｌ0.16Ｇａ0.84Ｎから成る。このｐ型ブロック層７１のキャリア濃度は５×１０17ｃｍ-3に設定されている。 On the active layer 60, there is a p-type layer formed by sequentially laminating a p-type block layer 71, a p-type cladding layer 72, and a p-type contact layer 80. The layer was also grown by setting the growth temperature to 1025 ° C. and adding magnesium (Mg) as an impurity. The first p-type block layer 71 from the bottom of the p-type layer is made of Al 0.16 Ga 0.84 N having a thickness of 40 nm. The carrier concentration of this p-type block layer 71 is set to 5 × 10 17 cm −3 .

また、ｐ型クラッド層７２は、膜厚約１．５ｎｍのＡｌ0.12Ｇａ0.88Ｎと膜厚約１．５ｎｍのＡｌ0.03Ｇａ0.97Ｎとを交互に合計３０ペア（３０周期）積層した超格子構造を有し、このｐ型クラッド層７２の総膜厚は約９０ｎｍ、キャリア濃度は５×１０17ｃｍ-3である。また、膜厚約３０ｎｍのＧａＮから成るｐ型コンタクト層８０のキャリア濃度は１×１０18ｃｍ-3である。 The p-type cladding layer 72 has a superlattice structure in which Al 0.12 Ga 0.88 N having a thickness of about 1.5 nm and Al 0.03 Ga 0.97 N having a thickness of about 1.5 nm are alternately stacked in total 30 pairs (30 periods). The p-type cladding layer 72 has a total film thickness of about 90 nm and a carrier concentration of 5 × 10 17 cm −3 . The carrier concentration of the p-type contact layer 80 made of GaN having a thickness of about 30 nm is 1 × 10 18 cm −3 .

以上の積層構成を有する短波長発光ＬＥＤ１００の発光ピーク波長は、３５１ｎｍであった。
更に、ＳｉＮから形成され、活性層６０の中に堆積される堆積層６ａの堆積時間を比較パラメータとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、短波長発光ＬＥＤ１００と同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図２は、それらの短波長発光ＬＥＤの発光強度（ＥＬ）と堆積層６ａの積層時間との関係を例示するグラフである。グラフの縦軸は、ＬＥＤの正負両電極（９１，９２）間に電圧を印加した時の発光強度（ＥＬ）を相対尺度であり、横軸は上記の比較パラメータ（堆積層６ａの堆積時間）である。ただし、ＳｉＮから成る堆積層６ａを斑状或いは島状に離散的に形成する際に、シラン（ＳｉＨ4）の１０ｐｐｍ希釈ガスを１５ｓｃｃｍの割合で、アンモニア（ＮＨ3）ガスを１２ｓｌｍの割合で、それぞれ供給した。 The light emission peak wavelength of the short wavelength light emitting LED 100 having the above laminated structure was 351 nm.
Further, with the deposition time of the deposition layer 6a formed from SiN and deposited in the active layer 60 as a comparison parameter, all other configurations are the same as those of the short wavelength light emitting LED 100 of FIG. The short wavelength light emitting LED was separately manufactured and the emission intensity was compared. FIG. 2 is a graph illustrating the relationship between the emission intensity (EL) of these short wavelength light emitting LEDs and the stacking time of the deposited layer 6a. The vertical axis of the graph is a relative scale of light emission intensity (EL) when a voltage is applied between the positive and negative electrodes (91, 92) of the LED, and the horizontal axis is the comparison parameter (deposition time of the deposited layer 6a). It is. However, when the deposited layer 6a made of SiN is discretely formed in spots or islands, a 10 ppm diluted gas of silane (SiH 4 ) is added at a rate of 15 sccm, and ammonia (NH 3 ) gas is added at a rate of 12 slm, respectively. Supplied.

堆積層６ａは、量子井戸層６ｂにおけるバンドギャップの空間的ゆらぎを形成するために堆積させるものであるので、この堆積層６ａを堆積させる面における堆積層６ａの面積占有率は、小さ過ぎても大きすぎても、そのゆらぎ生成効果は得難くなる。図２のグラフからも判る様に、その堆積時間は、望ましくは、６秒以上１４秒以下である。また、更に望ましくは、９秒から１３秒の間が理想的である。この様な条件設定によれば、堆積層６ａの形成状態（離散状態）を最適にすることができるので、高い発光強度を得ることができる。   The deposited layer 6a is deposited to form a bandgap spatial fluctuation in the quantum well layer 6b. Therefore, even if the area occupation ratio of the deposited layer 6a on the surface on which the deposited layer 6a is deposited is too small. If it is too large, it is difficult to obtain the fluctuation generating effect. As can be seen from the graph of FIG. 2, the deposition time is desirably 6 seconds or more and 14 seconds or less. More desirably, the time is between 9 seconds and 13 seconds. According to such a condition setting, since the formation state (discrete state) of the deposited layer 6a can be optimized, a high emission intensity can be obtained.

なお、堆積層６ａ、第１バッファ層２１、第２バッファ層３２は何れも、ＳｉＮの他にも、ＳｉＮ2，多結晶シリコン、多結晶窒化物半導体等の多結晶半導体、酸化珪素(SiOx)、窒化珪素(SiNx)、酸化チタン(TiOX)、酸化ジルコニウム(ZrOX)等の酸化物や、また、所謂ＥＬＯマスクなどとして一般にも利用されている周知の適当な窒化物などからも形成することができ、或いはチタン(Ti)、タングステン(W)のような高融点金属や、更には、これらの多層膜などをも用いることが可能である。また、これらの成膜方法は、蒸着、スパッタ、ＶＰＥ等の気相成長法の他、任意である。 The deposited layer 6a, the first buffer layer 21, and the second buffer layer 32 are all SiN 2 , polycrystalline semiconductors such as polycrystalline silicon and polycrystalline nitride semiconductor, silicon oxide (SiO x ), Silicon nitride (SiN x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ) and other oxides, and well-known appropriate nitrides commonly used as so-called ELO masks, etc. formed that can be, or titanium (Ti), a refractory metal or such as tungsten (W), further, it can also be used such as those of the multilayer film. In addition to these vapor deposition methods such as vapor deposition, sputtering, and VPE, these film forming methods are arbitrary.

また、ＳｉＮから成る第２バッファ層３２の有無を比較パラメータとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図３は、それらの短波長発光ＬＥＤの発光強度（ＥＬ）とＳｉＮから成る第２バッファ層３２の有無との関係を例示するグラフである。グラフの縦軸は、ＬＥＤの正負両電極（９１，９２）間に電圧を印加した時の発光強度（ＥＬ）を相対尺度であり、横軸は上記の比較パラメータ（ＳｉＮから成る第２バッファ層３２の有無）である。
このグラフより、ＳｉＮから成る第２バッファ層３２を設けた方が高い発光強度が得られることが判る。 Further, using the presence or absence of the second buffer layer 32 made of SiN as a comparison parameter, all other configurations are the same as those of the short wavelength light emitting LED 100 of FIG. . FIG. 3 is a graph illustrating the relationship between the emission intensity (EL) of these short wavelength light emitting LEDs and the presence or absence of the second buffer layer 32 made of SiN. The vertical axis of the graph is a relative scale of light emission intensity (EL) when a voltage is applied between the positive and negative electrodes (91, 92) of the LED, and the horizontal axis is the above-mentioned comparison parameter (second buffer layer made of SiN). 32).
From this graph, it can be seen that higher emission intensity can be obtained by providing the second buffer layer 32 made of SiN.

また、ＳｉＮから成る第２バッファ層の積層条件（：積層温度と積層時間）を比較パラメータとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、短波長発光ＬＥＤ１００と同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図４は、それらの短波長発光ＬＥＤの発光強度（ＥＬ）とＳｉＮから成る第２バッファ層の積層条件（：積層温度と積層時間）との関係を例示するグラフである。グラフの縦軸は、ＬＥＤの正負両電極（９１，９２）間に電圧を印加した時の発光強度（ＥＬ）を相対尺度であり、横軸は上記の比較パラメータ（積層温度と積層時間）であり、記号ＬＴは５００℃の低温を示しており、記号ＨＴは１０７５℃の高温を示している。その下の括弧内の数値は、積層時間（秒）である。   Further, with the stacking conditions (: stacking temperature and stacking time) of the second buffer layer made of SiN as the comparison parameters, all other configurations are the same as those of the short wavelength light emitting LED 100 of FIG. Wavelength light emitting LEDs were separately manufactured, and the light emission intensities were compared. FIG. 4 is a graph illustrating the relationship between the emission intensity (EL) of these short wavelength light emitting LEDs and the stacking conditions (: stacking temperature and stacking time) of the second buffer layer made of SiN. The vertical axis of the graph is a relative scale of light emission intensity (EL) when a voltage is applied between the positive and negative electrodes (91, 92) of the LED, and the horizontal axis is the above comparison parameters (lamination temperature and lamination time). Yes, the symbol LT indicates a low temperature of 500 ° C., and the symbol HT indicates a high temperature of 1075 ° C. The numerical value in the parenthesis below is the stacking time (second).

このグラフからも判る様に、第２バッファ層の積層温度は、１０７５℃程度（１０５０℃〜１１００℃程度）が望ましく、その時の積層時間は１２秒程度（６秒〜１８秒程度）が良い。また、上記の短波長発光ＬＥＤ１００の様に第２バッファ層の積層温度を１０７５℃程度にすれば、下地層（ＧａＮ層３１，３３）と略同温で積層できるので、積層条件を一定にしたまま第２バッファ層を積層できる。したがって、製造時間を短くすることができ、非常に都合がよい。
なお、同時に、５００℃程度の低温でも、積層時間の設定によっては、上記の高温条件より高い発光強度が得られる場合もあることも、図４のグラフから判る。 As can be seen from this graph, the lamination temperature of the second buffer layer is desirably about 1075 ° C. (about 1050 ° C. to 1100 ° C.), and the lamination time at that time is preferably about 12 seconds (about 6 seconds to 18 seconds). Further, if the stacking temperature of the second buffer layer is set to about 1075 ° C. as in the short wavelength light emitting LED 100 described above, the stacking conditions can be made constant because the stacking can be performed at substantially the same temperature as the base layer (GaN layers 31 and 33). The second buffer layer can be stacked as it is. Therefore, the manufacturing time can be shortened, which is very convenient.
At the same time, it can be seen from the graph of FIG. 4 that even at a low temperature of about 500 ° C., the emission intensity higher than the above high temperature condition may be obtained depending on the setting of the lamination time.

また、ｎ型クラッド層５２のキャリア濃度を比較パラメータとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、短波長発光ＬＥＤ１００と同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図５は、それらの短波長発光ＬＥＤの発光強度（ＥＬ）と、ｎ型クラッド層５２のキャリア濃度との関係を例示するグラフである。図５のグラフからも判る様に、ｎ型クラッド層５２のキャリア濃度は、５．０×１０18ｃｍ-3以上１．２×１０19ｃｍ-3以下にすると良い。より望ましくは、ｎ型クラッド層５２のキャリア濃度は８．０×１０18ｃｍ-3以上１．０×１０19ｃｍ-3以下が良い。 Further, with the carrier concentration of the n-type cladding layer 52 as a comparison parameter, all other configurations are the same as those of the short wavelength light emitting LED 100 in FIG. Compared. FIG. 5 is a graph illustrating the relationship between the light emission intensity (EL) of these short wavelength light emitting LEDs and the carrier concentration of the n-type cladding layer 52. As can be seen from the graph of FIG. 5, the carrier concentration of the n-type cladding layer 52 is preferably 5.0 × 10 18 cm −3 or more and 1.2 × 10 19 cm −3 or less. More preferably, the carrier concentration of the n-type cladding layer 52 is 8.0 × 10 18 cm −3 or more and 1.0 × 10 19 cm −3 or less.

また、活性層６０の量子井戸層６ｂの積層数を比較パラメータとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、短波長発光ＬＥＤ１００と同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図６は、それらの短波長発光ＬＥＤの発光強度（ＥＬ）と活性層６０の量子井戸層６ｂの積層数との関係を例示するグラフである。   Further, by using the number of stacked quantum well layers 6b of the active layer 60 as a comparison parameter, all other configurations are the same as those of the short wavelength light emitting LED 100 of FIG. 1, and a short wavelength light emitting LED similar to the short wavelength light emitting LED 100 is separately manufactured. The emission intensity was compared. FIG. 6 is a graph illustrating the relationship between the emission intensity (EL) of these short-wavelength LEDs and the number of stacked quantum well layers 6b of the active layer 60.

本図６より、多重量子井戸構造（ＭＱＷ構造）を採用すると、ＳＱＷ構造の場合よりも発光強度が高くなり、特に、量子井戸層の積層数を２層以上１０層以下にした場合に、高い発光強度が得られることが判る。より望ましくは、ＭＱＷ活性層における量子井戸層の積層数は３層又は４層が良い。   As shown in FIG. 6, when the multiple quantum well structure (MQW structure) is adopted, the emission intensity is higher than that in the case of the SQW structure, and is particularly high when the number of stacked quantum well layers is 2 or more and 10 or less. It can be seen that the emission intensity can be obtained. More preferably, the number of quantum well layers in the MQW active layer is three or four.

また、活性層６０の量子障壁層６ｃの成長時間（∝膜厚）を比較パラメータとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、短波長発光ＬＥＤ１００と同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図７は、それらの短波長発光ＬＥＤの発光強度（ＰＬ：フォト・ルミネッセンス）と活性層６０の量子障壁層６ｃの成長時間との関係を例示するグラフである。   Further, with the growth time (thickness) of the quantum barrier layer 6c of the active layer 60 as a comparison parameter, all other configurations are the same as those of the short wavelength light emitting LED 100 of FIG. LEDs were manufactured separately and the light emission intensities were compared. FIG. 7 is a graph illustrating the relationship between the light emission intensity (PL: photoluminescence) of these short wavelength light emitting LEDs and the growth time of the quantum barrier layer 6 c of the active layer 60.

ここでは、１４０秒の結晶成長時間が、Ａｌ0.12Ｇａ0.88Ｎから成る量子障壁層６ｃを膜厚１７．５ｎｍ成長させる時間に相当している。一方、量子障壁層６ｃを２４ｎｍ以上にすると、ＬＥＤの駆動電圧が高くなる。これらの結果から、ＭＱＷ活性層における量子障壁層６ｃの膜厚は、１２ｎｍ以上２４ｎｍ以下にすると良い。より望ましくは、ＭＱＷ活性層における量子障壁層の膜厚は１５ｎｍ以上２０ｎｍ以下が良い。 Here, the crystal growth time of 140 seconds corresponds to the time for growing the quantum barrier layer 6c made of Al 0.12 Ga 0.88 N to a thickness of 17.5 nm. On the other hand, when the quantum barrier layer 6c is 24 nm or more, the driving voltage of the LED increases. From these results, the film thickness of the quantum barrier layer 6c in the MQW active layer is preferably 12 nm or more and 24 nm or less. More desirably, the film thickness of the quantum barrier layer in the MQW active layer is 15 nm or more and 20 nm or less.

また、ｐ型クラッド層７２中の井戸層の結晶成長工程におけるＡｌ（ＣＨ3）3供給量（∝Ａｌ混晶比）を比較パラメータとし、ｐクラッド層中のＡｌ0.12Ｇａ0.88Ｎから成る量子障壁層の厚さを約１．５ｎｍとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、短波長発光ＬＥＤ１００と同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図８は、それらの短波長発光ＬＥＤの発光強度（ＥＬ）と、ｐ型クラッド層７２中の井戸層の結晶成長工程におけるＡｌ（ＣＨ3）3供給量との関係を例示するグラフである。 Further, a quantum barrier composed of Al 0.12 Ga 0.88 N in the p-cladding layer, using the Al (CH 3 ) 3 supply amount (∝Al mixed crystal ratio) in the crystal growth process of the well layer in the p-type cladding layer 72 as a comparison parameter. The thickness of the layer was set to about 1.5 nm, and all other configurations were the same as those of the short wavelength light emitting LED 100 of FIG. 1, and a short wavelength light emitting LED similar to the short wavelength light emitting LED 100 was separately manufactured, and the light emission intensity was compared. FIG. 8 is a graph illustrating the relationship between the emission intensity (EL) of these short-wavelength LEDs and the supply amount of Al (CH 3 ) 3 in the crystal growth step of the well layer in the p-type cladding layer 72.

ここでは、図１のｐ型クラッド層７２の井戸層に相当する膜厚約１．４ｎｍのＡｌ0.03Ｇａ0.97ＮのＡｌ混晶比０．０３を実現する条件が、図８のグラフでＡｌ（ＣＨ3）3の供給量を５ｓｃｃｍにした場合に相当する。ｐ型クラッド層７２中の各半導体層のアルミニウム（Ａｌ）組成比を何れも０．０１以上とし、かつ、ｐ型クラッド層のアルミニウム（Ａｌ）組成比の平均値を０．０７以上０．０８以下にすることで、キャリアの閉じ込め効果と、超格子構造による応力緩和効果の双方を同時に適度に得ることができ、ＬＥＤの発光強度が向上する。
ｐ型クラッド層７２の井戸層のＡｌ混晶比を上げ過ぎると、超格子構造が明確或いは急峻には維持しにくくなり、応力の緩和効果が下がるものと思われる。また、ｐ型クラッド層７２の井戸層のＡｌ混晶比を下げ過ぎると、キャリアの閉じ込め効果が低下する。 Here, the condition for realizing the Al mixed crystal ratio 0.03 of Al 0.03 Ga 0.97 N having a film thickness of about 1.4 nm corresponding to the well layer of the p-type cladding layer 72 of FIG. This corresponds to the case where the supply amount of CH 3 ) 3 is set to 5 sccm. The aluminum (Al) composition ratio of each semiconductor layer in the p-type cladding layer 72 is 0.01 or more, and the average value of the aluminum (Al) composition ratio of the p-type cladding layer is 0.07 or more and 0.08. By making it below, both the carrier confinement effect and the stress relaxation effect by the superlattice structure can be obtained at the same time, and the emission intensity of the LED is improved.
If the Al mixed crystal ratio of the well layer of the p-type cladding layer 72 is increased too much, it is difficult to maintain the superlattice structure clearly or steeply, and the stress relaxation effect is considered to decrease. Moreover, if the Al mixed crystal ratio of the well layer of the p-type cladding layer 72 is excessively lowered, the carrier confinement effect is lowered.

また、ｐ型クラッド層７２の結晶成長温度を比較パラメータとして、その他の構成は全て図１の短波長発光ＬＥＤ１００と同じにして、短波長発光ＬＥＤ１００と同様の短波長発光ＬＥＤを別途製造し、発光強度を比較した。図９はそれらの短波長発光ＬＥＤの発光強度（ＥＬ）とｐ型クラッド層７２の結晶成長温度との関係を例示するグラフである。   Further, by using the crystal growth temperature of the p-type cladding layer 72 as a comparison parameter, all other configurations are the same as those of the short wavelength light emitting LED 100 of FIG. The strength was compared. FIG. 9 is a graph illustrating the relationship between the emission intensity (EL) of these short wavelength light emitting LEDs and the crystal growth temperature of the p-type cladding layer 72.

ｐ型クラッド層の結晶成長温度を１０１５℃以上１０６０℃以下にすることで、高い発光強度が得られる。より望ましくは、１０２０℃以上１０５０℃以下にすると良い。この温度が高すぎると、活性層６０などの９００℃以下で先に結晶成長させた半導体層に熱的ダメージが及ぶので、素子の寿命や静電耐圧の面で望ましくない。   By setting the crystal growth temperature of the p-type cladding layer to 1015 ° C. or more and 1060 ° C. or less, high emission intensity can be obtained. More desirably, the temperature is set to 1020 ° C. or higher and 1050 ° C. or lower. If this temperature is too high, the semiconductor layer, such as the active layer 60, which has been crystal-grown at 900 ° C. or lower previously will be thermally damaged, which is undesirable in terms of device life and electrostatic withstand voltage.

〔その他の最適化条件〕
本発明の実施形態は、上記の形態に限定されるものではなく、その他にも幾つかの最適化条件が存在する。即ち、この様な変形或いは最適化などによっても、本発明の作用に基づいて本発明の効果を得ることができる。 [Other optimization conditions]
The embodiment of the present invention is not limited to the above-described form, and there are some other optimization conditions. That is, the effects of the present invention can be obtained based on the operation of the present invention even by such deformation or optimization.

（ｎ型クラッド層５２）
上記の様に、超格子構造のｎ型クラッド層（ｎ型クラッド層５２）を設け、その超格子構造において略周期的な積層構造を構成する周期構造の１単位を組成比が相異なる２層のIII族窒化物系化合物半導体から構成する場合、この１単位を上記のｎ型クラッド層において、２０周期以上４５周期以下の範囲で繰り返し積層すると良い。この様な超格子構造のｎ型クラッド層には、ｎ型コンタクト層などから上記の量子井戸層に転位やクラックが伝播するのを抑制する効果があり、また、超格子構造は、素子内部の応力を緩和する作用をも奏するので、量子井戸層自身が柔軟になったこととの相乗効果によって、量子井戸層に転位やクラックが生じ難くなる。より望ましくは、３０周期以上３８周期以下の範囲で繰り返すと良い。 (N-type cladding layer 52)
As described above, an n-type clad layer (n-type clad layer 52) having a superlattice structure is provided, and one unit of a periodic structure constituting a substantially periodic laminated structure in the superlattice structure is divided into two layers having different composition ratios. In the case where the group III nitride compound semiconductor is used, one unit is preferably stacked repeatedly in the range of 20 cycles or more and 45 cycles or less in the n-type cladding layer. The n-type clad layer having such a superlattice structure has an effect of suppressing dislocations and cracks from the n-type contact layer and the like to the quantum well layer. Since it also acts to relieve stress, dislocations and cracks are less likely to occur in the quantum well layer due to a synergistic effect with the flexibility of the quantum well layer itself. More preferably, it may be repeated within a range of 30 cycles or more and 38 cycles or less.

その理由は、上記のｎ型クラッド層の超格子構造の周期構造の１単位の繰り返し数に付いては、２０〜６０周期程度までの間で、発光強度が繰り返し数と共に徐々に増加する傾向があるが、一方、積層数が３８を超える辺りから、転位やクラックの発生密度も徐々に高くなる傾向があるためである。転位やクラックの発生密度が高くなると、素子の素子寿命や静電耐圧の点で不利であるので、これらの事情を総合的に考慮すると、より望ましくは、３０周期以上３８周期以下の範囲で繰り返すと良いと考えられる。   The reason is that the emission intensity tends to gradually increase with the number of repetitions between about 20 to 60 periods for the number of repetitions of one unit of the periodic structure of the superlattice structure of the n-type cladding layer. On the other hand, it is because the generation density of dislocations and cracks tends to gradually increase from the number of stacked layers exceeding 38. Higher dislocation and crack generation density is disadvantageous in terms of element lifetime and electrostatic withstand voltage, and in view of these circumstances, it is more desirable to repeat within a range of 30 cycles or more and 38 cycles or less. It is considered good.

（堆積層６ａの堆積時間）
また、上記の堆積層の厚さ又は面積占有率は、その堆積時間に換算して、１秒以上１６秒以下にすると良い。また、望ましくは、その堆積時間は、６秒以上１４秒以下である。また、更に望ましくは、９秒から１３秒の間が理想的である。
堆積層６ａは、量子井戸層６ｂにおけるバンドギャップの空間的ゆらぎを形成するために堆積させるものであるので、この堆積層６ａを堆積させる面における堆積層６ａの面積占有率は、小さ過ぎても大きすぎても、そのゆらぎ生成効果は得難くなる。上記の適正範囲はこれらの事情を踏まえたものであり、この様な条件設定によれば、堆積層６ａの形成状態（離散状態）を最適にすることができるので、高い発光強度を得ることができる。 (Deposition time of the deposition layer 6a)
In addition, the thickness or area occupancy of the deposited layer is preferably 1 second to 16 seconds in terms of the deposition time. Desirably, the deposition time is 6 seconds or longer and 14 seconds or shorter. More desirably, the time is between 9 seconds and 13 seconds.
The deposited layer 6a is deposited to form a band gap spatial fluctuation in the quantum well layer 6b. Therefore, even if the area occupancy of the deposited layer 6a on the surface on which the deposited layer 6a is deposited is too small. If it is too large, it is difficult to obtain the fluctuation generating effect. The appropriate range described above is based on these circumstances, and according to such a condition setting, the formation state (discrete state) of the deposited layer 6a can be optimized, so that high emission intensity can be obtained. it can.

上記の実施例においては、紫外線発光の発光ダイオード（ＬＥＤ）の例を示したが、本発明は、紫外線発光の半導体レーザについても本発明を適用することができる。   In the above embodiment, an example of a light emitting diode (LED) emitting ultraviolet light is shown, but the present invention can also be applied to a semiconductor laser emitting ultraviolet light.

本発明の実施例に係わる短波長発光ＬＥＤ１００の断面図Sectional drawing of the short wavelength light emission LED100 concerning the Example of this invention. 短波長発光ＬＥＤ１００の発光強度（ＥＬ）と堆積層６ａの積層時間との関係を例示するグラフGraph illustrating the relationship between the light emission intensity (EL) of the short wavelength light emitting LED 100 and the stacking time of the deposited layer 6a 短波長発光ＬＥＤ１００の発光強度（ＥＬ）とＳｉＮから成る第２バッファ層の有無との関係を例示するグラフThe graph which illustrates the relationship between the light emission intensity (EL) of short wavelength light emission LED100, and the presence or absence of the 2nd buffer layer which consists of SiN. 短波長発光ＬＥＤ１００の発光強度（ＥＬ）とＳｉＮから成る第２バッファ層の積層条件との関係を例示するグラフThe graph which illustrates the relationship between the light emission intensity (EL) of the short wavelength light emitting LED 100 and the lamination condition of the second buffer layer made of SiN 短波長発光ＬＥＤ１００の発光強度（ＥＬ）とｎ型クラッド層５２のキャリア濃度との関係を例示するグラフThe graph which illustrates the relationship between the light emission intensity (EL) of the short wavelength light emitting LED 100 and the carrier concentration of the n-type cladding layer 52 短波長発光ＬＥＤ１００の発光強度（ＥＬ）と活性層６０の量子井戸層６ｂの積層数との関係を例示するグラフThe graph which illustrates the relationship between the light emission intensity (EL) of short wavelength light emission LED100, and the number of lamination | stacking of the quantum well layer 6b of the active layer 60 短波長発光ＬＥＤ１００の発光強度（ＰＬ）と、活性層６０の量子障壁層６ｃの成長時間との関係を例示するグラフA graph illustrating the relationship between the emission intensity (PL) of the short wavelength light emitting LED 100 and the growth time of the quantum barrier layer 6c of the active layer 60 短波長発光ＬＥＤ１００の発光強度（ＥＬ）と、ｐ型クラッド層７２の井戸層の結晶成長工程におけるＡｌ（ＣＨ3）3供給量との関係を例示するグラフA graph illustrating the relationship between the emission intensity (EL) of the short wavelength light emitting LED 100 and the supply amount of Al (CH 3 ) 3 in the crystal growth process of the well layer of the p-type cladding layer 72 短波長発光ＬＥＤ１００の発光強度（ＥＬ）とｐ型クラッド層７２の結晶成長温度との関係を例示するグラフA graph illustrating the relationship between the emission intensity (EL) of the short wavelength light emitting LED 100 and the crystal growth temperature of the p-type cladding layer 72

１００ ： 短波長発光ＬＥＤ
１０ ： サファイア基板
２０ ： 低温成長バッファ層
３０ ： 下地層
４０ ： ｎ型コンタクト層
５１ ： ｎ型中間層
５２ ： ｎ型クラッド層（超格子構造）
６０ ： 活性層
７１ ： ｐ型ブロック層
７２ ： ｐ型クラッド層（超格子構造）
８０ ： ｐ型コンタクト層 100: Short wavelength light emitting LED
10: Sapphire substrate 20: Low temperature growth buffer layer 30: Underlayer 40: n-type contact layer 51: n-type intermediate layer 52: n-type cladding layer (superlattice structure)
60: Active layer 71: p-type block layer 72: p-type cladding layer (superlattice structure)
80: p-type contact layer

Claims (2)

III族窒化物系化合物半導体を結晶成長によって複数層積層することにより形成される多重量子井戸構造の活性層を有する半導体発光素子において、
結晶成長基板と、
低温成長バッファ層と、
下地層とを有し、
前記低温成長バッファ層は、前記結晶成長基板の結晶成長面上に積層された窒化ケイ素から成る第１バッファ層と、前記第１バッファ層の上に積層されたＧａＮ層とから成り、
前記下地層は、III族窒化物系化合物半導体から成る層と、窒化ケイ素から成る第２バッファ層と、III族窒化物系化合物半導体から成る層とが積層されており、
前記第１バッファ層と前記第２バッファ層はそれぞれ何れも、離散的に、斑状または島状に積層されており、
前記活性層を構成する量子井戸層は、ＡｌzＩｎyＧａ1-z-yＮ（０≦ｚ＜１，０＜ｙ＜１，０＜ｚ＋ｙ≦１）から形成されており、
前記量子井戸層はそれぞれ何れも、その直下に窒化ケイ素から成る堆積層を有し、
前記堆積層は、少なくとも前記量子井戸層に生じる転位の平均発生周期よりも短い間隔又は周期で、離散的に斑状または島状に堆積されていることを特徴とする半導体発光素子。 In a semiconductor light emitting device having an active layer of a multiple quantum well structure formed by laminating a plurality of layers of a group III nitride compound semiconductor by crystal growth,
A crystal growth substrate;
A low temperature growth buffer layer;
An underlayer,
The low temperature growth buffer layer is composed of a first buffer layer made of is silicon nitride stacked on the crystal growth surface of the crystal growth substrate, the GaN layer which is the product layer on the first buffer layer,
The underlayer includes a layer made of a group III nitride compound semiconductor, a second buffer layer made of silicon nitride, and a layer made of a group III nitride compound semiconductor,
Both each said first buffer layer is the second buffer layer, a discrete manner, is stacked patchy or islands,
The quantum well layer constituting the active layer is formed of Al z In y Ga 1-zy N (0 ≦ z <1, 0 <y <1, 0 <z + y ≦ 1),
Each of the quantum well layers has a deposited layer made of silicon nitride immediately below it.
The semiconductor light emitting device, wherein the deposited layer is discretely deposited in spots or islands at intervals or periods shorter than an average generation period of dislocations generated in the quantum well layer. 前記活性層における前記量子井戸層の積層数は、３層以上１０層以下であることを特徴とする請求項１に記載の半導体発光素子。 2. The semiconductor light emitting device according to claim 1 , wherein the number of stacked quantum well layers in the active layer is 3 or more and 10 or less.
JP2003435410A 2003-12-26 2003-12-26 Group III nitride compound semiconductor light emitting device Expired - Lifetime JP4553583B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003435410A JP4553583B2 (en) 2003-12-26 2003-12-26 Group III nitride compound semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003435410A JP4553583B2 (en) 2003-12-26 2003-12-26 Group III nitride compound semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JP2005197292A JP2005197292A (en) 2005-07-21
JP4553583B2 true JP4553583B2 (en) 2010-09-29

Family

ID=34815500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003435410A Expired - Lifetime JP4553583B2 (en) 2003-12-26 2003-12-26 Group III nitride compound semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JP4553583B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150088117A (en) * 2014-01-23 2015-07-31 엘지이노텍 주식회사 Light emitting device and lighting system having the same

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721160B1 (en) 2005-10-31 2007-05-23 삼성전기주식회사 Nitride semiconductor device
JP2007214384A (en) 2006-02-09 2007-08-23 Rohm Co Ltd Nitride semiconductor element
KR100821220B1 (en) 2006-06-29 2008-04-10 서울옵토디바이스주식회사 Light emitting device of a nitride compound semiconductor having multi buffer layers and the fabrication method thereof
US8338836B2 (en) * 2006-11-21 2012-12-25 Seoul Opto Device Co., Ltd. Light emitting device for AC operation
JP2008227103A (en) * 2007-03-12 2008-09-25 Rohm Co Ltd GaN-BASED SEMICONDUCTOR LIGHT EMITTING ELEMENT
TWI466314B (en) * 2008-03-05 2014-12-21 Advanced Optoelectronic Tech Light emitting device of iii-nitride based semiconductor
JP2011066073A (en) * 2009-09-15 2011-03-31 Showa Denko Kk Semiconductor light-emitting element
JP5421442B1 (en) 2012-09-26 2014-02-19 株式会社東芝 Nitride semiconductor wafer, nitride semiconductor device, and method of manufacturing nitride semiconductor wafer
JP2014068018A (en) * 2013-10-07 2014-04-17 Toshiba Corp Semiconductor light-emitting element and method of manufacturing semiconductor light-emitting element
CN104409586B (en) * 2014-11-13 2017-02-15 湘能华磊光电股份有限公司 GaN-based III-V compound semiconductor LED (light emitting diode) epitaxial wafer and production method thereof
US11139342B2 (en) 2018-09-26 2021-10-05 Nitride Semiconductors Co., Ltd. UV-LED and display

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000313733A (en) * 1999-04-30 2000-11-14 Sanyo Chem Ind Ltd Production of spherical resin particle dispersion and spherical resin particle
JP2001057460A (en) * 1999-06-10 2001-02-27 Nichia Chem Ind Ltd Nitride semiconductor laser element
JP2002033513A (en) * 2000-07-13 2002-01-31 Shiro Sakai Light emitting element
JP2002033288A (en) * 2000-07-18 2002-01-31 Sony Corp Crystal growing method
JP2002076522A (en) * 2000-09-01 2002-03-15 Nec Corp Nitride semiconductor laser
JP3285341B2 (en) * 2000-06-01 2002-05-27 士郎 酒井 Method of manufacturing gallium nitride based compound semiconductor
JP2003110197A (en) * 2001-09-28 2003-04-11 Toshiba Corp Nitride semiconductor light emission device, nitride semiconductor device and method for manufacturing the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3374737B2 (en) * 1997-01-09 2003-02-10 日亜化学工業株式会社 Nitride semiconductor device
JP3904709B2 (en) * 1997-02-21 2007-04-11 株式会社東芝 Nitride-based semiconductor light-emitting device and method for manufacturing the same
JP3545197B2 (en) * 1998-03-23 2004-07-21 三洋電機株式会社 Semiconductor device and method of manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000313733A (en) * 1999-04-30 2000-11-14 Sanyo Chem Ind Ltd Production of spherical resin particle dispersion and spherical resin particle
JP2001057460A (en) * 1999-06-10 2001-02-27 Nichia Chem Ind Ltd Nitride semiconductor laser element
JP3285341B2 (en) * 2000-06-01 2002-05-27 士郎 酒井 Method of manufacturing gallium nitride based compound semiconductor
JP2002033513A (en) * 2000-07-13 2002-01-31 Shiro Sakai Light emitting element
JP2002033288A (en) * 2000-07-18 2002-01-31 Sony Corp Crystal growing method
JP2002076522A (en) * 2000-09-01 2002-03-15 Nec Corp Nitride semiconductor laser
JP2003110197A (en) * 2001-09-28 2003-04-11 Toshiba Corp Nitride semiconductor light emission device, nitride semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150088117A (en) * 2014-01-23 2015-07-31 엘지이노텍 주식회사 Light emitting device and lighting system having the same
KR102119836B1 (en) 2014-01-23 2020-06-05 엘지이노텍 주식회사 Light emitting device and lighting system having the same

Also Published As

Publication number Publication date
JP2005197292A (en) 2005-07-21

Similar Documents

Publication Publication Date Title
JP5048236B2 (en) Semiconductor light emitting device and method for manufacturing semiconductor light emitting device
TWI479683B (en) Nitride semiconductor light-emitting device and method for producing the same
US20100133506A1 (en) Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor
JP4601950B2 (en) Group III nitride compound semiconductor light emitting device
JP2001160627A5 (en)
JP2001160627A (en) Group iii nitride compound semiconductor light emitting element
JP2011176240A (en) Semiconductor light emitting device, and method of manufacturing the same
JP5991176B2 (en) Group III nitride semiconductor light emitting device manufacturing method
JP2001203385A (en) Nitride semiconductor light emitting diode
JP2006332258A (en) Nitride semiconductor device and its manufacturing method
JP4553583B2 (en) Group III nitride compound semiconductor light emitting device
WO2014061692A1 (en) Nitride semiconductor light emitting element
JP6010869B2 (en) Group III nitride semiconductor light emitting device
JP2002043618A (en) Method for manufacturing nitride semiconductor
WO2006057485A1 (en) Iii-nitride semiconductor light emitting device
JP4940670B2 (en) Method for fabricating nitride semiconductor light emitting device
JP4645225B2 (en) Manufacturing method of semiconductor device
JP5234814B2 (en) Manufacturing method of nitride semiconductor light emitting device
JP2006237254A5 (en)
JP4457691B2 (en) GaN-based semiconductor device manufacturing method
JP5423026B2 (en) Group III nitride semiconductor light emitting device and method of manufacturing the same
JP2010003913A (en) Nitride semiconductor light-emitting diode element and method of manufacturing the same
TWI567877B (en) Manufacturing method of nitride semiconductor device
JPH09266326A (en) Iii group nitride compound semiconductor light emitting device
JP2006237539A (en) Method for manufacturing semiconductor element of group iii nitride compound

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060529

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090619

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090623

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090820

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100713

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100713

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130723

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4553583

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term