JP4645225B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- JP4645225B2 JP4645225B2 JP2005049416A JP2005049416A JP4645225B2 JP 4645225 B2 JP4645225 B2 JP 4645225B2 JP 2005049416 A JP2005049416 A JP 2005049416A JP 2005049416 A JP2005049416 A JP 2005049416A JP 4645225 B2 JP4645225 B2 JP 4645225B2
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本発明は、III族窒化物系化合物半導体から成る半導体層を基板上に複数層積層して形成される半導体素子に関し、特に、素子の静電耐圧特性を改善するための半導体の積層構造やその製造方法に関する。ただし、ここで言う半導体素子には、半導体レーザや発光ダイオード等の半導体発光素子の他にも、半導体受光素子などをも含む。
本発明は、半導体素子の静電耐圧特性の改善に大いに有用なものである。
The present invention relates to a semiconductor element formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate, and more particularly to a semiconductor laminated structure for improving the electrostatic withstand voltage characteristics of the element and its It relates to a manufacturing method. However, the semiconductor element referred to here includes a semiconductor light receiving element and the like in addition to a semiconductor light emitting element such as a semiconductor laser or a light emitting diode.
The present invention is very useful for improving the electrostatic withstand voltage characteristics of semiconductor elements.
半導体素子の静電耐圧特性は、例えば、２００Ｖ〜２０００Ｖ程度の逆向きの静電圧をその半導体素子に印加する耐久テスト（例：人体モデル（ＨＢＭ）のＥＳＤ試験）などを実施して、その時のその半導体素子の生存率などによって評価することができる。例えばこの様な静電耐圧特性の向上を目的として提案された窒化物半導体素子としては、下記の特許文献１に記載されているものなどが公知である。本願図３にこの特許文献１中の実施例１に記載されている半導体素子（ＬＥＤ）の断面図（特許文献１中の図１）を示す。この半導体素子はこの図に示す様に、基板１、バッファ層２、アンドープＧａＮ層３、ｎ側コンタクト層４、ｎ側第１多層膜層５、ｎ側第２多層膜層６、活性層７、ｐ側多層膜クラッド層８、ｐ側ＧａＮコンタクト層９、ｐ電極１０、及びｎ電極１２などを有して成る。中でも特に、ｎ側第１多層膜層５とｎ側第２多層膜層６は、この従来の半導体素子の静電耐圧の向上に寄与する部分である。 The electrostatic withstand voltage characteristic of a semiconductor element is, for example, an endurance test (eg, an ESD test of a human body model (HBM)) in which a reverse electrostatic voltage of about 200 V to 2000 V is applied to the semiconductor element. It can be evaluated by the survival rate of the semiconductor element. For example, as a nitride semiconductor device proposed for the purpose of improving the electrostatic withstand voltage characteristics, those described in Patent Document 1 below are known. FIG. 3 of the present application shows a cross-sectional view (FIG. 1 in Patent Document 1) of the semiconductor element (LED) described in Example 1 in Patent Document 1. As shown in the figure, the semiconductor element includes a substrate 1, a buffer layer 2, an undoped GaN layer 3, an n-side contact layer 4, an n-side first multilayer film layer 5, an n-side second multilayer film layer 6, and an active layer 7. , A p-side multilayer clad layer 8, a p-side GaN contact layer 9, a p-electrode 10, an n-electrode 12, and the like. In particular, the n-side first multilayer film layer 5 and the n-side second multilayer film layer 6 are portions that contribute to the improvement of the electrostatic withstand voltage of this conventional semiconductor element.
静電耐圧の向上に寄与する構造を供する上記従来のｎ側第１多層膜層５とｎ側第２多層膜層６の中には、不純物が添加された半導体層が１層だけ存在する。即ち、ｎ側第１多層膜層５及びｎ側第２多層膜層６の中では、ｎ側第１多層膜層５の一部を構成するＳｉドープのｎ形の中間層５ｂ以外の各半導体層は、全てアンドープの半導体から形成されている。
しかしながら、静電耐圧の向上に寄与する構造を供する例えば上記の様な多層膜構造（ｎ側第１多層膜層５及びｎ側第２多層膜層６）では、各膜厚の最適化を実施しても、高い静電圧が印加された際に、キャリアが素子中の結晶構造の欠陥に集中する現象を必ずしも十分には緩和することができなかった。 However, in the multilayer film structure (n-side first multilayer film layer 5 and n-side second multilayer film layer 6) as described above that provides a structure that contributes to improvement in electrostatic withstand voltage, each film thickness is optimized. Even when a high electrostatic voltage is applied, however, the phenomenon of carriers concentrating on defects in the crystal structure in the device cannot always be sufficiently mitigated.
例えば、上記の様な従来構造の発光ダイオードにおいて、１０００Ｖ〜１８００Ｖ程度の逆向きの静電圧を印加する耐久テスト（：人体モデル（ＨＢＭ）のＥＳＤ試験）を実施した場合には、十分な出力性能を維持したまま、試験後の生存率を十分に引き上げることは困難であった。 For example, in a conventional light emitting diode as described above, when an endurance test (an ESD test of a human body model (HBM)) applying a reverse electrostatic voltage of about 1000 V to 1800 V is performed, sufficient output performance is achieved. It was difficult to sufficiently increase the survival rate after the test while maintaining the above.
一般に、静電耐圧の向上に寄与する構造を供する例えば上記の様な多層膜構造の中の無添加の半導体層の膜厚を厚くするほど静電耐圧特性が向上するわけではなく、結晶成長温度の設定によっては、膜厚が薄い方がむしろ素子の静電耐圧特性が向上する無添加の半導体層もあり得、その傾向は単純には一定しない。また、その様な無添加の半導体層の膜厚を厚くするほど、その増大に反して素子の出力性能は低下してしまう。したがって、その半導体素子の出力性能を維持した上で、その半導体素子の静電耐圧特性を向上させることは困難であった。 In general, providing a structure that contributes to an improvement in electrostatic withstand voltage, for example, as the thickness of an additive-free semiconductor layer in the multilayer film structure as described above increases, the electrostatic withstand voltage characteristics do not improve, but the crystal growth temperature Depending on the setting, there may be an additive-free semiconductor layer in which the electrostatic withstand voltage characteristic of the device is improved rather as the film thickness is smaller, and the tendency is not simply constant. Further, as the film thickness of such an additive-free semiconductor layer is increased, the output performance of the element is lowered against the increase. Therefore, it is difficult to improve the electrostatic withstand voltage characteristics of the semiconductor element while maintaining the output performance of the semiconductor element.
本発明は、上記の課題を解決するために成されたものであり、その目的は、半導体素子の発光性能または受光性能を従来程度に維持するかまたは向上させつつ、その半導体素子の静電耐圧特性を従来よりも改善することである。 The present invention has been made to solve the above-mentioned problems, and its purpose is to maintain or improve the light emitting performance or light receiving performance of a semiconductor element to the conventional level, while maintaining the electrostatic withstand voltage of the semiconductor element. The characteristic is to improve compared to the conventional one.
上記の課題を解決するためには、以下の手段が有効である。
即ち、本発明の第１の手段は、III族窒化物系化合物半導体から成る半導体層を基板上に複数層積層して形成される半導体素子であって、活性層とｎ形のコンタクト層との間にそのｎ形のコンタクト層の側から、不純物が無添加の無添加半導体層、ｎ形の不純物が添加された添加半導体層の順で２層１組にて構成された耐電圧構造を２組有し、上記の活性層の発光ピーク波長又は受光ピーク波長を４５０ｎｍ以上４８０ｎｍ以下とし、上記のｎ形のコンタクト層の側から数えて２組目の耐電圧構造を構成する無添加半導体層の膜厚を、１００ｎｍ以上３００ｎｍ以下とした半導体素子の製造方法において、ｎ形のコンタクト層の側から数えて１組目の耐電圧構造を構成する添加半導体層の結晶成長温度、及び、ｎ形のコンタクト層の側から数えて２組目以降の耐電圧構造を構成する半導体層の結晶成長温度を何れも８００℃以上９００℃以下にし、ｎ形のコンタクト層の側から数えて１組目の耐電圧構造を構成する無添加半導体層の結晶成長温度を１０００℃以上１２００℃以下にすることを特徴とする半導体素子の製造方法である。この無添加半導体層の膜厚は、より望ましくは、１６０ｎｍ以上２４０ｎｍ以下にすると良い。
In order to solve the above problems, the following means are effective.
That is, the first means of the present invention is a semiconductor element formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate, and comprises an active layer and an n-type contact layer. from the side of the n-type contact layer between, additive-free semiconductor layer of impurity-free addition, the withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added 2 set has an emission peak wavelength or the light receiving peak wavelength of the active layer is 450nm or more 480nm or less, the additive-free semiconductor layer constituting the second set of withstand voltage structure counted from the side of the n-type contact layer of the In the method for manufacturing a semiconductor element having a thickness of 100 nm to 300 nm , the crystal growth temperature of the added semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the n-type Counting from the contact layer side The crystal growth temperatures of the semiconductor layers constituting the second and subsequent sets of withstand voltage structures are all set to 800 ° C. or more and 900 ° C. or less, and the first set of withstand voltage structures constituting the first set of withstand voltage structures are counted from the n-type contact layer side. A method for manufacturing a semiconductor element, wherein the crystal growth temperature of the additional semiconductor layer is set to 1000 ° C. or more and 1200 ° C. or less. The film thickness of the additive-free semiconductor layer is more preferably 160 nm or more and 240 nm or less.
また、ｎ側とｐ側の両方のコンタクト層に対してそれぞれ同時に上記の構造を適用しても良い。
また、上記の不純物は、複数の種類の不純物を同時に添加しても良い。また、ｎ形の不純物とｐ形の不純物とを同時に添加しても良い。ただし、両方の形の不純物を混在させて１層の添加半導体層を形成する場合には、例えばｎ形コンタクト層では、ｐ形の不純物よりもｎ形の不純物の方をより高い濃度で用いるものとする。
なお、上記の半導体素子は、発光ダイオードや半導体レーザなどの半導体発光素子であっても良いし、半導体受光素子であっても良い。また、上記の活性層は、ＭＱＷ構造のものであっても、ＳＱＷ構造のものであっても良い。
Further, the above structure may be applied simultaneously to both the n-side and p-side contact layers.
In addition, a plurality of types of impurities may be added at the same time. Further, an n-type impurity and a p-type impurity may be added simultaneously. However, when one additive semiconductor layer is formed by mixing both types of impurities, for example, an n-type contact layer uses n-type impurities at a higher concentration than p-type impurities. And
The semiconductor element may be a semiconductor light emitting element such as a light emitting diode or a semiconductor laser, or a semiconductor light receiving element. The active layer may have an MQW structure or an SQW structure.
また、本発明の第２の手段は、III族窒化物系化合物半導体から成る半導体層を基板上に複数層積層して形成される半導体素子であって、活性層とｎ形のコンタクト層との間にそのｎ形のコンタクト層の側から、不純物が無添加の無添加半導体層、ｎ形の不純物が添加された添加半導体層の順で２層１組にて構成された耐電圧構造を２組有し、上記の活性層の発光ピーク波長又は受光ピーク波長を、５１０ｎｍ以上５５０ｎｍ以下以下とし、上記のｎ形のコンタクト層の側から数えて２組目の前記耐電圧構造を構成する無添加半導体層の膜厚を、１０ｎｍ以上５０ｎｍ以下とした半導体素子の製造方法において、ｎ形のコンタクト層の側から数えて１組目の耐電圧構造を構成する添加半導体層の結晶成長温度、及び、ｎ形のコンタクト層の側から数えて２組目以降の耐電圧構造を構成する半導体層の結晶成長温度を何れも８００℃以上９００℃以下にし、ｎ形のコンタクト層の側から数えて１組目の耐電圧構造を構成する無添加半導体層の結晶成長温度を１０００℃以上１２００℃以下にすることを特徴とする半導体素子の製造方法である。この無添加半導体層の膜厚は、より望ましくは、２５ｎｍ以上３５ｎｍ以下にすると良い。 A second means of the present invention is a semiconductor element formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate, and comprises an active layer and an n-type contact layer. from the side of the n-type contact layer between, additive-free semiconductor layer of impurity-free addition, the withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added 2 set has an emission peak wavelength or the light receiving peak wavelength of the active layer, the following 550nm inclusive 510 nm, no additives constituting the withstand voltage structure of the second set are counted from the side of the n-type contact layer of the In the method for manufacturing a semiconductor element in which the thickness of the semiconductor layer is 10 nm or more and 50 nm or less , the crystal growth temperature of the added semiconductor layer constituting the first set of withstand voltage structures counted from the n-type contact layer side, and on the n-type contact layer side The crystal growth temperatures of the semiconductor layers constituting the second and subsequent sets of withstand voltage structures are all set to 800 ° C. to 900 ° C., and the first set of withstand voltage structures are configured from the n-type contact layer side. The semiconductor element manufacturing method is characterized in that the crystal growth temperature of the additive-free semiconductor layer is 1000 ° C. or more and 1200 ° C. or less. The film thickness of this additive-free semiconductor layer is more preferably 25 nm or more and 35 nm or less.
また、本発明の第３の手段は、上記の第１又は第２の手段において、上記の無添加半導体層を、不純物が無添加の窒化ガリウム（ＧａＮ）から構成することである。
また、本発明の第４の手段は、上記の第１乃至第３の何れか１つの手段において、上記の添加半導体層を、シリコン（Ｓｉ）を添加した窒化ガリウム（ＧａＮ）から構成することである。
According to a third means of the present invention, in the first or second means described above, the additive-free semiconductor layer is made of gallium nitride (GaN) to which no impurity is added.
According to a fourth means of the present invention, in any one of the first to third means, the additive semiconductor layer is made of gallium nitride (GaN) to which silicon (Si) is added. is there.
より望ましくは、この無添加半導体層の結晶成長温度は、１０５０℃以上１１５０℃以下にすると良い。 More preferably, the crystal growth temperature of the additive-free semiconductor layer is 1050 ° C. or higher and 1150 ° C. or lower.
より望ましくは、この添加半導体層の結晶成長温度は、８３０℃以上８７０℃以下にすると良い。 More desirably, the crystal growth temperature of the added semiconductor layer is 830 ° C. or higher and 870 ° C. or lower.
以上の本発明の手段により、前記の課題を効果的、或いは合理的に解決することができる。 By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.
以上の本発明の手段によって得られる効果は以下の通りである。
即ち、本発明の第１又は第２の手段によれば、２層１組にて構成される上記の耐電圧構造が２組半導体素子の中に形成されるので、この静電耐圧特性の向上に寄与する上記の２組の耐電圧構造から成る部分において、少なくとも２層以上の添加半導体層が具備される。この構成によれば、高い静電圧が印加された際にキャリアが素子中の結晶構造の欠陥に集中する現象を従来よりも良好に緩和することができる。したがって、本発明の第１又は第２の手段によれば、発光強度や閾値電圧などの素子の発光性能または受光性能を少なくとも従来程度に十分確保したまま、素子の静電耐圧特性を従来よりも更に良好に得ることができる。
The effects obtained by the above-described means of the present invention are as follows.
In other words, according to the first or second means of the present invention, the above-mentioned withstand voltage structure constituted by one set of two layers is formed in two sets of semiconductor elements, so that the improvement of the electrostatic withstand voltage characteristics is achieved. In the portion composed of the two sets of withstand voltage structures that contribute to the above, at least two or more additional semiconductor layers are provided. According to this configuration, when a high electrostatic voltage is applied, the phenomenon of carriers concentrating on the defects in the crystal structure in the device can be alleviated better than before. Therefore, according to the first or second means of the present invention, the electrostatic withstand voltage characteristic of the element is improved as compared with the prior art while ensuring the light emitting performance or light receiving performance of the element such as the light emission intensity and the threshold voltage at least sufficiently. It can be obtained even better.
また、結晶成長基板に近い側である下方側にｎ形の半導体層を積層し、その反対側である上方側にｐ形の半導体層を積層する場合に、本発明の第１又は第２の手段によれば、上記の耐電圧構造が、結晶成長基板に近い側のコンタクト層に隣接または接近して２組形成される。したがって、本発明の第１又は第２の手段によれば、活性層の結晶成長温度よりも高い温度で結晶成長させる高温成長層を上記の耐電圧構造の中に形成しても、その結晶成長過程の高温環境における熱ダメージを活性層に与える恐れがない。 In the case where an n-type semiconductor layer is stacked on the lower side, which is closer to the crystal growth substrate, and a p-type semiconductor layer is stacked on the upper side, which is the opposite side, the first or second of the present invention. According to the means, two sets of the withstand voltage structures are formed adjacent to or close to the contact layer on the side close to the crystal growth substrate. Therefore, according to the first or second means of the present invention, even if a high-temperature growth layer for crystal growth at a temperature higher than the crystal growth temperature of the active layer is formed in the above-mentioned withstand voltage structure, the crystal growth There is no risk of heat damage to the active layer in the high temperature environment of the process.
このため、結晶成長基板に近い側である下方側にｎ形の半導体層を積層し、その反対側である上方側にｐ形の半導体層を積層する場合に、活性層の結晶品質と上記の耐電圧構造の結晶品質とを同時に高く確保することが可能となり、よって、素子の発光性能または受光性能を効果的に維持または向上させることができる。 Therefore, when an n-type semiconductor layer is stacked on the lower side, which is closer to the crystal growth substrate, and a p-type semiconductor layer is stacked on the upper side, which is the opposite side, the crystal quality of the active layer and the above-mentioned It is possible to ensure a high crystal quality of the withstand voltage structure at the same time, so that the light emitting performance or light receiving performance of the device can be effectively maintained or improved.
また、外部量子効率を向上させるために、結晶成長面に凹凸を有する加工基板を結晶成長基板として用いる場合には、その凹凸によって結晶の欠陥が形成され易くなるので、素子に高い静電圧を掛けた際の欠陥へのキャリアの集中は、その加工基板に近い側でより発生し易くなる。
したがって、その様な加工基板に近い側である下方側にｎ形の半導体層を積層し、その反対側である上方側にｐ形の半導体層を積層する場合に本発明の第１又は第２の手段を用いれば、加工基板に近い側である下方側にｎ形の半導体層を積層し、かつ、ｐ側のみに上記の耐電圧構造を形成する場合よりも、より効果的に上記のキャリアの集中を緩和することができる。
また、各波長の光を発光または受光する各半導体素子において、発光性能または受光性能を従来以上に確保しつつ、静電耐圧特性を従来よりも向上させることができる。この２組目の耐電圧構造の無添加半導体層の膜厚が薄過ぎるとこの無添加半導体層自身の抵抗が小さくなり過ぎるので、静電耐圧特性の改善を図ることが難しくなる。また、この無添加半導体層の膜厚が厚過ぎると、次の何れかの理由によって、素子の発光性能または受光性能を従来以上に確保することが難しくなる。
（理由１）この無添加半導体層自身の抵抗が大きくなり過ぎるため。
（理由２）この無添加半導体層を後述の８００℃〜９００℃程度の比較的低い結晶成長温度で成長させると、この無添加半導体層の表面に適度の荒れを形成することができる。この時、この無添加半導体層の膜厚が厚過ぎると、その表面荒れによってこの無添加半導体層の結晶品質や、その後に結晶成長させる例えば活性層などの半導体層の結晶品質を良好に確保することが困難になるため。
なお、この２組目の耐電圧構造の無添加半導体層の、８００℃〜９００℃程度の結晶成長温度における表面荒れや厚膜化に伴って、活性層などの半導体層の結晶品質もが劣化する現象は、原子半径が大きいために格子不整合を招き易いインジウム（Ｉｎ）を活性層に比較的多く用いる緑色発光または緑色受光の半導体素子においてより顕著化し易い。
In addition, when a processed substrate having an uneven surface on the crystal growth surface is used as the crystal growth substrate in order to improve external quantum efficiency, crystal defects are easily formed by the uneven surface, and therefore a high electrostatic voltage is applied to the device. Concentration of carriers to defects at the time of occurrence is more likely to occur on the side closer to the processed substrate.
Therefore, when the n-type semiconductor layer is stacked on the lower side that is the side close to such a processed substrate and the p-type semiconductor layer is stacked on the upper side that is the opposite side, the first or second of the present invention. The above carrier is more effective than the case where an n-type semiconductor layer is stacked on the lower side, which is closer to the processing substrate, and the above-mentioned withstand voltage structure is formed only on the p side. Can be relaxed.
Further, in each semiconductor element that emits or receives light of each wavelength, the electrostatic withstand voltage characteristic can be improved as compared with the conventional one while ensuring the light emission performance or the light reception performance. If the film thickness of the additive-free semiconductor layer of the second set of withstand voltage structure is too thin, the resistance of the additive-free semiconductor layer itself becomes too small, making it difficult to improve the electrostatic withstand voltage characteristics. Further, if the film thickness of the additive-free semiconductor layer is too thick, it becomes difficult to ensure the light emitting performance or light receiving performance of the device more than the conventional one for any of the following reasons.
(Reason 1) The resistance of the additive-free semiconductor layer itself becomes too large.
(Reason 2) When the additive-free semiconductor layer is grown at a relatively low crystal growth temperature of about 800 ° C. to 900 ° C., which will be described later, moderate roughness can be formed on the surface of the additive-free semiconductor layer. At this time, if the film thickness of the additive-free semiconductor layer is too thick, the crystal quality of the additive-free semiconductor layer and the crystal quality of the semiconductor layer such as an active layer to be subsequently grown are ensured by the surface roughness. Because it becomes difficult.
In addition, the crystal quality of the semiconductor layer such as the active layer is deteriorated as the surface roughness or thickening of the second set of withstand voltage structure additive-free semiconductor layer at a crystal growth temperature of about 800 ° C. to 900 ° C. This phenomenon is more prominent in a green light-emitting or green light-receiving semiconductor element that uses a relatively large amount of indium (In) that easily causes lattice mismatch due to a large atomic radius.
また、本発明の第３または第４の手段によれば、上記の作用を良好に奏する好適または最適な耐電圧構造を一般的な材料を用いて簡単に形成することができる。 In addition, according to the third or fourth means of the present invention, a suitable or optimal withstand voltage structure that exhibits the above-described effects can be easily formed using a general material.
また、本発明の第１、第２の手段によれば、ｎ形のコンタクト層の側から数えて１組目の耐電圧構造を構成する無添加半導体層の結晶成長温度が比較的高温に設定されるため、この無添加半導体層の結晶品質を良好に確保することができる。このため、その後に結晶成長させる各半導体層の結晶品質が良好に確保されるので、素子の出力性能または入力性能を良好に確保することができる。 Further, according to the first and second means of the present invention, the crystal growth temperature of the additive-free semiconductor layer constituting the first withstand voltage structure counting from the n-type contact layer side is set to a relatively high temperature. Therefore, the crystal quality of the additive-free semiconductor layer can be ensured satisfactorily. For this reason, since the crystal quality of each semiconductor layer to be subsequently crystal-grown is ensured, the output performance or input performance of the element can be secured satisfactorily.
また、本発明の第１、第２の手段によれば、ｎ形のコンタクト層の側から数えて１組目の耐電圧構造を構成する添加半導体層の結晶成長温度、及び、コンタクト層の側から数えて２組目以降の耐電圧構造を構成する半導体層の結晶成長温度が何れも比較的低温に設定されるため、これらの半導体層の表面に適度の荒れを形成することができる。したがって、本発明によれば、高い静電圧が印加された際にキャリアが素子中の結晶構造の欠陥に集中する現象を従来よりも緩和することができる。したがって、本発明によれば、発光強度や閾値電圧などの素子の発光性能または受光性能を十分確保したまま、素子の静電耐圧特性を従来以上に得ることができる。 According to the first and second means of the present invention, the crystal growth temperature of the added semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the contact layer side Since the crystal growth temperatures of the semiconductor layers constituting the second and subsequent sets of withstand voltage structures counted from the above are set to relatively low temperatures, moderate roughness can be formed on the surfaces of these semiconductor layers. Therefore, according to this onset bright, it can be carriers when the high static voltage is applied to relieve than before the phenomenon of concentration in defects in the crystal structure in the device. Therefore, according to this onset bright, while a light-emitting performance or the light receiving device performance such as emission intensity and the threshold voltage was sufficiently secured, it is possible to obtain an electrostatic withstand voltage characteristics of the device more than before.
なお、上記の活性層における発光波長または受光波長を４５０ｎｍ以上４８０ｎｍ以下とする場合には、上記のコンタクト層の側から数えて２組目以降の各耐電圧構造を構成する各半導体層の膜厚の総和の値と、そのコンタクト層の側から数えて１組目の耐電圧構造を構成する添加半導体層の膜厚の値との合計値を１４０ｎｍ以上６００ｎｍ以下にすることがより望ましい。 When the emission wavelength or the light reception wavelength in the active layer is set to 450 nm or more and 480 nm or less, the film thickness of each semiconductor layer constituting each second withstand voltage structure counted from the contact layer side. It is more preferable that the total value of the sum of the values and the value of the film thickness of the added semiconductor layer constituting the first set of withstand voltage structures counted from the contact layer side be 140 nm or more and 600 nm or less.
この構成によって、発光特性または受光特性を従来以上に維持しつつ、静電耐圧特性を従来よりも改善することができる。なお、この膜厚が厚過ぎると前述の（理由１）または（理由２）による発光性能または受光性能の低下を招き、この膜厚が薄過ぎるとこれらの半導体層自身の抵抗が小さくなり過ぎて静電耐圧特性の向上が難しくなる。 With this configuration, the electrostatic withstand voltage characteristic can be improved as compared with the conventional one while maintaining the light emitting characteristic or the light receiving characteristic more than the conventional one. If the film thickness is too thick, the light emission performance or light reception performance due to the above (reason 1) or (reason 2) is reduced. If the film thickness is too thin, the resistance of these semiconductor layers themselves becomes too small. It becomes difficult to improve the electrostatic withstand voltage characteristics.
また、上記の活性層における発光波長または受光波長を５１０ｎｍ以上５５０ｎｍ以下とする場合には、上記のコンタクト層の側から数えて２組目以降の各耐電圧構造を構成する各半導体層の膜厚の総和の値と、そのコンタクト層の側から数えて１組目の耐電圧構造を構成する添加半導体層の膜厚の値との合計値を５０ｎｍ以上２５０ｎｍ以下にすることがより望ましい。 Further, when the emission wavelength or the light reception wavelength in the active layer is set to 510 nm or more and 550 nm or less, the film thickness of each semiconductor layer constituting each withstand voltage structure of the second and subsequent sets counted from the contact layer side. It is more desirable that the total value of the sum of the values and the thickness value of the added semiconductor layer constituting the first withstand voltage structure counted from the contact layer side be 50 nm or more and 250 nm or less.
この構成によって、発光特性または受光特性を従来以上に維持しつつ、静電耐圧特性を従来よりも改善することができる。なお、この膜厚が厚過ぎると前述の（理由１）または（理由２）による発光性能または受光性能の低下を招き、この膜厚が薄過ぎるとこれらの半導体層自身の抵抗が小さくなり過ぎて静電耐圧特性の向上が難しくなる。 With this configuration, the electrostatic withstand voltage characteristic can be improved as compared with the conventional one while maintaining the light emitting characteristic or the light receiving characteristic more than the conventional one. If the film thickness is too thick, the light emission performance or light reception performance due to the above (reason 1) or (reason 2) is reduced. If the film thickness is too thin, the resistance of these semiconductor layers themselves becomes too small. It becomes difficult to improve the electrostatic withstand voltage characteristics.
また、コンタクト層の側から数えて１組目の耐電圧構造を構成する無添加半導体層の膜厚は、１００ｎｍ以上３００ｎｍ以下にすることがより望ましい。なお、この膜厚が厚過ぎると前述の（理由１）による発光性能または受光性能の低下を招き、この膜厚が薄過ぎるとこの無添加半導体層自身の抵抗が小さくなり過ぎて静電耐圧特性の向上が難しくなる。 The thickness of the additive-free semiconductor layer constituting the first set of withstand voltage structures counted from the contact layer side is more preferably 100 nm or more and 300 nm or less. If this film thickness is too thick, the light emitting performance or light receiving performance due to the above (reason 1) is deteriorated. If this film thickness is too thin, the resistance of the additive-free semiconductor layer itself becomes too small and the electrostatic withstand voltage characteristics are reduced. It becomes difficult to improve.
また、コンタクト層の側から数えて１組目の耐電圧構造を構成する添加半導体層の膜厚は、１０ｎｍ以上１００ｎｍ以下にすることがより望ましい。なお、この膜厚が厚過ぎると前述の（理由２）による発光性能または受光性能の低下を招き、この膜厚が薄過ぎると、キャリアの横方向への分散作用が不足して静電耐圧特性の向上が難しくなる。 Further, it is more desirable that the thickness of the added semiconductor layer constituting the first set of withstand voltage structure counted from the contact layer side be 10 nm or more and 100 nm or less. If this film thickness is too thick, the light emission performance or light receiving performance due to the above-mentioned (reason 2) is deteriorated. If this film thickness is too thin, the dispersing action in the lateral direction of the carrier is insufficient, and the electrostatic withstand voltage characteristics. It becomes difficult to improve.
また、コンタクト層の側から数えて２組目の耐電圧構造を構成する添加半導体層の膜厚は、２０ｎｍ以上４０ｎｍ以下にすることがより望ましい。なお、この膜厚が厚過ぎると前述の（理由２）による発光性能または受光性能の低下を招き、この膜厚が薄過ぎると、キャリアの横方向への分散作用が不足して静電耐圧特性の向上が難しくなる。 Further, it is more preferable that the thickness of the added semiconductor layer constituting the second withstand voltage structure counted from the contact layer side is 20 nm or more and 40 nm or less. If this film thickness is too thick, the light emission performance or light receiving performance due to the above-mentioned (reason 2) is deteriorated. If this film thickness is too thin, the dispersing action in the lateral direction of the carrier is insufficient, and the electrostatic withstand voltage characteristics. It becomes difficult to improve.
なお、本明細書で言う「III族窒化物系化合物半導体」一般には、２元、３元、又は４元の「Ａｌ1-x-yＧａyＩｎxＮ；０≦ｘ≦１，０≦ｙ≦１，０≦１−ｘ−ｙ≦１」成る一般式で表される任意の混晶比の半導体が含まれ、更に、ｐ形或いはｎ形の不純物が添加された半導体もまた、これらの「III族窒化物系化合物半導体」の範疇である。 Note that in the present specification, "Group III nitride compound semiconductor" generally, binary, ternary, or quaternary "Al 1-xy Ga y In x N; 0 ≦ x ≦ 1,0 ≦ y ≦ A semiconductor having an arbitrary mixed crystal ratio represented by a general formula of 1,0 ≦ 1−x−y ≦ 1 is included, and a semiconductor to which a p-type or n-type impurity is added is also included in these “ This is a category of “Group III nitride compound semiconductor”.
また、上記のIII族元素（Ａｌ，Ｇａ，Ｉｎ）の内の少なくとも一部をボロン（Ｂ）やタリウム（Ｔｌ）等で置換したり、或いは、窒素（Ｎ）の少なくとも一部をリン（Ｐ）、砒素（Ａｓ）、アンチモン（Ｓｂ）、ビスマス（Ｂｉ）等で置換したりしても良い。
また、上記のｐ形の不純物（アクセプター）としては、例えば、マグネシウム（Ｍｇ）や、或いはカルシウム（Ｃａ）等の公知のｐ形不純物を添加することができる。
Further, at least a part of the above group III elements (Al, Ga, In) is replaced with boron (B), thallium (Tl), or the like, or at least a part of nitrogen (N) is phosphorus (P ), Arsenic (As), antimony (Sb), bismuth (Bi), or the like.
Moreover, as said p-type impurity (acceptor), well-known p-type impurities, such as magnesium (Mg) or calcium (Ca), can be added, for example.
また、上記のｎ形の不純物（ドナー）としては、例えば、シリコン（Ｓｉ）や、硫黄（Ｓ）、セレン（Ｓｅ）、テルル（Ｔｅ）、或いはゲルマニウム（Ｇｅ）等の公知のｎ形不純物を添加することができる。
また、これらの不純物（アクセプター又はドナー）は、同時に２元素以上を添加しても良いし、同時に両形（ｐ形とｎ形）を添加しても良い。
As the n-type impurity (donor), for example, known n-type impurities such as silicon (Si), sulfur (S), selenium (Se), tellurium (Te), or germanium (Ge) are used. Can be added.
Moreover, two or more elements may be added simultaneously to these impurities (acceptor or donor), or both types (p-type and n-type) may be added simultaneously.
以下、本発明を具体的な実施例に基づいて説明する。
ただし、本発明の実施形態は、以下に示す個々の実施例に限定されるものではない。
Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.
図１は、本実施例１の発光ダイオード１００の断面図である。
この発光ダイオード１００は、サファイア基板１１０の結晶成長面上に、バッファ層１２０、ｎ形コンタクト層１３０、静電耐圧部１４０、ｎ形クラッド層１５０、ＭＱＷ活性層１６０、ｐ形クラッド層１７０、及びｐ形コンタクト層１８０を順次結晶成長させて得られたものである。ただし、上記の静電耐圧部１４０は、下側から無添加半導体層１４１、添加半導体層１４２、無添加半導体層１４３、及び添加半導体層１４４の順に、各半導体層を順次結晶成長によって積層したものである。この静電耐圧部１４０では、無添加半導体層１４１と添加半導体層１４２とで、本発明の１組目の耐電圧構造が構成されており、更に、無添加半導体層１４３と添加半導体層１４４とで本発明の２組目の耐電圧構造が構成されている。
FIG. 1 is a cross-sectional view of the light emitting diode 100 according to the first embodiment.
The light emitting diode 100 includes a buffer layer 120, an n-type contact layer 130, an electrostatic withstand voltage portion 140, an n-type cladding layer 150, an MQW active layer 160, a p-type cladding layer 170 on the crystal growth surface of the sapphire substrate 110, The p-type contact layer 180 is obtained by sequentially growing crystals. However, the electrostatic withstand voltage portion 140 is formed by sequentially laminating each semiconductor layer by crystal growth in the order of the additive-free semiconductor layer 141, additive semiconductor layer 142, additive-free semiconductor layer 143, and additive semiconductor layer 144 from the lower side. It is. In the electrostatic withstand voltage portion 140, the additive-free semiconductor layer 141 and the additive semiconductor layer 142 constitute the first set of withstand voltage structure of the present invention. Further, the additive-free semiconductor layer 143, the additive semiconductor layer 144, Thus, the second withstand voltage structure of the present invention is formed.
以下、上記の発光ダイオード１００の製造方法を、図１を用いて説明する。
上記の発光ダイオード１００の各半導体層は何れも、有機金属化合物気相成長法（ＭＯＶＰＥ）による気相成長により結晶成長されたものである。ここで用いられたガスは、キャリアガス（Ｈ2又はＮ2）と、アンモニアガス（ＮＨ3）と、トリメチルガリウム（Ｇａ(CH3)3：以下「ＴＭＧ」と書く。）と、トリメチルインジウム（Ｉｎ(CH3)3：以下「ＴＭＩ」と書く。）と、トリメチルアルミニウム（Ａｌ(CH3)3：以下「ＴＭＡ」と書く。）と、シラン（ＳｉＨ4）と、シクロペンタジエニルマグネシウム（Ｍｇ（Ｃ5Ｈ5）2：以下「ＣＰ2Ｍｇ」と書く。）などである。
ただし、これらの半導体層を結晶成長させる方法としては、上記の有機金属化合物気相成長法（ＭＯＶＰＥ）の他にも、分子線気相成長法（ＭＢＥ）、ハライド気相成長法（ＨＶＰＥ）等を用いることができる。
Hereinafter, a method for manufacturing the light emitting diode 100 will be described with reference to FIG.
Each of the semiconductor layers of the light emitting diode 100 is a crystal grown by vapor phase growth using a metal organic compound vapor phase growth method (MOVPE). The gases used here are carrier gas (H 2 or N 2 ), ammonia gas (NH 3 ), trimethylgallium (Ga (CH 3 ) 3 : hereinafter referred to as “TMG”), and trimethylindium ( In (CH 3 ) 3 : hereinafter referred to as “TMI”), trimethylaluminum (Al (CH 3 ) 3 : hereinafter referred to as “TMA”), silane (SiH 4 ), and cyclopentadienyl magnesium ( Mg (C 5 H 5 ) 2 : hereinafter referred to as “CP 2 Mg”).
However, as a method for crystal growth of these semiconductor layers, in addition to the above-mentioned organometallic compound vapor phase epitaxy (MOVPE), molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (HVPE), etc. Can be used.
まず最初に、図１に図示する様な断面形状が三角波形状の互いに平行なストライプ溝を有する加工基板（サファイア基板１１０）をＭＯＶＰＥの反応容器内にセットし、水素を流しながら、基板の温度を１０５０℃まで上昇させ、基板のクリーニングを行う。 First, a processed substrate (sapphire substrate 110) having parallel stripe grooves having a triangular cross section as shown in FIG. 1 is set in a MOVPE reaction vessel, and the temperature of the substrate is adjusted while flowing hydrogen. The temperature is raised to 1050 ° C., and the substrate is cleaned.
ここで、サファイアａ面に上記の様な凹凸加工が施されたサファイア基板１１０を用いる目的は、マウントまたはサブマウント等へのマウント方式（給電形態）などにもよるが、少なくとも次の何れか１つである。
（ａ）フェイスダウン型のＬＥＤを製造する場合に、外部量子効率を向上させる。
（ｂ）ＥＬＯ（半導体結晶の横方向成長）に寄与する。
（ｃ）基板と半導体層との間に生じる応力を緩和する。
Here, the purpose of using the sapphire substrate 110 having the sapphire a surface subjected to the above-described concavo-convex processing is at least one of the following, although it depends on the mounting method (power supply form) to the mount or submount, etc. One.
(A) External quantum efficiency is improved when manufacturing a face-down type LED.
(B) Contributes to ELO (semiconductor crystal lateral growth).
(C) Relieve stress generated between the substrate and the semiconductor layer.
（バッファ層１２０）
続いて、温度を５１０℃まで下げ、キャリアガスに水素、原料ガスにアンモニアとＴＭＡ（トリメチルアルミニウム）とを用い、サファイア基板１１０上にＡｌＮよりなるバッファ層１２０を約１５ｎｍの膜厚で成長させる。
(Buffer layer 120)
Subsequently, the temperature is lowered to 510 ° C., hydrogen is used as a carrier gas, ammonia and TMA (trimethylaluminum) are used as a source gas, and a buffer layer 120 made of AlN is grown on the sapphire substrate 110 to a thickness of about 15 nm.
（ｎ形コンタクト層１３０）
バッファ層１２０成長後、ＴＭＧのみ止めて、温度を１１００℃まで上昇させる。１１００℃になったら、同じく原料ガスにＴＭＧ、アンモニアガス、不純物ガスにシランガスを用い、Ｓｉを４．５×１０18〔cm-3〕ドープしたＧａＮよりなるｎ形コンタクト層１３０を４μｍの膜厚で成長させる。
(N-type contact layer 130)
After growth of the buffer layer 120, only TMG is stopped and the temperature is raised to 1100 ° C. When the temperature reaches 1100 ° C., TMG, ammonia gas, and silane gas are used as the source gas, and the n-type contact layer 130 made of GaN doped with Si of 4.5 × 10 18 [cm −3 ] is formed to a thickness of 4 μm. Grow in.
（静電耐圧部１４０）
（１）無添加半導体層１４１
次に、シランガスのみを止め、１１００℃で、ＴＭＧ、アンモニアガスを用いて、アンドープＧａＮからなる無添加半導体層１４１を２００ｎｍの膜厚で成長させる。
（２）添加半導体層１４２
続いて、ＴＭＧを止めて、温度を８５０℃まで降下させる。８５０℃になったら、ＴＭＧ及びシランガスを追加して、Ｓｉを４．５×１０18〔cm-3〕ドープしたＧａＮからなる添加半導体層１４２を５０ｎｍの膜厚で成長させる。
なお、この無添加半導体層１４１と添加半導体層１４２の２層の半導体層によって、ｎ形コンタクト層１３０の側から数えて１組目の本発明の耐電圧構造が構成される。
(Electrostatic pressure resistant part 140)
(1) Additive-free semiconductor layer 141
Next, only the silane gas is stopped, and an undoped semiconductor layer 141 made of undoped GaN is grown to a thickness of 200 nm using TMG and ammonia gas at 1100 ° C.
(2) Additive semiconductor layer 142
Subsequently, the TMG is turned off and the temperature is lowered to 850 ° C. When the temperature reaches 850 ° C., TMG and silane gas are added, and an additive semiconductor layer 142 made of GaN doped with Si of 4.5 × 10 18 [cm −3 ] is grown to a thickness of 50 nm.
The two semiconductor layers of the additive-free semiconductor layer 141 and the additive semiconductor layer 142 constitute the first set of withstand voltage structure of the present invention counted from the n-type contact layer 130 side.
（３）無添加半導体層１４３
その後、シランガスのみを止め、同温（８５０℃）にてアンドープＧａＮからなる無添加半導体層１４３を２００ｎｍの膜厚で成長させる。
（４）添加半導体層１４４
最後に、シランガスを追加し、同温（８５０℃）にてＳｉを４．５×１０18〔cm-3〕ドープしたＧａＮからなる添加半導体層１４４を３０ｎｍの膜厚で成長させる。
なお、この無添加半導体層１４３と添加半導体層１４４の２層の半導体層によって、ｎ形コンタクト層１３０の側から数えて２組目の本発明の耐電圧構造が構成される。
(3) Additive-free semiconductor layer 143
Thereafter, only the silane gas is stopped and an undoped semiconductor layer 143 made of undoped GaN is grown to a thickness of 200 nm at the same temperature (850 ° C.).
(4) Added semiconductor layer 144
Finally, silane gas is added, and an additive semiconductor layer 144 made of GaN doped with Si of 4.5 × 10 18 [cm −3 ] is grown at the same temperature (850 ° C.) to a thickness of 30 nm.
The two semiconductor layers of the additive-free semiconductor layer 143 and the additive semiconductor layer 144 constitute a second set of withstand voltage structures of the present invention counted from the n-type contact layer 130 side.
（ｎ形クラッド層１５０）
次に、シランガスとＴＭＧを止めて、温度を１０５０℃まで上昇させる。１０５０℃になったら、ＴＭＧを追加し、アンドープＧａＮよりなる第１の窒化物半導体層を４ｎｍ成長させ、次に温度を８００℃にして、ＴＭＧ、ＴＭＩ、アンモニアを用いて、アンドープＩｎ0.13Ｇａ0.87Ｎよりなる第２の窒化物半導体層を２ｎｍ成長させる。そしてこれらの操作を繰り返し、第１＋第２の順で交互に１０層づつ積層させ、最後にＧａＮよりなる第１の窒化物半導体層を４ｎｍ成長さた超格子構造の多層膜よりなるｎ形クラッド層１５０を６４ｎｍの膜厚で成長させる。
(N-type cladding layer 150)
Next, silane gas and TMG are stopped and the temperature is raised to 1050 ° C. When the temperature reaches 1050 ° C., TMG is added, and a first nitride semiconductor layer made of undoped GaN is grown to 4 nm. Next, the temperature is set to 800 ° C., and TMG, TMI, and ammonia are used to undoped In 0.13 Ga 0.87. A second nitride semiconductor layer made of N is grown by 2 nm. Then, these operations are repeated, and 10 layers are alternately stacked in the order of 1 + 2, and finally, an n-type cladding made of a multilayer film having a superlattice structure in which a first nitride semiconductor layer made of GaN is grown to 4 nm. Layer 150 is grown to a thickness of 64 nm.
（ＭＱＷ活性層１６０）
次に、温度を８００℃にして、膜厚２０ｎｍの無添加のＧａＮから成る障壁層と、膜厚３ｎｍの無添加のＩｎ0.2Ｇａ0.8Ｎから成る井戸層とを交互に積層して構成されるＭＱＷ活性層１６０を成長させる。
(MQW active layer 160)
Next, the temperature is set to 800 ° C., and a barrier layer made of additive-free GaN with a thickness of 20 nm and a well layer made of additive-free In 0.2 Ga 0.8 N with a thickness of 3 nm are alternately stacked. An MQW active layer 160 is grown.
（ｐ形クラッド層１７０）
次に、温度１０５０℃でＴＭＧ、ＴＭＡ、アンモニア、ＣＰ2Ｍｇ（シクロペンタジエニルマグネシウム）を用い、Ｍｇを１×１０20〔cm-3〕ドープしたｐ形Ａｌ0.2Ｇａ0.8Ｎよりなる第３の窒化物半導体層を４ｎｍの膜厚で成長させ、続いて温度を８００℃にして、ＴＭＧ、ＴＭＩ、アンモニア、ＣＰ2Ｍｇを用いて、Ｍｇを１×１０20〔cm-3〕ドープしたＩｎ0.03Ｇａ0.97Ｎよりなる第４の窒化物半導体層を２．５ｎｍの膜厚で成長させる。そしてこれらの操作を繰り返し、第３＋第４の順で交互に５層ずつ積層し、最後に第３の窒化物半導体層を４ｎｍの膜厚で成長させた超格子構造の多層膜よりなるｐ形クラッド層１７０を３６．５ｎｍの膜厚で成長させる。
(P-type cladding layer 170)
Next, a third layer of p-type Al 0.2 Ga 0.8 N doped with 1 × 10 20 [cm −3 ] Mg using TMG, TMA, ammonia, CP 2 Mg (cyclopentadienyl magnesium) at a temperature of 1050 ° C. Indium doped with 1 × 10 20 [cm −3 ] of Mg using TMG, TMI, ammonia, CP 2 Mg at a temperature of 800 ° C. A fourth nitride semiconductor layer made of 0.03 Ga 0.97 N is grown to a thickness of 2.5 nm. Then, these operations are repeated, and 5 layers are alternately stacked in the order of 3 + 4, and finally a p-type formed of a multilayer film having a superlattice structure in which a third nitride semiconductor layer is grown to a thickness of 4 nm. The cladding layer 170 is grown to a thickness of 36.5 nm.
（ｐ形コンタクト層１８０）
続いて、１０５０℃でＴＭＧ、アンモニア、ＣＰ2Ｍｇを用いて、Ｍｇを１×１０20〔cm-3〕ドープしたｐ形ＧａＮよりなるｐ形コンタクト層１８０を７０ｎｍの膜厚で成長させる。
(P-type contact layer 180)
Subsequently, a p-type contact layer 180 made of p-type GaN doped with 1 × 10 20 [cm −3 ] of Mg is grown to a thickness of 70 nm using TMG, ammonia, and CP 2 Mg at 1050 ° C.
その後、最上層のｐ形コンタクト層１８０の表面に所定の形状のマスクを形成し、ＲＩＥ（反応性イオンエッチング）装置でｐ形コンタクト層１８０側からエッチングを行い、図１に示すようにｎ形コンタクト層１３０の一部を露出させる。 Thereafter, a mask having a predetermined shape is formed on the surface of the uppermost p-type contact layer 180, and etching is performed from the p-type contact layer 180 side by an RIE (reactive ion etching) apparatus. As shown in FIG. A part of the contact layer 130 is exposed.
次に、ｐ形コンタクト層１８０の上には透光性のｐ電極１９１ａを蒸着し、また、ｎ形コンタクト層１３０上にはｎ電極１９２を蒸着する。このｐ電極１９１ａは、ｐ形コンタクト層１８０に直接接合する膜厚約1.5nmのコバルト(Co)より成る第１層と、このコバルト膜に接合する膜厚約６nmの金（Au）より成る第２層とを順次積層することにより構成する。
更に、透光性のｐ電極１９１ａの上に蒸着するｐパッド電極１９１ｂは、膜厚約18nmのバナジウム(V)より成る第１層と、膜厚約1.5μmの金(Au)より成る第２層と、膜厚約10nmのアルミニウム(Al)より成る第３層とを順次積層することにより構成する。
一方、多層構造のｎ電極１９２は、ｎ形コンタクト層１３０の一部露出された部分の上から、膜厚約18nmのバナジウム(V)より成る第１層と、膜厚約100nmのアルミニウム(Al)より成る第２層とを順次積層することにより構成する。
Next, a light-transmitting p-electrode 191 a is deposited on the p-type contact layer 180, and an n-electrode 192 is deposited on the n-type contact layer 130. The p-electrode 191a includes a first layer made of cobalt (Co) having a thickness of about 1.5 nm directly bonded to the p-type contact layer 180 and a first layer made of gold (Au) having a thickness of about 6 nm bonded to the cobalt film. It is configured by sequentially laminating two layers.
Further, the p-pad electrode 191b deposited on the translucent p-electrode 191a is a first layer made of vanadium (V) having a thickness of about 18 nm and a first layer made of gold (Au) having a thickness of about 1.5 μm . Two layers and a third layer made of aluminum (Al) having a thickness of about 10 nm are sequentially stacked.
On the other hand, the n-electrode 192 having a multilayer structure includes a first layer made of vanadium (V) having a thickness of about 18 nm and an aluminum (Al ) And the second layer are sequentially laminated.
なお、透光性のｐ電極１９１ａの露出面や、エッチングなどによって露出した各半導体層の側壁面などには、SiO2膜より成る保護膜を形成しても良い。また、サファイア基板１１０の底面に当たる外側の最下部には、例えば膜厚約５００ｎｍのアルミニウム（Al）より成る反射金属層を蒸着しても良い。この様な反射金属層を形成する場合には、その材料として、Ｒｈ、Ｔｉ、Ｗなどの金属の他にも、例えばＴｉＮ、ＨｆＮなどの窒化物を用いても良い。 Note that a protective film made of a SiO 2 film may be formed on the exposed surface of the translucent p-electrode 191a, the side wall surface of each semiconductor layer exposed by etching, or the like. Further, a reflective metal layer made of, for example, aluminum (Al) having a film thickness of about 500 nm may be deposited on the outermost lowermost portion corresponding to the bottom surface of the sapphire substrate 110. When such a reflective metal layer is formed, nitrides such as TiN and HfN may be used as the material in addition to metals such as Rh, Ti and W.
以上の様にして作成された発光ダイオード１００の発光ピーク波長は約４７０ｎｍ（青色発光）で、順方向電流２０ｍＡにおける駆動電圧Ｖｆは約３．５Ｖであった。この発光ダイオード１００に対して、１０００Ｖ〜１８００Ｖの逆向きの静電圧を印加する耐久テスト（：人体モデル（ＨＢＭ）のＥＳＤ試験）を実施した。その時の各静電圧に対する発光ダイオード１００の生存率は次の通りであり、何れの場合においても従来よりも大幅に高い生存率が得られた。
（ａ）静電圧が−１０００Ｖの時の生存率：約８３％
（ｂ）静電圧が−１２００Ｖの時の生存率：約８３％
（ｃ）静電圧が−１８００Ｖの時の生存率：約８２％
The light emitting diode 100 produced as described above has a light emission peak wavelength of about 470 nm (blue light emission), and a drive voltage Vf at a forward current of 20 mA is about 3.5V. A durability test (: ESD test of human body model (HBM)) in which a reverse electrostatic voltage of 1000 V to 1800 V was applied to the light emitting diode 100 was performed. The survival rate of the light emitting diode 100 with respect to each static voltage at that time is as follows, and in any case, a significantly higher survival rate was obtained than before.
(A) Survival rate when static voltage is -1000 V: about 83%
(B) Survival rate when static voltage is -1200V: about 83%
(C) Survival rate when static voltage is -1800V: about 82%
また、上記の添加半導体層１４２の膜厚は、１０ｎｍ〜１００ｎｍの範囲内で変動させても、静電耐圧特性（生存率）や出力特性（駆動電圧Ｖｆ）等には、あまり大きな変化が現われないことが分かった。 In addition, even if the film thickness of the additive semiconductor layer 142 is varied within the range of 10 nm to 100 nm, the electrostatic breakdown voltage characteristics (survival rate), output characteristics (drive voltage Vf), etc., change significantly. I found that there was no.
一方、上記のＥＳＤ試験と対比するために、従来構造のＬＥＤを試作してその生存率を求めた。ここで用いた対比用のＬＥＤとしては、次の相違点以外は上記の発光ダイオード１００と同じ構造のものを用いた。
（相違点）無添加半導体層１４１、添加半導体層１４２、及び無添加半導体層１４３の３層を積層する代わりに、結晶成長温度８５０℃で結晶成長された膜厚３００ｎｍのアンドープのＧａＮから成る半導体層を、添加半導体層１４４とｎ形コンタクト層１３０との間に積層した。なお、この場合も、図３に例示される従来構造と同様に、静電耐圧特性に寄与する部分における、不純物が添加された半導体層の数は、上記の添加半導体層１４４に対応するＳｉドープの半導体層の１層のみとなる。
On the other hand, in order to compare with the above ESD test, an LED having a conventional structure was prototyped and its survival rate was determined. The comparison LED used here has the same structure as that of the light emitting diode 100 except for the following differences.
(Difference) Instead of stacking three layers of the additive-free semiconductor layer 141, the additive semiconductor layer 142, and the additive-free semiconductor layer 143, a semiconductor composed of 300 nm-thick undoped GaN grown at a crystal growth temperature of 850 ° C. The layer was laminated between the additive semiconductor layer 144 and the n-type contact layer 130. Also in this case, as in the conventional structure illustrated in FIG. 3, the number of semiconductor layers to which impurities are added in the portion that contributes to the electrostatic withstand voltage characteristics is the Si doping corresponding to the added semiconductor layer 144. There is only one semiconductor layer.
この対比用のＬＥＤに対して上記と同様のＥＳＤ試験を実施した結果、この対比用のＬＥＤの生存率は次の通りであった。
（ａ）静電圧が−１０００Ｖの時の生存率：約４５％
（ｂ）静電圧が−１２００Ｖの時の生存率：約４３％
（ｃ）静電圧が−１８００Ｖの時の生存率：約４２％
As a result of conducting the ESD test similar to the above on the LED for comparison, the survival rate of the LED for comparison was as follows.
(A) Survival rate when static voltage is -1000 V: about 45%
(B) Survival rate when static voltage is -1200V: about 43%
(C) Survival rate when static voltage is -1800V: about 42%
また、この対比用のＬＥＤの出力特性は、上記の発光ダイオード１００と同等であった。これらの結果から、本発明の手段により、半導体素子において出力性能を良好に維持したまま静電耐圧特性を大幅に改善できることが分かった。 Further, the output characteristics of the comparative LED were equivalent to those of the light emitting diode 100 described above. From these results, it was found that the electrostatic withstand voltage characteristics can be greatly improved by the means of the present invention while maintaining excellent output performance in the semiconductor element.
図２は、本実施例２の発光ダイオード２００の断面図である。この発光ダイオード２００の発光ピーク波長は約５３０ｎｍ（緑色発光）であり、以下の相違点以外の点については、上記の実施例１の発光ダイオード１００と同じ構造とした。
（相違点１）
サファイア基板２１０に対して実施例１で示した凹凸加工は実施せずに、結晶成長面にはサファイアａ面を用いた。
FIG. 2 is a cross-sectional view of the light emitting diode 200 according to the second embodiment. The light emitting diode 200 has an emission peak wavelength of about 530 nm (green light emission), and has the same structure as the light emitting diode 100 of Example 1 except for the following differences.
(Difference 1)
The sapphire a surface was used for the crystal growth surface without performing the uneven processing shown in Example 1 on the sapphire substrate 210.
（相違点２）
発光ダイオード１００の静電耐圧部１４０に対応する発光ダイオード２００の静電耐圧部２４０において、ｎ形コンタクト層１３０の側から数えて２組目の本発明の耐電圧構造の下層側を構成するアンドープの半導体層（無添加半導体層２４３）を次の結晶成長条件で積層した。
＜結晶成長条件＞結晶成長温度８５０℃にてアンドープＧａＮからなる半導体層（無添加半導体層２４３）を３０ｎｍの膜厚で成長させた。
(Difference 2)
In the electrostatic withstand voltage portion 240 of the light emitting diode 200 corresponding to the electrostatic withstand voltage portion 140 of the light emitting diode 100, the undoped constituting the lower layer side of the second withstand voltage structure of the present invention, counted from the n-type contact layer 130 side. The semiconductor layer (additive semiconductor layer 243) was stacked under the following crystal growth conditions.
<Crystal growth conditions> A semiconductor layer (undoped semiconductor layer 243) made of undoped GaN was grown to a thickness of 30 nm at a crystal growth temperature of 850 ° C.
（相違点３）
ＭＱＷ活性層２６０を構成する各井戸層の組成を変更した。即ち、緑色発光とするために、各井戸層をそれぞれアンドープのＩｎ0.4Ｇａ0.6Ｎから成る膜厚約３ｎｍの半導体層から形成した。
そして、上記以外の点については、実施例１の発光ダイオード１００と同等の製造条件で、本実施例２の発光ダイオード２００を製造した。
(Difference 3)
The composition of each well layer constituting the MQW active layer 260 was changed. That is, in order to emit green light, each well layer was formed from a semiconductor layer having a thickness of about 3 nm made of undoped In 0.4 Ga 0.6 N.
And about the point other than the above, the light emitting diode 200 of this Example 2 was manufactured on the manufacturing conditions equivalent to the light emitting diode 100 of Example 1. FIG.
この様にして製造された発光ダイオード２００においては、順方向電流２０ｍＡにおける駆動電圧Ｖｆは約３．５Ｖであった。この発光ダイオード２００に対して、１０００Ｖの逆向きの静電圧を印加する耐久テスト（：人体モデル（ＨＢＭ）のＥＳＤ試験）を実施した。その時の静電圧に対する発光ダイオード２００の生存率は次の通りであり、従来よりも大幅に高い生存率が得られた。
（ａ）静電圧が−１０００Ｖの時の生存率：約７７％
In the light emitting diode 200 manufactured in this way, the drive voltage Vf at a forward current of 20 mA was about 3.5V. A durability test (: ESD test of human body model (HBM)) in which a reverse electrostatic voltage of 1000 V was applied to the light emitting diode 200 was performed. The survival rate of the light-emitting diode 200 with respect to the static voltage at that time is as follows, and a significantly higher survival rate than the conventional one was obtained.
(A) Survival rate when static voltage is -1000 V: about 77%
一方、上記のＥＳＤ試験と対比するために、従来構造のＬＥＤを試作してその生存率を求めた。ここで用いた対比用のＬＥＤとしては、次の相違点以外は上記の発光ダイオード２００と同じ構造のものを用いた。
（相違点）無添加半導体層１４１、添加半導体層１４２、及び無添加半導体層２４３の３層を積層する代わりに、結晶成長温度８５０℃で結晶成長された膜厚３００ｎｍのアンドープのＧａＮから成る半導体層を、添加半導体層１４４とｎ形コンタクト層１３０との間に積層した。
On the other hand, in order to compare with the above ESD test, an LED having a conventional structure was prototyped and its survival rate was determined. The comparison LED used here has the same structure as that of the light emitting diode 200 except for the following differences.
(Difference) Instead of stacking three layers of the additive-free semiconductor layer 141, the additive semiconductor layer 142, and the additive-free semiconductor layer 243, a semiconductor made of undoped GaN having a film thickness of 300 nm grown at a crystal growth temperature of 850 ° C. The layer was laminated between the additive semiconductor layer 144 and the n-type contact layer 130.
この対比用のＬＥＤに対して上記と同様のＥＳＤ試験を実施した結果、この対比用のＬＥＤの生存率は次の通りであった。
（ａ）静電圧が−１０００Ｖの時の生存率：約４．１％
As a result of conducting the ESD test similar to the above on the LED for comparison, the survival rate of the LED for comparison was as follows.
(A) Survival rate when static voltage is −1000 V: about 4.1%
また、この対比用のＬＥＤの出力特性は、上記の発光ダイオード２００と同等であった。これらの結果から、本発明の手段により、半導体素子において出力性能を良好に維持したまま静電耐圧特性を大幅に改善できることが分かった。 Further, the output characteristics of the comparative LED were equivalent to those of the light emitting diode 200 described above. From these results, it was found that the electrostatic withstand voltage characteristics can be greatly improved by the means of the present invention while maintaining excellent output performance in the semiconductor element.
本発明を適用することにより本発明の作用・効果が得られる半導体素子としては、半導体レーザや発光ダイオード等の半導体発光素子の他にも、半導体受光素子などがある。
また、III族窒化物系化合物半導体から成る半導体層を基板上に複数層積層して形成されるその他の半導体デバイス（半導体素子）においても同様に、本発明の手段を適用することによって、本発明の作用・効果を得ることができる。
As a semiconductor element that can obtain the functions and effects of the present invention by applying the present invention, there is a semiconductor light receiving element in addition to a semiconductor light emitting element such as a semiconductor laser or a light emitting diode.
Similarly, the present invention can be applied to other semiconductor devices (semiconductor elements) formed by laminating a plurality of semiconductor layers made of a group III nitride compound semiconductor on a substrate. The operation and effect of can be obtained.
１００ ： 発光ダイオード
１１０ ： サファイア基板
１２０ ： バッファ層
１３０ ： ｎ形コンタクト層
１４０ ： 静電耐圧部
１４１ ： 無添加半導体層（無添加ＧａＮ）
１４２ ： 添加半導体層（ＳｉドープＧａＮ）
１４３ ： 無添加半導体層（無添加ＧａＮ）
１４４ ： 添加半導体層（ＳｉドープＧａＮ）
１５０ ： ｎ形クラッド層（超格子構造）
１６０ ： ＭＱＷ活性層
１７０ ： ｐ形クラッド層（超格子構造）
１８０ ： ｐ形コンタクト層
１９１ａ： ｐ電極
１９１ｂ： ｐパッド電極
１９２ ： ｎ電極
100: light emitting diode 110: sapphire substrate 120: buffer layer 130: n-type contact layer 140: electrostatic withstand voltage portion 141: additive-free semiconductor layer (additive-free GaN)
142: Additive semiconductor layer (Si-doped GaN)
143: additive-free semiconductor layer (additive-free GaN)
144: Additive semiconductor layer (Si-doped GaN)
150: n-type cladding layer (superlattice structure)
160: MQW active layer 170: p-type cladding layer (superlattice structure)
180: p-type contact layer 191a: p electrode 191b: p pad electrode 192: n electrode
２００ ： 発光ダイオード
２１０ ： サファイア基板
２２０ ： バッファ層
２４０ ： 静電耐圧部
２４３ ： 無添加半導体層（無添加ＧａＮ）
２６０ ： ＭＱＷ活性層
200: light emitting diode 210: sapphire substrate 220: buffer layer 240: electrostatic withstand voltage portion 243: additive-free semiconductor layer (additive-free GaN)
260: MQW active layer
Claims (4)
前記ｎ形のコンタクト層の側から数えて１組目の前記耐電圧構造を構成する前記添加半導体層の結晶成長温度、及び、前記ｎ形のコンタクト層の側から数えて２組目以降の前記耐電圧構造を構成する前記半導体層の結晶成長温度を何れも８００℃以上９００℃以下にし、
前記ｎ形のコンタクト層の側から数えて１組目の前記耐電圧構造を構成する前記無添加半導体層の結晶成長温度を１０００℃以上１２００℃以下にする
ことを特徴とする半導体素子の製造方法。 The semiconductor layer composed of a Group III nitride compound semiconductor is a semiconductor device formed by a plurality of layers stacked on the substrate, from the side of the n-type contact layer between the active layer and the n-type contact layer , n-type impurity is not added semiconductor layer of additive-free, has two sets of withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added, the active layer The light emission peak wavelength or the light reception peak wavelength is 450 nm or more and 480 nm or less, and the film thickness of the additive-free semiconductor layer constituting the second withstand voltage structure counted from the n-type contact layer side is 100 nm or more and 300 nm or less. In the method for manufacturing a semiconductor element,
The crystal growth temperature of the additional semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the second and subsequent sets counted from the n-type contact layer side. The crystal growth temperature of the semiconductor layer constituting the withstand voltage structure is 800 ° C. or more and 900 ° C. or less,
The crystal growth temperature of the additive-free semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side is set to 1000 ° C. or more and 1200 ° C. or less.
A method for manufacturing a semiconductor device, comprising:
前記ｎ形のコンタクト層の側から数えて１組目の前記耐電圧構造を構成する前記添加半導体層の結晶成長温度、及び、前記ｎ形のコンタクト層の側から数えて２組目以降の前記耐電圧構造を構成する前記半導体層の結晶成長温度を何れも８００℃以上９００℃以下にし、
前記ｎ形のコンタクト層の側から数えて１組目の前記耐電圧構造を構成する前記無添加半導体層の結晶成長温度を１０００℃以上１２００℃以下にする
ことを特徴とする半導体素子の製造方法。 The semiconductor layer composed of a Group III nitride compound semiconductor is a semiconductor device formed by a plurality of layers stacked on the substrate, from the side of the n-type contact layer between the active layer and the n-type contact layer , n-type impurity is not added semiconductor layer of additive-free, has two sets of withstand voltage structure constituted by two layers 1 set in the order of addition semiconductor layer n-type impurity is added, the active layer The light emission peak wavelength or the light reception peak wavelength is 510 nm or more and 550 nm or less, and the film thickness of the additive-free semiconductor layer constituting the second set of withstand voltage structure counted from the n-type contact layer side is 10 nm or more and 50 nm. In the following method for manufacturing a semiconductor element:
The crystal growth temperature of the additional semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side, and the second and subsequent sets counted from the n-type contact layer side. The crystal growth temperature of the semiconductor layer constituting the withstand voltage structure is 800 ° C. or more and 900 ° C. or less,
The crystal growth temperature of the additive-free semiconductor layer constituting the first withstand voltage structure counted from the n-type contact layer side is set to 1000 ° C. or more and 1200 ° C. or less.
A method for manufacturing a semiconductor device, comprising:
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| KR101459754B1 (en) | 2007-09-06 | 2014-11-13 | 엘지이노텍 주식회사 | Semiconductor light emitting device and fabrication method thereof |
| WO2009039402A1 (en) | 2007-09-19 | 2009-03-26 | The Regents Of The University Of California | (al,in,ga,b)n device structures on a patterned substrate |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000244072A (en) * | 1998-10-06 | 2000-09-08 | Nichia Chem Ind Ltd | Nitride semiconductor element |
| JP2001148507A (en) * | 1999-03-29 | 2001-05-29 | Nichia Chem Ind Ltd | Nitride semiconductor device |
| JP2001237456A (en) * | 2000-02-21 | 2001-08-31 | Nichia Chem Ind Ltd | Light-emitting element |
| JP2004047867A (en) * | 2002-07-15 | 2004-02-12 | Sony Corp | Manufacturing method of nitride semiconductor light emitting element |
| JP2004356442A (en) * | 2003-05-29 | 2004-12-16 | Toyoda Gosei Co Ltd | Group iii nitride system compound semiconductor light emitting element |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000244072A (en) * | 1998-10-06 | 2000-09-08 | Nichia Chem Ind Ltd | Nitride semiconductor element |
| JP2001148507A (en) * | 1999-03-29 | 2001-05-29 | Nichia Chem Ind Ltd | Nitride semiconductor device |
| JP2001237456A (en) * | 2000-02-21 | 2001-08-31 | Nichia Chem Ind Ltd | Light-emitting element |
| JP2004047867A (en) * | 2002-07-15 | 2004-02-12 | Sony Corp | Manufacturing method of nitride semiconductor light emitting element |
| JP2004356442A (en) * | 2003-05-29 | 2004-12-16 | Toyoda Gosei Co Ltd | Group iii nitride system compound semiconductor light emitting element |
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