JP4549726B2 - 半導体ウエハの接着前表面処理 - Google Patents

半導体ウエハの接着前表面処理 Download PDF

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Publication number
JP4549726B2
JP4549726B2 JP2004136254A JP2004136254A JP4549726B2 JP 4549726 B2 JP4549726 B2 JP 4549726B2 JP 2004136254 A JP2004136254 A JP 2004136254A JP 2004136254 A JP2004136254 A JP 2004136254A JP 4549726 B2 JP4549726 B2 JP 4549726B2
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JP
Japan
Prior art keywords
wafer
bonding
process according
brushing
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2004136254A
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English (en)
Japanese (ja)
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JP2005142524A (ja
JP2005142524A5 (https=
Inventor
クリストフ、マルビル
コリンヌ、モナン、テュソ
セバスティアン、ケルディル
オリビエ、ライサック
ベンジャミン、スカルフォグリエール
ユベール、モリソー
クリストフ、モラル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Soitec SA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Soitec SA
Publication of JP2005142524A publication Critical patent/JP2005142524A/ja
Publication of JP2005142524A5 publication Critical patent/JP2005142524A5/ja
Application granted granted Critical
Publication of JP4549726B2 publication Critical patent/JP4549726B2/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15—Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/60—Cleaning only by mechanical processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Cleaning Or Drying Semiconductors (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
JP2004136254A 2003-04-29 2004-04-30 半導体ウエハの接着前表面処理 Expired - Lifetime JP4549726B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0305236A FR2854493B1 (fr) 2003-04-29 2003-04-29 Traitement par brossage d'une plaquette semiconductrice avant collage

Publications (3)

Publication Number Publication Date
JP2005142524A JP2005142524A (ja) 2005-06-02
JP2005142524A5 JP2005142524A5 (https=) 2006-05-18
JP4549726B2 true JP4549726B2 (ja) 2010-09-22

Family

ID=32982322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004136254A Expired - Lifetime JP4549726B2 (ja) 2003-04-29 2004-04-30 半導体ウエハの接着前表面処理

Country Status (3)

Country Link
EP (1) EP1473765B1 (https=)
JP (1) JP4549726B2 (https=)
FR (1) FR2854493B1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7919391B2 (en) * 2004-12-24 2011-04-05 S.O.I.Tec Silicon On Insulator Technologies Methods for preparing a bonding surface of a semiconductor wafer
JP5064692B2 (ja) * 2006-02-09 2012-10-31 信越化学工業株式会社 Ｓｏｉ基板の製造方法
JP5064693B2 (ja) * 2006-02-13 2012-10-31 信越化学工業株式会社 Ｓｏｉ基板の製造方法
JP2007220782A (ja) * 2006-02-15 2007-08-30 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
JP5064695B2 (ja) * 2006-02-16 2012-10-31 信越化学工業株式会社 Ｓｏｉ基板の製造方法
JP5042506B2 (ja) 2006-02-16 2012-10-03 信越化学工業株式会社 半導体基板の製造方法
WO2008029607A1 (en) * 2006-09-07 2008-03-13 Nec Electronics Corporation Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device
JP2009123831A (ja) 2007-11-13 2009-06-04 Tokyo Electron Ltd Ｂｓｐ除去方法、ｂｓｐ除去装置、基板処理装置、及び記憶媒体
FR2935067B1 (fr) * 2008-08-14 2011-02-25 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice plan de masse enterre
KR102567863B1 (ko) * 2021-01-14 2023-08-18 (주)인터체크 스크러버를 이용한 레티클 세정장치

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62186938A (ja) * 1986-02-13 1987-08-15 Okazaki Seisakusho:Kk 固体の接合方法
JPS6437841A (en) * 1987-08-04 1989-02-08 Nec Corp Semiconductor wafer cleaner
JP2671419B2 (ja) * 1988-08-09 1997-10-29 株式会社日本自動車部品総合研究所 半導体装置の製造方法
JPH02183510A (ja) * 1989-01-10 1990-07-18 Sony Corp 半導体用基板の製法
US5131968A (en) * 1990-07-31 1992-07-21 Motorola, Inc. Gradient chuck method for wafer bonding employing a convex pressure
JPH0719739B2 (ja) * 1990-09-10 1995-03-06 信越半導体株式会社 接合ウェーハの製造方法
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2701709B2 (ja) * 1993-02-16 1998-01-21 株式会社デンソー ２つの材料の直接接合方法及び材料直接接合装置
JP3162914B2 (ja) * 1994-05-26 2001-05-08 三菱マテリアル株式会社 半導体素子用貼り合せシリコンウェーハの製造方法
JP3171366B2 (ja) * 1994-09-05 2001-05-28 三菱マテリアル株式会社 シリコン半導体ウェーハ及びその製造方法
JP3287524B2 (ja) * 1995-03-13 2002-06-04 三菱マテリアル株式会社 Ｓｏｉ基板の製造方法
US6159824A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
US6388290B1 (en) * 1998-06-10 2002-05-14 Agere Systems Guardian Corp. Single crystal silicon on polycrystalline silicon integrated circuits
US6566233B2 (en) * 1999-12-24 2003-05-20 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
JP4628580B2 (ja) * 2001-04-18 2011-02-09 信越半導体株式会社 貼り合せ基板の製造方法

Also Published As

Publication number Publication date
EP1473765A3 (fr) 2005-12-28
FR2854493A1 (fr) 2004-11-05
JP2005142524A (ja) 2005-06-02
EP1473765B1 (fr) 2013-06-05
FR2854493B1 (fr) 2005-08-19
EP1473765A2 (fr) 2004-11-03

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