JP4547871B2 - Solid-state image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to a charge transfer type solid-state imaging device typified by a CCD (Charge Coupled Device) solid-state imaging device in which a plurality of charge detection units for converting signal charges into electrical signals are arranged adjacent to each other.
[0002]
[Prior art]
Conventionally, as a charge transfer type solid-state image pickup device, for example, a CCD solid-state image pickup device, it is suitable for high pixel count (multiple pixels) and is transferred by a vertical CCD to enable low power consumption and high speed drive. There is a so-called horizontal scan type solid-state image pickup device in which a plurality of charge detection units for converting signal charges into voltages are provided for each vertical CCD, and signal voltages output from each of the plurality of charge detection units are read while sequentially scanning (for example, Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-135656
FIG. 7 is a circuit diagram showing a configuration of a conventional general charge detection unit. In FIG. 7, signal charges transferred by a charge transfer unit (not shown) are injected into the floating diffusion region FD in units of pixels. The signal charge injected into the floating diffusion region FD is converted into a signal voltage by the output circuit 100 including the output transistor 101 of the source follower whose gate is connected to the region FD, and is output from the output terminal 102. The output transistor 101 has a drain connected to a power supply terminal 103 to which a power supply voltage VDD is applied, and a source grounded via a resistor 104.
[0005]
When signal charge is read from the floating diffusion region FD, the potential of the region FD is reset to the reset drain voltage V _RD by the reset transistor 105. The reset drain voltage V _RD is set so that the voltage value is substantially equal to the power supply voltage VDD. The reset transistor 105 has a drain connected to a reset drain (RD) terminal 106 to which a reset drain voltage V _RD is applied, and a source connected to a floating diffusion region FD, and a reset gate pulse φRG is reset at a predetermined cycle (RG). ) To reset the potential of the floating diffusion region FD to the reset drain voltage V _RD .
[0006]
FIG. 8 is a cross-sectional view showing the structure of the floating diffusion region FD and the reset transistor 105. In FIG. 8, a floating diffusion region FD is an n + -type diffusion region 111 formed in the surface layer portion of the silicon substrate 110, for example. Signal charges are injected into the n + -type diffusion region 111 via the output gate portion 121 of the charge transfer portion 120. The reset transistor 105 uses the n + -type diffusion region 111 as a source region, the source region 111, an n + -type drain region 112 formed in the surface layer portion of the silicon substrate 110, and a channel region between both the regions 111 and 112. The gate electrode 113 is formed on the upper substrate surface via the gate insulating film 114.
[0007]
FIG. 9 shows an example of a planar arrangement pattern when a plurality of, for example, two, charge detection units having the above-described configuration are arranged adjacent to each other. As can be seen from the figure, one charge detector includes a power supply (VDD) terminal 103, a floating diffusion region FD, an output terminal (VOUT) 102, a gate electrode (RG) and a reset drain (RD) terminal of the reset transistor 105. The five terminal electrodes 106 are arranged side by side in order. In the case of this example, two charge detectors are arranged adjacent to each other.
[0008]
[Problems to be solved by the invention]
In the above-described horizontal scan type solid-state imaging device, in order to arrange the charge detection unit having the above configuration for each vertical CCD, the charge detection unit has a configuration in which five terminal electrodes are arranged side by side. It is necessary to secure a certain pitch between the CCDs. Therefore, in the sensor unit (pixel unit) in which the pixels are two-dimensionally arranged, there is a limit in reducing the size particularly in the horizontal direction (left-right direction). Further, since the pitch between the vertical CCDs is determined by the pitch between the pixels in the horizontal direction, securing a certain pitch between the vertical CCDs means that the pitch between the pixels cannot be reduced. Is very disadvantageous.
[0009]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device that enables miniaturization of the charge detection unit when arranging a plurality of charge detection units adjacent to each other. It is in.
[0010]
[Means for Solving the Problems]
The solid-state imaging device according to the present invention is
A plurality of photoelectric conversion elements for photoelectrically converting received light;
A plurality of charge transfer units for transferring signal charges from the plurality of photoelectric conversion elements;
A charge detector disposed adjacent to the plurality of charge transfer units for each predetermined unit;
The charge detector is
A floating diffusion region into which charges are injected from the charge transfer section ;
A reset transistor connected between a reset terminal for applying a voltage for resetting the floating diffusion region and the floating diffusion region;
A source follower output transistor having a gate connected to the floating diffusion region, a drain connected to a power supply terminal for supplying a power supply voltage, and a source connected to an output terminal;
The power supply terminal and the reset terminal are shared between the adjacent charge detection units ,
The common power / reset terminal, the floating diffusion region, the output terminal, and the gate electrode of the reset transistor are arranged side by side in the adjacent direction of the charge detection unit .
[0011]
In the solid-state imaging device having the above-described configuration, when a plurality of charge detection units having a floating diffusion configuration are arranged adjacent to each other, by sharing a power supply terminal and a reset terminal between adjacent charge detection units, the charge detection unit at one end is Except for this, it is possible to reduce one terminal per charge detection unit. As a result, it is possible to miniaturize individual charge detection portions by a width corresponding to one terminal that can be reduced.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0013]
FIG. 1 is a schematic configuration diagram illustrating a solid-state imaging device according to an embodiment of the present invention. Here, the signal charge photoelectrically converted by each pixel of the sensor unit (pixel unit) is transferred in the vertical direction by the vertical transfer unit, and is obtained by voltage conversion by the charge detection unit provided in the subsequent stage of each vertical transfer unit. As an example, a case where the present invention is applied to a horizontal solid-state CCD solid-state imaging device that sequentially reads out each signal voltage by horizontal scanning is described.
[0014]
In FIG. 1, a sensor circuit 20 and its peripheral circuit section 30 are mounted on a semiconductor substrate 10. The sensor unit 20 is arranged for each vertical pixel column with respect to the photosensors (photoelectric conversion elements) 21 including photodiodes and the like that are arranged two-dimensionally in a matrix on the semiconductor substrate 10. Each of the vertical CCDs 22 includes a vertical CCD (vertical transfer unit) 22 and a charge detection unit 23 arranged at the end of the transfer destination for each vertical CCD 22.
[0015]
The photosensor 21 photoelectrically converts the received light over the exposure period and accumulates signal charges generated by the photoelectric conversion. The vertical CCD 22 transfers signal charges read from each of the photosensors 21 in the vertical direction by being driven by, for example, four-phase clock pulses φV1 to φV4. From each of the vertical CCDs 22, signal charges are transferred to the corresponding charge detection unit 23 in units of one row (one line).
The charge detector 23 converts the signal charge transferred by the vertical CCD 22 into a signal voltage and outputs it. The configuration of the charge detector 23 is a feature of the present invention, and the specific configuration will be described later in detail.
[0016]
As an example, the peripheral circuit unit 30 includes a signal processing circuit 31 provided corresponding to each vertical pixel column of the sensor unit 20 and a horizontal readout that sequentially reads each signal voltage output through the signal processing circuit 31 by horizontal scanning. The output circuit 32 and the horizontal scanning circuit 33 are included.
[0017]
The signal processing circuit 31 includes a noise removing circuit that removes a noise component included in a signal voltage supplied via the output circuit 33, such as a CDS (Correlated Double Sampling). ing. The horizontal output circuit 33 is also one of the peripheral circuits mounted on the same semiconductor substrate 10, and is mounted on the substrate 10 together with the horizontal output circuit 33 and is sequentially output from a horizontal scanning circuit 34 including a shift register or the like. In synchronism with the pulse, signals for one line supplied through the signal processing circuit 32 are sequentially selected in units of pixels and output to the outside of the substrate 10 as the CCD imaging signal Vout.
[0018]
FIG. 2 shows two charge detection units 23-1 and 23-2 from the end of the charge detection unit group in which one charge detection unit 23 is provided corresponding to each of the plurality of vertical CCDs 22. It is a circuit diagram which shows a structure.
[0019]
In FIG. 2, the charge detection unit 23-1 located at the extreme end side is a floating diffusion region (hereinafter referred to as “FD region”) 41 into which signal charges are injected via the output gate 221-1 of the vertical CCD 22. −1, a reset transistor 42-1 having a source connected to the FD region 41-1 and a gate to which a reset gate pulse φRG is applied, and a power supply terminal 43 to which the gate is applied to the FD region 41-1 and a power supply voltage VDD is applied. -1 and an output circuit 46-1 including a source follower output transistor 45-1 having a drain connected to each other and a source grounded via a resistor 44-1.
[0020]
The drain of the reset transistor 42-1 is connected to the power supply terminal 43-2 of the adjacent charge detection unit 23-2, and the reset gate pulse φRG is given to the gate at a predetermined period, whereby the reset transistor 42-1 has the drain of the FD unit 41-1. The potential is reset to the power supply voltage VDD. The output transistor 45-1 converts the signal charge injected from the vertical CCD 22 into the FD unit 41-1 in units of pixels into a signal voltage, and outputs the signal voltage to the next stage circuit through the output terminal 47-1. For example, MOS transistors are used as the reset transistor 42-1 and the output transistor 45-1.
[0021]
Similarly to the first charge detection circuit 23-1, the second charge detection circuit 23-2 also includes an FD region 41-2 into which signal charges are injected via the output gate 221-2 of the vertical CCD 22, A source is connected to the FD region 41-2, a reset transistor 42-2 to which a gate is supplied with a reset gate pulse φRG, and a gate of the FD region 41-2 is shared with a drain terminal of the charge detection circuit 23-1. The power supply terminal 43-2 has a drain connected to the output terminal 46-2 and a source connected to the ground via a resistor 44-2. The output circuit 46-2 includes a source follower output transistor 45-2.
[0022]
The drain of the reset transistor 42-2 is connected to the power supply terminal 43-3 of the charge detection unit 23-3 adjacent to the opposite side of the charge detection circuit 23-1, and the reset gate pulse φRG is given to the gate. The potential of the FD unit 41-2 is reset to the power supply voltage VDD. The output transistor 45-2 converts the signal charge injected (transferred) from the vertical CCD 22 into the FD unit 41-2 in units of pixels into a signal voltage and outputs the signal voltage to the next stage circuit through the output terminal 47-2. MOS transistors are also used as the reset transistor 42-2 and the output transistor 45-2.
[0023]
In this circuit example, the output circuits 46-1, 46-2,... Are configured by a single output transistor 45-1, 45-2,... And resistors 44-1, 44-2,. Although an example has been given, the present invention is not limited to this, and it is of course possible to use an output circuit having a known source follower circuit configuration in which source follower stages composed of a driving MOS transistor and a load MOS transistor are connected in cascade. It is.
[0024]
FIG. 3 shows an example of a planar arrangement pattern in the case where, for example, two charge detection units 23-1 and 23-2 having the above configuration are arranged adjacent to each other. As can be seen from the figure, one charge detection unit 23-1 has a reset drain terminal in common with the power supply terminal 43-2 of the adjacent charge detection unit 23-2, thereby providing a power supply (VDD) terminal. 43-1, an FD region 41-1, an output terminal (VOUT) 47-1 and a gate electrode (RG) 48-1 of the reset transistor 42-1 are arranged side by side in order. ing.
[0025]
Next, the operation of, for example, the charge detection circuit 23-1 having the above configuration will be described with reference to the timing chart of FIG.
[0026]
When the output gate 221-1 is turned on (opened) in response to an input pulse at a certain time, the signal charge transferred by the vertical CCD 22 is injected into the FD region 41-1 via the output gate 221-1. Then, when the potential of the FD region 41-1 is C _{FD for} the FD capacitance of the FD region 41-1 and the charge amount (number) of the injected signal charge is Q _Tot , the FD capacitance C _FD and the charge amount Q _Tot are Determined potential ΔV, ie ΔV = Q _Tot / C _FD
The voltage is lowered from the reset level, that is, the power supply voltage VDD by the potential.
[0027]
This potential ΔV becomes a signal level, is detected as a signal voltage by the output transistor 45-1, and is passed to the next stage circuit through the output terminal 47-1. Thereafter, when the reset gate pulse φRG is applied to the gate of the reset transistor 42-1, the signal charge accumulated in the gate of the FD region 41-1, that is, the output transistor 45-1, is reset. As a result, the FD region 41 The potential of −1 becomes the power supply voltage VDD.
[0028]
As described above, in the horizontal scanning type CCD solid-state imaging device in which a plurality of charge detection units 23 having a floating diffusion configuration are arranged adjacent to each of the vertical CCDs 22, adjacent to each of the charge detection units 23 is formed. By sharing the power supply terminal and the reset drain terminal between the matching charge detection units 23-1, 23-2,..., One charge detection unit is provided for each charge detection unit except for one end of the charge detection unit. The number of electrodes, specifically, the electrodes of the reset drain terminal can be reduced one by one.
[0029]
As a result, each charge detector 23 can be miniaturized by a width corresponding to one electrode of the reset drain terminal that can be reduced. As described above, since the charge detection unit 23 can be miniaturized, the pitch of the vertical CCD 22 can be set narrow, and the horizontal pixel pitch of the photoelectric conversion element 21 can be narrowed accordingly, which can greatly contribute to further increase in the number of pixels. Become.
[0030]
In the above-described embodiment, the case where the present invention is applied to a horizontal scan type CCD solid-state imaging device in which one charge detection unit 23 is arranged for each of a plurality of vertical CCDs 22 has been described as an example. As shown in FIG. 5, the present invention can be similarly applied to a horizontal scan type CCD solid-state imaging device in which a plurality of vertical CCDs 22 are provided, for example, two units each, and one charge detection unit 23 is arranged for each unit. is there. In this horizontal scan type CCD solid-state imaging device, the signal charges transferred by the two vertical CCDs 22 and 22 are selectively transferred to the charge detection unit 23 by the output gate unit 24.
[0031]
As described above, in the horizontal scanning type CCD solid-state imaging device, by arranging two vertical CCDs 22 as a unit and one charge detection unit 23 for each unit, the number of the charge detection units 23 is reduced to half or less. Since it can reduce to the above, the arrangement space of each electric charge detection part 23 can be ensured reliably. In other words, compared to the case where one charge detection unit 23 is arranged for each of the plurality of vertical CCDs 22, the arrangement space of the entire charge detection unit 23 can be reduced by half or more, so The pitch of the pits and thus the horizontal pixel pitch can be reduced, thereby contributing to pixel miniaturization. In addition, as described above, by sharing the power supply terminal and the reset drain terminal between the adjacent charge detection units 23 and 23, the arrangement space of the charge detection unit 23 as a whole can be further reduced. Can contribute.
[0032]
In this application example, the case of applying to a horizontal scanning CCD solid-state imaging device in which two vertical CCDs 22 are provided as a unit and one charge detection unit 23 is arranged for each unit has been described as an example. However, the present invention is not limited to this, and the present invention can be similarly applied to a horizontal scan type CCD solid-state imaging device in which three or more vertical CCDs 22 are used as a unit and one charge detection unit 23 is arranged for each unit. is there.
[0033]
Further, the present invention is not limited to application to a horizontal scanning CCD solid-state imaging device, and as shown in FIG. 6, one row (one line) is transferred from the sensor unit 20 by each of the vertical CCDs 22. This is a so-called horizontal CCD type CCD solid-state image pickup device in which a signal charge is further horizontally transferred by a horizontal CCD (horizontal transfer unit) 51 and then converted into a signal voltage by a charge detection unit 52. The present invention can be similarly applied to an image sensor.
[0034]
That is, in a horizontal CCD type CCD solid-state imaging device, a plurality of horizontal CCDs 51, for example, two horizontal CCDs 51-1 and 51-2 are provided, and a distribution gate unit 53 is disposed between the horizontal CCDs 51-1 and 51-2. Thus, the signal charges are distributed to the two horizontal CCDs 51-1 and 51-2 by the action of the distribution gate unit 53, and are horizontally transferred in parallel by the horizontal CCDs 51-1 and 51-2. Since the driving frequency of 51-2 can be lowered as compared with the case of one horizontal CCD 51, the power consumption can be reduced correspondingly.
[0035]
In the horizontal CCD type CCD solid-state imaging device having the two horizontal CCDs 51-1 and 51-2, the charge detection units 52-1 and 52-2 are arranged at the transfer end sides of the horizontal CCDs 51-1 and 51-2. The signal charges transferred by the horizontal CCDs 51-1 and 51-2 are detected by the charge detection units 52-1 and 52-2, converted into signal voltages, and output. Therefore, the two charge detection units 52-1 and 52-2 are arranged adjacent to each other.
[0036]
Therefore, the present invention is applied to a horizontal CCD type CCD solid-state imaging device having the two horizontal CCDs 51-1 and 51-2, and a power supply terminal and a reset drain terminal are connected between the two charge detection units 52-1 and 52-2. Can be shared, the arrangement space of the entire charge detection units 52-1, 52-2 can be reduced. That is, as described above, since one charge detection unit 52 requires five terminal electrodes, it is necessary to provide a total of 10 terminal electrodes by the two charge detection units 52-1 and 52-2. On the other hand, since the terminal electrode can be reduced by one by sharing the power supply terminal and the reset drain terminal between the charge detection units 52-1, 52-2, the charge detection units 52-1, 52- are correspondingly reduced. As a result, the arrangement space of the entire two devices can be reduced, and as a result, the pitch between the two horizontal CCDs 51-1 and 51-2 can be reduced.
[0037]
【The invention's effect】
As described above, according to the present invention, when a plurality of charge detection units having a floating diffusion configuration are arranged adjacent to each other, the terminal electrode can be reduced by sharing the power supply terminal and the reset terminal between the adjacent charge detection units. Therefore, the individual charge detection units can be miniaturized.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing a horizontal solid-state CCD solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of two charge detection units.
FIG. 3 is a diagram illustrating an example of a planar arrangement pattern when two charge detection units are arranged adjacent to each other.
FIG. 4 is a timing chart for explaining the operation of the charge detection unit;
FIG. 5 is a schematic configuration diagram illustrating a horizontal scan type CCD solid-state imaging device according to another application example of the invention.
FIG. 6 is a schematic configuration diagram showing a horizontal CCD type CCD solid-state imaging device according to another application example of the invention.
FIG. 7 is a circuit diagram showing a general configuration of a charge detection unit.
FIG. 8 is a cross-sectional view showing structures of a floating diffusion region and a reset transistor.
FIG. 9 is a diagram illustrating an example of a planar arrangement pattern of charge detection units according to the related art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Peninsula timing board, 20 ... Sensor part, 21 ... Photoelectric conversion element, 22 ... Vertical CCD, 23, 23-1, 23-2, 52-1, 52-2 ... Charge detection part, 32 ... Horizontal output circuit, 33 ... Horizontal scanning circuit, 41-1, 41-2 ... Floating diffusion (FD) region, 42-1, 42-2 ... Reset transistor, 45-1, 45-2 ... Output transistor, 51-1, 51-2 ... Horizontal CCD

Claims (4)

A plurality of photoelectric conversion elements for photoelectrically converting received light;
A plurality of charge transfer units for transferring signal charges from the plurality of photoelectric conversion elements;
A charge detector disposed adjacent to the plurality of charge transfer units for each predetermined unit;
The charge detector is
A floating diffusion region into which charges are injected from the charge transfer section ;
A reset transistor connected between a reset terminal for applying a voltage for resetting the floating diffusion region and the floating diffusion region;
A source follower output transistor having a gate connected to the floating diffusion region, a drain connected to a power supply terminal for supplying a power supply voltage, and a source connected to an output terminal;
The power supply terminal and the reset terminal are shared between the adjacent charge detection units ,
The common power source / reset terminal, the floating diffusion region, the output terminal, and the gate electrode of the reset transistor are arranged in order in the adjacent direction of the charge detection unit . The plurality of charge transfer units are a plurality of vertical transfer units that are arranged for each vertical pixel column of the plurality of photoelectric conversion elements and transfer signal charges from the plurality of photoelectric conversion elements in a vertical direction,
The solid-state imaging device according to claim 1, wherein one charge detection unit is arranged for each of the plurality of vertical transfer units. The solid-state imaging device according to claim 2, wherein the charge detection unit is arranged for each of the plurality of vertical transfer units as a unit. The plurality of charge transfer units are a plurality of horizontal transfer units that transfer signal charges transferred by a plurality of vertical transfer units arranged for each vertical pixel column of the plurality of photoelectric conversion elements in a horizontal direction in parallel. Yes,
The solid-state imaging device according to claim 1, wherein one charge detection unit is arranged for each of the plurality of horizontal transfer units.

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