JPH06165040A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide the solid-state image pickup device suitable for high-speed image pickup. CONSTITUTION:Charge/voltage converting amplifiers 40-42 are provided at the output parts of respective partial shift registers 30-32 but a transistor for reset as one of the constitutive members of-these charge/voltage converting amplifiers 40-42 is arranged outside an area sandwiched by the plural partial shift registers 30-32. Therefore, the constitutive members of the charge/voltage converting amplifiers 40-42 arranged inside the area sandwiched by the plural partial shift registers 30-32 are reduced. Thus, even when the plural partial shift registers 30-32 are arranged in one column while reducing the intervals, the space for arranging the charge/voltage converting amplifiers 4O-42 is sufficiently secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a CCD image sensor.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional FFT method n-channel CC.
The structure of the D image sensor 100 is shown. Light receiving regions for performing photoelectric conversion are arranged in a matrix above the CCD image sensor 100, and the vertical transfer shift register 10 for serially transferring the signal charges generated in the respective light receiving regions.
Have one. In addition, the vertical transfer shift register 101
The horizontal transfer shift register 102 that inputs in parallel the signal charges output from the horizontal transfer shift register 102 and the charge-voltage conversion amplifier that converts the signal charges output from the horizontal transfer shift register 102 into a voltage, such as an FDA (floating diffusion amplifier). ) 103.

Japanese Unexamined Patent Publication No. 3-224371 discloses a parallel output type CCD image sensor which is an improvement of the CCD image sensor 100.

FIG. 6 shows a block diagram of the parallel output CCD image sensor 110. CCD image sensor 10
Although the basic configuration is the same as that of 0, the parallel output CCD image sensor 110 includes a plurality of output units 120 to 150, so that it is possible to divide and output all pixel signals by the number of output units. In this example, 1/4 of all pixels may be output from each output unit. Therefore, the parallel output CCD image sensor 110 can capture images at a higher speed than the CCD image sensor 100. For example, when reading is performed at a data rate of 10 MHz in an image sensor of 100,000 pixels, the CCD image sensor 100 has a limit of capturing 100 frames (100 frames / sec) per second. However, in the parallel output CCD image sensor 110 having the four output sections 120 to 150, it is sufficient to read out 25,000 pixels from each output section.
High-speed imaging of 0 frame / second is possible. If the number of output units is increased, it is possible to perform higher speed imaging.

FIG. 7 is a top structural view of the output section 120 of the parallel output CCD image sensor 110, and FIG. 8 is CC ′.
10 is a sectional structural view of the surface, FIG. 9 is an operation timing diagram, and FIG.
The potential diagrams of the AA ′ plane and the BB ′ plane are shown in FIG. C
The CD image sensor 110 includes a vertical transfer shift register 121 and a horizontal transfer shift register 122. Each register has a plurality of transfer electrodes 121a and 121a.
, 122a, 122b, ... are arranged side by side, and two adjacent transfer electrodes form one bit. The FDA 123 is provided at the output end of the horizontal transfer shift register 122.
Are arranged.

As shown in the sectional structure view of FIG.
23 is an OG (output gate) to which a proper bias is applied
123a, FD (floating diffusion) 123b which is in a floating state but whose potential changes due to inflow of signal charges, and RG (reset for resetting FD 123b to the potential of RD (reset drain) 123c. Gate) 123d. The potential change of the FD123b is caused by the source follower MOSF.
The impedance is converted by the ET 124 and output. The dotted line portion 125 indicates that the wiring is actually made of aluminum although it cannot be displayed on the sectional view.

Next, the operation timing chart of FIG. 9 and FIG.
CCD image sensor 11 using the potential diagram of
The operation of 0 will be described.

At time t1, the horizontal transfer shift register 1
The signal charge DL2 stored under the transfer electrode 122a of No. 22
Is transferred to the FDA 123 and converted into a voltage.

At time t2, a high level (H) voltage is applied to the RG 123d and the FDA 123 is reset. In addition, the transfer electrode 12 of the vertical transfer shift register 121
The signal charge DF2 stored under 1b is transferred to the transfer electrode 121a.
The signal charges DL1 stored in the horizontal transfer shift register 122 and below the transfer electrode 122b of the horizontal transfer shift register 122 are moved downward.
Move 2a down.

At time t3, a low level (L) voltage is applied to the RG 123d and the FDA 123 is put in a floating state.

At time t4, the signal charge D stored under the transfer electrode 122a of the horizontal transfer shift register 122 is reached.
L1 is transferred to the FDA 123 and output as a voltage signal. In addition, the transfer electrode 12 of the vertical transfer shift register 121
The signal charge DF2 stored under 1a moves under the transfer electrode 122d of the horizontal transfer shift register 122, and the signal charge DF3 stored under the transfer electrode 121c of the vertical transfer shift register 121 moves under the transfer electrode 121b.

At time t5, a high level (H) voltage is applied to the RG 123d again, and the FDA 123 is reset. Further, the signal charges stored under each transfer electrode of the horizontal transfer shift register 122 are shifted.

At time t6, a low level (L) voltage is applied to the RG 123d and the FDA 123 becomes in a floating state.

At time t7, the signal charges stored under each transfer electrode of the horizontal transfer shift register are shifted,
The signal charge DF1 is transferred to the FDA 123 and output as a voltage signal.

By repeating the above operation for the number of transfer stages of the horizontal transfer shift register, the signal charge for one line of the pixel can be read from the FDA 123. Further, by repeating this for the number of vertical pixels, the signals of all pixels can be read.

[0016]

As described above, in order to speed up the image capturing by the parallel output image sensor 110, the horizontal transfer shift register of the parallel output image sensor 110 should be divided to provide a large number of output sections. Good. However, since it is desirable that the horizontal pitch of the pixels and the horizontal transfer shift register pitch be the same, it was not possible to secure a sufficient space for forming the floating diffusion amplifier in the output section.

It is an object of the present invention to solve such a problem and to provide a solid-state image pickup device suitable for high-speed image pickup.

[0018]

In order to solve the above-mentioned problems, a solid-state image pickup device of the present invention comprises a plurality of vertical transfer shift registers for serially transferring charges generated according to the amount of incident light, and a plurality of vertical transfer shift registers. A horizontal transfer shift register that inputs in parallel the charges output from the transfer shift register and transfers them in series, and the horizontal transfer shift register is composed of a plurality of partial shift registers. Each of them is provided with a charge-voltage conversion amplifier, and the reset transistor that constitutes the charge-voltage conversion amplifier is arranged outside the region sandwiched by a plurality of partial shift registers.

[0019]

According to the solid-state image pickup device of the present invention, the output portion of each partial shift register is provided with the charge-voltage conversion amplifier. The reset transistor, which is one of the members constituting the charge-voltage conversion amplifier, is provided. Are arranged outside the region sandwiched by the plurality of partial shift registers. Therefore, the number of constituent members of the charge-voltage conversion amplifier arranged inside the region sandwiched by the plurality of partial shift registers is reduced. As a result, even when a plurality of partial shift registers are arranged in a row with a narrow interval, a sufficient space for arranging the charge-voltage conversion amplifier can be secured.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the solid-state image pickup device according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a parallel output CCD image sensor 10 according to this embodiment. Parallel output CCD image sensor 10
Light receiving regions for performing photoelectric conversion are arranged in a matrix form on the upper part of, and a plurality of vertical transfer shift registers 20 for serially transferring the signal charges generated in the respective light receiving regions are provided. Further, these vertical transfer shift registers 20 are divided into a plurality of groups, and each group of vertical transfer shift registers 20 is divided.
A plurality of sets of horizontal transfer shift registers 30 to 32 that input in parallel the signal charges output from the horizontal transfer shift registers, and an FDA (floating diffusion) that converts the signal charges output from the horizontal transfer shift registers 30 to 32 into a voltage. Amplifiers) 40 to 42.

When the CCD image sensor is classified by the pixel configuration, the light receiving section and the transfer section are laid out side by side, and the IT (interline transfer) method in which the signal charges are transferred to the transfer section at a time and then sequentially transferred and read out, The transfer unit is used as it is as a MOS capacitor type light receiving unit, and is transferred to the storage unit during the vertical blanking period and is sequentially read from this storage unit. Although a frame transfer method or the like is known, an FFT method CCD image sensor is used in this embodiment.

The signal charges generated in each light receiving region are accumulated in the vertical transfer shift register 20 and transferred to the horizontal transfer shift registers 30 to 32 by serial shift. The signal charges transferred to the horizontal transfer shift registers 30 to 32 are
It is given to the FDAs 40 to 42 by serial shift and is output as a voltage signal.

Next, a parallel output CCD according to this embodiment
FIG. 2A is a top view of the output part of the image sensor 10.
2B shows a sectional view taken along the line AA ′. Horizontal transfer shift registers 30 and 31 are provided at the output ends of the vertical transfer shift registers 20, and the signal charges output by serial shift from the vertical transfer shift registers 20 are transferred to the horizontal transfer shift registers 30 and 31. Electrode 3
0b, 30e, 31b, ... Store below. FDAs 40 and 41 are provided at the output ends of the horizontal transfer shift registers 30 and 31, respectively. The FDA 41 includes an OG (output gate) 41a to which a proper bias is applied, an FD (floating diffusion) 41b that is in a floating state but changes in potential due to the inflow of signal charges.
The FD 41b is composed of a MOSFET 41c for resetting. The MOSFET 41c has an RG for resetting the FD 41b to the potential of RD (reset drain).
(Reset gate) is provided. The signal charges output from the horizontal transfer shift registers 30 and 31 by serial shift are given to the FDs 40b and 41b of the FDAs 40 and 41. Source follower M for FD40b and 41b
The gate electrodes of the OSFETs 50 and 51 are connected,
The potential change due to the inflow of the signal charges into the FDs 40b and 41b is impedance-converted and output.

The vertical transfer shift register 20 and the horizontal transfer shift registers 30 and 31 are both operated by two-phase driving, and have two transfer electrodes (20a, 20b) and (30a, 30a,
30b), (30d, 30e), (31a, 31b),
1 bit is composed of ...

MOSFET as a component of FDA 41
41 c is arranged apart from the area sandwiched between the horizontal transfer shift register 30 and the horizontal transfer shift register 31. Therefore, the OG 41a and the FD 41b are the only constituent members of the FDA 41 provided between the horizontal transfer shift register 30 and the horizontal transfer shift register 31. Accordingly, in this embodiment, the interval between the horizontal transfer shift register 30 and the horizontal transfer shift register 31 can be narrowed, and the horizontal transfer shift register 30 and the horizontal transfer shift register 3
1 and 1 can be arranged in a line. As described above, in this embodiment, the plurality of horizontal transfer shift registers 30, 31,
Is provided and the image data is output from many output units, the high-speed imaging is realized.

The parallel output CCD according to the present embodiment
The operation timing of the image sensor 10 is the same as the operation timing of the conventional parallel output CCD image sensor 110 shown in the operation timing chart of FIG.

Next, FIG. 3 shows the upper surface structure of the output portion of the parallel output CCD image sensor 70 according to another embodiment of the present invention. From the figure, the horizontal transfer shift registers 71, 7
FD73 of FDA73 and 74 provided at the output end of 2
a and 74a extend outside the horizontal transfer shift registers 71 and 72. Then, RDs 73b, 74b, RGs 73c, 74c are provided at the tips of the FDs 73a, 74a. With this structure, the constituent members of the FDA 74 provided between the horizontal transfer shift register 71 and the horizontal transfer shift register 72 are FD74a and O
Only G74d. As a result, this embodiment can obtain the same effect as that of the embodiment of FIG.

The operation timing of the parallel output CCD image sensor 70 according to this embodiment is the same as that of the conventional parallel output CCD image sensor 1 shown in the operation timing chart of FIG.
It is the same as the operation timing of 10. In addition, the parallel output CCD image sensor 70 according to the present embodiment is AA ′.
The cross-sectional structure is the same as the cross-sectional structure shown in the cross-sectional structure diagram of FIG.

Next, FIG. 4 shows the upper surface structure of the output portion of the parallel output CCD image sensor 80 according to a modification of the embodiment of FIG. In this modification, the horizontal transfer registers 81 and 8 are
By bending the final transfer electrodes 81a and 82a to the outside of 2, the same effect as that of the embodiment of FIG. 3 can be obtained.

The parallel output CCD image sensor 80 according to the present modification has the same operation timing and AA ′ plane sectional structure as the conventional parallel output CCD image sensor 110.
Is the same as.

In this embodiment, the transfer gate lengths of several bits adjacent to the FDAs 40 to 42 among the respective bits of the horizontal transfer shift registers 30 to 32 are defined as the transfer charge amount,
FD is shortened within the range that does not affect other characteristics.
It is more effective when used in combination with measures such as securing a space for incorporating A40 to A42.

In this embodiment, an FFT type n-channel CCD is assumed, but the present invention is not limited to this CCD, and an IT type or FT type CCD can also be a p-channel CCD.
However, the same effect can be obtained.

Further, in the present embodiment, the case where the horizontal transfer shift registers 30 to 32 are two-phase driven has been described.
Similar effects can be obtained by phase drive, four phase drive, and the like.

[0034]

According to the solid-state image pickup device of the present invention, a charge-voltage conversion amplifier is provided at the output of each partial shift register. For resetting, which is one of the components of this charge-voltage conversion amplifier. The transistor is arranged outside the region sandwiched by the plurality of partial shift registers. For this reason, the number of constituent members of the charge-voltage conversion amplifier arranged inside the region sandwiched by the plurality of partial shift registers is reduced, so that the space for disposing the charge-voltage conversion amplifier is sufficiently secured.

Therefore, it is possible to divide the horizontal transfer shift register into many partial shift registers and arrange them in a line in accordance with the demand for higher speed of the solid-state image pickup device.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a parallel output CCD image sensor according to an embodiment.

FIG. 2 is a diagram showing a top surface structure of an output portion of a parallel output CCD image sensor according to the present embodiment.

FIG. 3 is a parallel output CCD according to another embodiment of the present invention.
It is a figure which shows the upper surface structure of the output part of an image sensor.

FIG. 4 is a diagram showing a top surface structure of an output section of a parallel output CCD image sensor according to the present modification.

FIG. 5 is a top structural view showing a configuration of a conventional FFT type n-channel CCD image sensor.

FIG. 6 is a top structural view showing a configuration of a conventional FFT type n-channel CCD image sensor.

FIG. 7 is a top structural view of an output portion of a conventional parallel output CCD image sensor.

FIG. 8 C of a conventional parallel output CCD image sensor
It is a cross-sectional structural view of the -C 'plane.

FIG. 9 is an operation timing chart of a conventional parallel output CCD image sensor.

FIG. 10 is a potential diagram of AA ′ surface and BB ′ surface of a conventional parallel output CCD image sensor.

[Explanation of symbols]

10 ... Parallel output CCD image sensor, 20 ... Vertical transfer shift register, 30, 31, 32 ... Horizontal transfer shift register, 40, 41, 42 ... FDA, 50, 51 ...
Source follower MOSFET.

Claims (1)

[Claims] 1. A plurality of vertical transfer shift registers for serially transferring charges generated according to the amount of incident light, and charges output from the plurality of vertical transfer shift registers in parallel for serial transfer. In a solid-state imaging device including a horizontal transfer shift register, the horizontal transfer shift register is composed of a plurality of partial shift registers, and a charge-voltage conversion amplifier is provided at an output section of each of the partial shift registers. The solid-state imaging device, wherein the resetting transistor forming the charge-voltage conversion amplifier is arranged outside an area sandwiched by the plurality of partial shift registers.