JPH01147972A - Charge transfer type solid-state image pickup element - Google Patents

Abstract

PURPOSE:To expand the dynamic range of a vertical CCD shift register by a multiple of N by carrying a signal charge stored by a photoelectric conversion element to a storage area by the vertical CCD shift register while dividing it for plural number of times. CONSTITUTION:The optical signal charge stored during one field period or one frame period by a photoelectric conversion element 3' constituting an image pickup area 1' is read for plural number of times by controlling a switch pulse voltage impressed to a transfer switch 4'. Every time the signal charge read by the vertical CCD shift register 2; with split is read out, the charge is fed to the storage area 5' by high speed transfer of the vertical CCD shift register 2'. Thus, even if the charge storage capacity of the vertical CCD is not increased, the charge stored in the photoelectric conversion element is transferred sufficiently by operating the switching number of times of the transfer gate with split.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a photoelectric conversion element on a semiconductor substrate and a charge transfer element (Charge Co., Ltd.) for extracting optical information from each element.
Upled Device, hereinafter abbreviated as CCD. ) is related to a solid-state image sensor using

[Conventional technology]

Solid-state imaging devices must have the same resolution as the electronic imaging tubes used in current television broadcasting.
Therefore, there are 500 pieces in the vertical direction and 800 to 10 pieces in the horizontal direction.
A matrix of 00 picture elements (photoelectric conversion elements) and a corresponding scanning element are required. Therefore, the solid-state imaging device is manufactured using MO8 large-scale circuit technology that requires high integration, and generally uses CCDs, MOS transistors, etc. as constituent elements. Figure 2 shows the frame interline method (hereinafter referred to as
This figure shows a CCD solid-state image sensor (abbreviated as FIT method). This element is, for example, Horii et al.

It is described in "Study of small CCD solid-state image sensor" Journal of Television Society, Vol. 37, p. 788 (1983).

1 is an imaging area, which includes a vertical CCD shift register 2, a photoelectric conversion element 3 (for example, a photodiode), and a transfer gate 49.
It consists of etc. Reference numeral 5 denotes an accumulation region for temporarily accumulating the signal charge stored in the photodiode, and it is composed of two selection gates 6 and a CCD shift register 7 for accumulation. Reference numeral 8 designates a horizontal CCD shift register that transfers the signals of each row sent out one column at a time by the storage CCD shift register 7 toward an output 9.

In the image sensor having this configuration, the signal charges read from the photodiode 3 are transferred from the imaging area 1 to the storage area 5 at high speed (in a short time) by operating the CCD shift registers 2 and 7 at high speed.

Therefore, when transferring signals, the vertical CCD shift register 2
The amount of optical false signals leaked into the device is reduced from several tenths to one hundredth of that of conventional interline devices, making it possible to significantly reduce smear noise.

Here, the smear is a phenomenon caused by a false light signal leaked to the vertical CCD shift register 2, and a vertical striped pattern appears above and below a high-luminance optical information pattern (that is, a bright pattern) on the monitor. This is a phenomenon unique to solid-state image sensors, and has been the main cause of image quality deterioration. On the other hand, with the FIT method, smear is greatly reduced and high image quality can be obtained, and two-wire method elements are expected to have a promising future.

[Problem that the invention seeks to solve]

However, in general, C
The aperture ratio (that is, light-receiving area) of the CD image sensor is as low as about 1/2 of that of the MO8 image sensor, which causes a decrease in photosensitivity. Also, the amount of charge that can be accumulated in the photodiode is vertical C
Limited by the charge storage capacity of the CD shift register 2, the amount of accumulated charge (ie, dynamic range) of the CCD image sensor is as small as 174 to 115 of the MO8 image sensor.

In order to increase the aperture ratio, it is necessary to reduce the area of areas not related to photoelectric conversion, such as the vertical CCD shift register, but this further reduces the amount of accumulated charge (dynamic range) of the originally small vertical CCD shift register. Resulting in. Therefore, in order to improve the performance of the FIT type D image sensor, it is important to increase the dynamic range of the vertical CCD shift register.

The purpose of the present invention is to solve the above problems,
It is an object of the present invention to provide a charge transfer type solid-state image sensor that has an expanded aperture ratio and dynamic range than a FIT type D image sensor.

[Means for solving problems]

The object of the present invention is to provide, on the same semiconductor substrate, an imaging area comprising a group of photoelectric conversion elements, a transfer switch, and a scanning element that carries optical signal charges stored in the group of photoelectric conversion elements;
In a solid-state imaging device that integrates a storage region that temporarily accumulates optical signals detected in this imaging region, by controlling the pulse voltage applied to the transfer switch, the optical signal charge stored in the photoelectric conversion element is transferred. A charge transfer type solid-state imaging device characterized by comprising means for reading out the signal charge in multiple times and means for sequentially sending the read signal charge to the accumulation region by high-speed transfer operation of the scanning element. achieved.

To explain the feature of the present invention in more detail, the optical signal charges accumulated in the photoelectric conversion elements constituting the imaging area can be transferred for one field period or by controlling the switch pulse voltage applied to the transfer switch. During one frame period, the accumulated optical signal charge is divided into multiple times and read out.

The feature is that each time the divided signal charges are read out to the vertical CCD shift registers, they are sent to the accumulation region by the high-speed transfer operation of the vertical CCD shift registers.

The optical signal charge accumulated in the photoelectric conversion element is read out by dividing it into multiple times, and the timing of sending it to the storage area via the vertical CCD shift register may be divided into any number of times, but it is practical. is preferably divided into 2 to 5 times, more preferably 3 to 4 times. In addition, the amount of optical signal charge sent out (read) at one time may be the average value of the number of times of 2 divisions, and when the number of 2 divisions is N times, the first time is the amount of 1/N, and the remaining The amount of charge may be equally or unevenly divided N-1 times, and any method may be used as to how to divide into one. In any case, what is important in the present invention is that the optical signal charge accumulated in the photoelectric conversion element is divided into a plurality of times and sent from the vertical CCD shift register to the accumulation region at high speed.

[Effect]

As described above, in the charge-transfer type stationary image pickup device of the present invention, the image signal charge accumulated in the photoelectric conversion element is transferred to the vertical CCD by switching the transfer gate in a plurality of times (N times). Charge can be transported to the storage region by high-speed operation.

Therefore, even if the charge storage capacity of the vertical CCD is not increased, the charges accumulated in the photoelectric conversion element can be sufficiently transferred by dividing the number of switching times of the transfer gate into a predetermined number of times.

〔Example〕

The present invention will be described in detail below using examples.

FIG. 1 is a diagram showing an embodiment that is the gist of the present invention.

This is a schematic diagram showing a planar pattern of a charge transfer type solid-state imaging device. In FIG. 1(a).

2' is a vertical CCD shift register (hereinafter referred to as vertical COD), and 3' is a photodiode, which constitute an imaging area 1'. 10 is a capture gate, 11 is a CCD shift register for storage (hereinafter referred to as a CCD shift register).

(referred to as storage CCD), and these are storage area 5'
It consists of The optical signal charge Q stored in the photodiode during one field period or one frame period passes through the transfer gate 4' multiple times (N times, where N is a positive integer of 2 or more).
By opening and closing over the vertical COD, it is fed into the storage CCD 11 that constitutes the storage area. This divided transfer operation will be explained using the transfer gate drive pulse (RP) shown in FIG. 1(b). RPC is a traditional CcD
This figure is shown in order to compare the structure, operation 2, etc. of two elements of the present invention using pulses for driving the field image element transmission gate 4 (shown in FIG. 2). This pulse indicates that the transfer gate is passed through once during the vertical retrace interval (ta). On the other hand, RPN is a pulse for driving the transfer gate 4' (shown in FIG. 1(a)) of the device of the present invention; This shows that the transfer gate 4' is placed in a twice-passed state. To make the transfer gate conductive N times, it is sufficient to generate N pulses during the vertical retrace period, but here, to simplify the explanation of the operation, we will use N = 2 pulses. The operation of the device of the present invention will be explained using a case as an example.

(1) At time t□□, a pulse RPN having a voltage amplitude of the ``M'' level is applied to the transfer gate 4'. Fig. 1 (Q) schematically shows the structure of the pixels constituting the imaging area. It is an explanatory diagram, and 4''E is a transfer gate electrode, and 2'-E is an electrode constituting a vertical CCD.

3'-D is a diffusion layer for photodiodes (for example, N pieces).

12 is a semiconductor substrate (for example, P type), 2'-B is a vertical C
An impurity layer (for example, n-type) is used to make the CD a buried channel, and 13 is a gate oxide film (for example, SiO2) for insulating and separating the electrodes 2'-E and 4'-E from the substrate. By applying the pulse RP)4(tx, ), potentials such as φ and □ are formed in each region of the pixel portion. Here, φt1□(4') is M level transfer gate pulse RP
The voltage formed under the transfer gate by N(t□□〉), φ
(2') is a vertical CCD driving pulse (vp
, not shown).

This is the potential formed under the vertical CCD electrode. Also.

φ(3'L) is the potential at which the photodiode is placed after charge readout is completed by the H level transfer gate pulse during the previous readout (field before previous readout or readout in the previous frame) (hereinafter referred to as reset potential) , φ (%U) is the field period (TF (□) = T F (2) ) +
Or frame period CTF<x> + TF(2))
This is the potential formed by the charge Q stored in the photodiode due to light incident on the photodiode. The upper limit of this potential φ (3'υ) is determined by the potential formed under the transfer gate by the L level transfer gate pulse RPN, as shown by the dotted line in FIG. 2C.

The potential increase due to accumulated charge is ΔV (=φ(3' U)
-φ(3'L)), then 2M level pulse RP
Due to N(ti,), the potential under the transfer gate φ, 1□(4'
) should be φ(3'L)+. By setting such a potential.

The charge of the photodiode is read out to the vertical CCD via the transfer gate 4' from the potential φ(3'υ) to the potential Δ■φ(3'U)-□. Namely.

Half (Q/2) of the charge Q accumulated in the photodiode is sent to the vertical COD by the first readout. The charge Q/2 sent to the vertical COD is then sent to the storage region 5' by a high-speed transfer operation of the vertical CCD 2' (shown in FIG. 1(a)).

(2) When the first charge transfer to the storage region is completed, 2
Transfer gate pulse RPN (
t(2) is applied to the transfer gate 4'.

The potential below the vertical CCD electrode is the same potential φ(2') as during the first readout (it is not necessary to set it to the same potential as the first readout, just set it to a lower potential than below the transfer gate) , and the potential below the transfer gate is set to the potential φtiz(4'>(=φ(J'L)) by RPH(t□2).Therefore, the potential of the photodiode is ΔV φ(i'U)-□ From, when the charge reading is completed, φ(
3'L). As a result, the potential of the photodiode drops by ΔV/2, and the remaining half of the charge remaining in the photodiode is sent to the vertical CCD via the transfer gate. This charge read out the second time is
After this, the storage area 5' is
sent to.

This high-speed transfer is performed within the vertical blanking period (tBL).

(3) Even during the vertical retrace period of the second field, the transfer gate pulse RP has the same level as the previous field.
N(tz□) s RP N(□2) to transfer gate 4'
By applying this voltage, the charge stored in the photodiode is divided into the first and second times and sent to the accumulation region 5' by the same operation as the previous time.

The operation of reading out the charges accumulated in the photodiode twice and sending the charges into the accumulation region 5' by two high-speed operations of the vertical CCD has been described above. If the transfer pulse is generated N times during the vertical retrace period, the charge can be divided and transferred N times. Therefore, the charge storage capacity of the vertical CCD can be reduced to 1/N compared to the conventional readout method in which all the data is sent at one time. That is, by reducing the channel width of the vertical CCD or increasing the number of stages of the vertical CCD or increasing the number of bits, it becomes possible to send many types of optical signal charges. Furthermore, in the above explanation, the operation was shown in which the same amount of charge (Q/N) is sent each time N readings are performed, but it is of course possible to send different amounts of charge (for example, 2
In the case of multiple readings, the first reading is Q/3. 2Q/3 for the second time
).

Next, a method of collecting charges read out N times in the storage region 5' into the same memory cell as described above will be described using an embodiment. Note that the charges read out from the same photodiode must be extracted in the form of N times of addition at the time of output. However, if a memory or the like is provided in the output section 9 (which may be inside or outside the element), there is no need for addition, and each batch may be taken out independently.

In the embodiment of FIG. 3, 10-1 is an intake gate;
11-. 1 and 11-2 are storage CCUs, and 14 is an addition circuit.

15 and 16 are storage area transfer gates.

(1) In the first read, charge q is first sent to the storage CGD 11-1 via the gate 10-1.

(2) Subsequently, by turning on the transfer gate 15, the charge q temporarily held in the storage CCDll-1 is transferred to the storage CCDll-2.

(3) Next, the second read charge q2 is applied to the gate 10-
1 to the storage CCD 11-1.

Charge qx held in storage CGDIl-1, 11-2
+q2 is sent to the adder circuit 14 via the transfer gate 16, where the divided and read charges q1e q2 are combined to form Q ("qt+ 92).

(4) The charges Q added by the circuit 14 are sent to the horizontal CCD 8 and taken out from the output 9 in time sequence.

Here, to simplify the explanation, we have described the case where the charge is divided into two times and sent to the storage CCD, but it may also be read out in N times.
It is possible to consider a configuration in which ti-N pieces are provided.

In the embodiment of FIG. 4, 10-2 is an intake gate;
11-1 and 11-2 are storage CCDs.

(1) During the first reading, the charge q is sent to the storage CCD 11-1 by the selection operation of the gate 10-2.

(2) The second read charge q2 is sent to the storage CCDll-2 by the selection operation of the gate 10-2.

(3) After this, the addition operation as described above is performed and the charge Q is taken out from the output.

FIG. 5(a) shows that the first charge q□ and the second charge q2 are sent to the storage CCDs 11-1 and 11-2 by the method shown in FIG. 3 or 4. This figure shows an embodiment in which the remaining charges are taken out without providing an adding circuit. Here, the charge qx+ 92 divided into two is indicated by the arrow 17-1
, 17-2, the horizontal CCD 8'
arrow 17-3 by well-known charge transfer methods.
As shown in , two charges are added by the horizontal CCD transfer operation.

In FIG. 5(b), the first charge q.

The second charge q2 is sent to the storage CCDs 11-1 and 11-2 by the method shown in FIG. 3 or 4. Charge q + qz are arrows 19-1, 19-2
As shown in
sent to. Charge qsp transferred in horizontal CCD
After q2 is added by an adder circuit 18 provided at the output end of the horizontal CCD, it is sequentially taken out from the output 9.

Figure 5(c) shows charge qttq2 as horizontal CC, D8'-1
, 8'-2 and taken out directly (without addition) to outputs 9-1, 9-2.

The addition of qxeqz is performed by an adder circuit (not shown) provided after the outputs 9-1, 9-2. This adder circuit may be integrated within the element, or may be provided separately outside the element.

〔Effect of the invention〕 As described above in detail using the examples.

According to the present invention, the signal charge stored in the photoelectric conversion element is divided into multiple times (Nl: N is a positive integer of 2 or more) and transferred to the vertical CCD.
Since it can be carried to the storage area by the shift register, there is an effect that the dynamic range of the vertical COD shift register can be expanded by N times. Therefore, the narrow dynamic range of vertical CCD shift registers, which has been a problem up to now, can be solved.

Furthermore, according to the present invention, even if the channel width of the vertical CCD shift register is reduced to 1/N of the conventional one, it is possible to maintain the same dynamic range as the conventional one. this is,
If you plan to increase the number of pixels (higher resolution) in the future, or
This is an excellent means for improving sensitivity9, and the practical value of the present invention is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration and operation of the CCD solid-state image sensor of the present invention, FIG. 2 is a diagram showing the configuration of a conventional CCD solid-state image sensor, and FIGS. FIG. 3 is a diagram showing an element configuration different from the embodiment shown in FIG. 2; In fig. 1.1'...Imaging area 2.2'...Vertical CCD shift register 3.3'...
・Photoelectric conversion element 4,4'...Transfer gate 5,5'...Storage region 7
．． 11...Storage CCD shift register 8...Horizontal CCD shift register 9...Output 14...Additional circuit attorney Junnosuke Nakamura Figure 1 (Q) 1' --- Eyelid fl q Relatives 8-11 Eiko CC
D shift register η2゛--CD shift register 9
--- and force 5'- width area Fig. 2 9-1-t Ka@11 (φt12-n 11shi2-i soil (φt, Lee-〇- Fig. 3 10-2--distributed area Fig. 5(a) 10-2-m-take Δ and gate Fig. 5(b) 10-2-m-take) +y: t

Claims (1)

[Claims] 1. On the same semiconductor substrate, an imaging area consisting of a photoelectric conversion element group, a transfer switch, and a scanning element that carries optical signal charges stored in the photoelectric conversion element group; In a solid-state imaging device that integrates a storage region that temporarily stores detected optical signals, the optical signal charge stored in the photoelectric conversion element is divided into multiple times by controlling the pulse voltage applied to the transfer switch. 1. A charge transfer type solid-state imaging device, comprising: means for reading out the signal charges; and means for sequentially sending the read signal charges into the accumulation region by high-speed transfer operation of the scanning element. 2. The charge transfer type solid-state imaging device according to claim 1, characterized in that the timing at which the optical signal charge stored in the photoelectric conversion element is divided into a plurality of times is within one field period or one frame period. . 3. The charge transport type solid-state imaging device according to claim 2, wherein the number of times the optical signal charge is divided is 2 to 5 times.