JP2005020716A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size of cells and time required to inspect discharge in all photoelectric conversion units by reducing the number of transistors and wirings in one photoelectric conversion cell. <P>SOLUTION: A readout pulse line 34 is provided that is common to and supplies signals for switching to transfer gates 15, 16, 19, and 20, which are added to photo diodes (PD) units 1, 2, 5, and 6 disposed on a pair of rows adjacent to each other, respectively. The readout pulse line 34 switches each of the transfer gates to transfer the discharge of the PD units on the pair of rows adjacent to each other to floating diffusion (FD) units 9, 10, 12, and 13, which differ from each other. Pixel amplification units 25, 26, 27, and 27, which are provided in correspondence with each FD unit, detects discharge generated. Pixel signals on a pair of rows are acquired simultaneously on output signal lines 38, 39, 40, and 41. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device in which a plurality of photoelectric conversion units for photoelectrically converting incident light are arranged.

  A FDA (Floating Diffusion Amplifier) type MOS image sensor is known. In this MOS type image sensor, a photoelectric conversion cell having four transistor gates and five wirings is generally used (see Patent Document 1).

In addition, there has been a device in which the configuration of the photoelectric conversion cell itself is devised for the purpose of reducing the power consumption of the MOS image sensor and improving the aperture ratio (see Patent Documents 2 and 3).
Japanese Patent Laid-Open No. 11-274455 JP 2002-335455 A JP 2002-354343 A

  In the photoelectric conversion cell having the above four transistor gates and five wirings, for example, when the area of the photoelectric conversion cell is 4.1 μm × 4.1 μm, if the design is performed with the rule of 0.35 μm, the photoelectric conversion cell composed of a photodiode is used. The aperture ratio of the conversion part is only about 5%.

  An object of the present invention is to improve an aperture ratio of a photoelectric conversion unit in each photoelectric conversion cell by paying attention to photoelectric conversion cells in adjacent rows.

  In order to achieve the above object, according to the present invention, a plurality of photoelectric conversion units arranged two-dimensionally, a floating diffusion (FD) unit to which charges of the photoelectric conversion unit are transferred, and the photoelectric conversion unit In a solid-state imaging device comprising: a transfer gate for transferring charges to the FD unit; a pixel amplifier for detecting the potential of the FD unit; and an output signal line for outputting a detection signal of the pixel amplifier. A readout wiring for supplying a signal for switching the transfer gate is provided in common to the transfer gates attached to the photoelectric conversion units in a pair of rows, and the transfer gates are connected through the common readout wiring. Switching is performed to transfer the charges of the photoelectric conversion units in a pair of adjacent rows to the FD units different from each other, and provided corresponding to the FD units. The serial pixel amplifier, detects the generated electric charge.

  According to the present invention, the number of transistors and the number of wirings per photoelectric conversion cell can be reduced, and the aperture ratio of the photoelectric conversion unit is improved. Further, since reading is performed in units of two rows, charges from all the photoelectric conversion cells can be read out in a short time.

  Hereinafter, solid-state imaging devices according to embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration example of a solid-state imaging device according to the present invention. In FIG. 1, reference numerals 1 to 8 denote photodiode (PD) units that perform photoelectric conversion. Floating diffusion (FD) sections 9 to 14 that store charges after photoelectric conversion are arranged adjacent to the PD sections 1 to 8. Charge transfer from each PD unit 1 to 8 to each FD unit 9 to 14 is performed via transfer gates 15 to 22. Reset gates 23 and 24 for discharging the charges are connected to the FD portions 9 to 14. The FD units 9 to 14 are connected to the gates of the pixel amplifiers 25 to 28 for performing charge detection. The load transistors 29 to 32 form a source follower amplifier together with the pixel amplifiers 25 to 28.

  In FIG. 1, 33 is a cell power line (VDDCELL), 34 and 35 are read pulse lines (READ) for applying a pulse voltage to the transfer gates 15 to 22, and 36 and 37 are discharging charges of the FD sections 9 to 14. Reset pulse line (RESET), 38 to 41 are output signal lines (VOUT) for transmitting detection voltages of the FD units 9 to 14, 42 is a load gate line for applying a signal to the gates of the load transistors 29 to 32, 43 Is a source power line for the load transistors 29-32.

  FIG. 2 shows drive timings within one horizontal blanking period in the solid-state imaging device of FIG. The signal charge is detected for the photoelectric conversion cells arranged in the first and second rows in a certain horizontal blanking period, and in the next horizontal blanking period, the second and third rows are used. Detection is performed every time. At this time, signal charges are detected simultaneously for two rows.

  First, charges in the PD portions 1, 5, 2, and 6 in the first and second rows are transferred. Therefore, a predetermined voltage is applied to the load gate line 42 and the source power supply line 43 so that the load transistors 29, 30, 31, and 32 are constant current sources. Next, after the cell power supply line 33 is set to HIGH, the reset pulse lines 36 and 37 are set to HIGH, the reset gates 23 and 24 are turned on, and the charges of the FD portions 9, 10, 12 and 13 are discharged. At this time, the signal level at reset is detected by the pixel amplifiers 25, 26, 27, and 28, and a black level signal clamp is performed in the noise cancellation circuit (not shown) through the output signal lines 38, 39, 40, and 41.

  Next, the reset pulse lines 36 and 37 are set to LOW to turn off the reset gates 23 and 24, and then a HIGH voltage is applied to the read pulse line 34 to turn on the transfer gates 15, 16, 19, and 20. As a result, the charges accumulated in the PD units 1, 2, 5, and 6 are transferred to the corresponding FD units 9, 10, 12, and 13, respectively. With respect to the charges transferred to the FD units 9, 10, 12, and 13, the signal amplifier levels are detected by the pixel amplifiers 25, 26, 27, and 28, respectively, and passed to the noise cancellation circuit through the output signal lines 38, 39, 40, and 41, respectively. Signal sampling. By this operation, it is possible to detect the output signal from which the pixel amplifiers 25, 26, 27, and 28 have the threshold variation and noise components removed.

  Next, when the cell power line 33 is set to LOW and the reset pulse lines 36 and 37 are set to HIGH and the reset gates 23 and 24 are turned on, the FD units 9, 10, 12, and 13 are set to the LOW level of the cell power line 33. Thus, the pixel amplifiers 25, 26, 27 and 28 do not operate. Thereafter, the pixel amplifiers 25, 26, 27, and 28 do not operate until the read pulse line 34 is selected by a vertical line scanning circuit (not shown), so that the pixel amplifiers 25 are not selected. In the next horizontal blanking period, the charges of the PD units 3, 4, 7, and 8 in the third row and the fourth row are transferred from the output signal lines 38, 39, 40, and 41 at the same drive timing. To detect.

  As described above, according to the configuration of FIG. 1, switching is performed for the transfer gates 15, 16, 19, and 20 attached to the PD portions (for example, 1, 2, 5, 6) of a pair of adjacent rows. The readout pulse line 34 for supplying a signal for use is provided in common, whereby each transfer gate is switched, and the charges of the PD portions of a pair of adjacent rows are changed to the FD portions 9, 10, 12, 13 different from each other. , And the generated charges are detected by the pixel amplifiers 25, 26, 27, and 28 provided corresponding to the respective FD units, so that the number of readout wirings per photoelectric conversion cell is reduced and the cell size is reduced. Can contribute to In addition, since pixel signals in a pair of rows are obtained simultaneously on the output signal lines 38, 39, 40, and 41, charges from all the photoelectric conversion cells on the solid-state imaging device can be read out at high speed.

  In addition, the PD portions 2 and 6 in one row of the pair of adjacent rows and the PD portions 3 and 7 in the row adjacent to the one row and not forming the pair. In contrast, since the FD units 10 and 13 and the pixel amplifiers 26 and 28 are provided in common, the number of FD units and the number of pixel amplifiers per photoelectric conversion cell can be reduced.

  Further, pixel amplifiers 25 and 27 using a common drain portion are provided for PD portions (for example, 1 and 5) arranged in the same row and adjacent to each other, and different output signal lines 38 and 41 from the respective pixel amplifiers. Since the charge is detected, the number of drain portions per photoelectric conversion cell can be reduced.

  Specifically, by adopting the circuit configuration of FIG. 1, the number of transistors and the number of wirings per photoelectric conversion cell are 1.75 and 2.75, respectively. For example, when the area of one photoelectric conversion cell is 4.1 μm × 4.1 μm, the aperture ratio of each of the PD portions 1 to 8 is 30% when the design is performed using the 0.35 μm rule.

  Further, since the reset gate 23 for resetting the potential of the FD section (for example, 9 and 12) is further provided, after detecting the signals from the PD sections 1 and 5 by the output signal lines 38 and 41, the pixel amplifier 25, The signal transfer from 27 can be stopped. The reset gate 23 can simultaneously reset the FD units 9 and 12 that transfer charges of the PD units 1 and 5 in the first row. The other reset gate 24 can simultaneously reset the FD units 10 and 13 that transfer charges of the PD units 2, 3, 6, and 7 in the second and third rows.

  In addition, since the regions where the FD portions 9 to 14 and the pixel amplifiers 25 to 28 are provided and the regions where the readout pulse lines 34 and 35 are provided are alternately arranged, the PD portions 1 to 8 are arranged at equal pitches. It becomes easy to arrange and a uniform image is easily obtained.

  3 is a partial cross-sectional view of the solid-state imaging device of FIG. As shown in FIG. 3, the PD portion 1 and the like are formed on the silicon substrate 54, and the gate electrode (polysilicon film) 51 is formed on the gate oxide film 56. Then, the first layer metal wiring 52 and the second layer metal wiring 53 are arranged via the interlayer film 55. Here, the second layer metal wiring 53 functioning as the cell power line 33 also serves as a light shielding film of the FD portions 9 to 14. Thus, if the cell power supply line 33 is formed on a different plane from the output signal lines 38 to 41, the aperture ratio can be further improved. When designed under the same conditions as described above, the aperture ratios of the PD portions 1 to 8 are as high as 32%, leading to an improvement in sensitivity.

  FIG. 4 is a block diagram of a camera module 61 using the solid-state imaging device of FIG. The camera module 61 of FIG. 4 includes a sensor module 62 having the configuration of FIG. 1, a drive circuit 63 that transmits a signal for driving the sensor module 62, and output signal lines 38 to 38 shown in FIG. 1 from the sensor module 62. And a digital signal processor (DSP) 68 for processing a signal read out via the terminal 41. The signal read from the sensor module 62 is temporarily stored in the preprocessing unit 64 of the DSP 68. In the sensor module 62, the memory elements of the same number as the number of pixels in the two rows are provided in the preprocessing portion 64 in order to read out the accumulated charges of the PD portions 1 to 8 every two rows. The output of the preprocessing unit 64 is converted into a color image by the image processing circuit 65 similar to the conventional one, and is replaced by a signal for display on the display by the display processing circuit 66. The media control circuit 67 can store the image of the sensor module 62 on a recording medium.

  As described above, the solid-state imaging device according to the present invention can reduce the number of transistors and the number of wirings per photoelectric conversion cell, and can contribute to miniaturization of the photoelectric conversion cell.

It is a circuit diagram which shows the structural example of the solid-state imaging device which concerns on this invention. It is a wave form diagram which shows the drive timing of the solid-state imaging device of FIG. It is a fragmentary sectional view of the solid-state imaging device of FIG. It is a block diagram of the camera module using the solid-state imaging device of FIG.

Explanation of symbols

1-8 Photodiode (PD) part 9-14 Floating diffusion (FD) part 15-22 Transfer gate 23, 24 Reset gate 25-28 Pixel amplifier 29-32 Load transistor 33 Cell power supply line (VDDCELL)
34, 35 Read pulse line (READ)
36, 37 Reset pulse line (RESET)
38 to 41 Output signal line (VOUT)
42 Load gate line 43 Source power supply line 51 Gate electrode 52 First layer metal wiring 53 Second layer metal wiring (also used as light shielding film)
54 Silicon substrate 55 Interlayer film 56 Gate oxide film 61 Camera module 62 Sensor module 63 Drive circuit 64 Preprocessing unit 65 Image processing circuit 66 Display processing circuit 67 Media control circuit 68 Digital signal processor (DSP)

Claims (7)

A plurality of photoelectric conversion units arranged two-dimensionally, a floating diffusion (FD) unit to which charges of the photoelectric conversion unit are transferred, and a transfer gate for transferring charges of the photoelectric conversion unit to the FD unit; In a solid-state imaging device including a pixel amplifier that detects the potential of the FD unit, and an output signal line that outputs a detection signal of the pixel amplifier,
A readout wiring for supplying a signal for switching the transfer gate is provided in common to the transfer gates respectively attached to the photoelectric conversion units in a pair of adjacent rows, and each transfer is performed through the common readout wiring. By switching the gates, the charges of the photoelectric conversion units in a pair of adjacent rows are transferred to the FD units different from each other, and generated by the pixel amplifiers provided corresponding to the FD units. A solid-state imaging device, wherein the charge is detected. The solid-state imaging device according to claim 1,
The FD unit and the photoelectric conversion unit in one of the pair of adjacent rows and the photoelectric conversion unit in a row that does not form the pair and is adjacent to the one row. A solid-state imaging device characterized in that a pixel amplifier is provided in common. The solid-state imaging device according to claim 1,
A pixel amplifier using a common drain portion is provided for each of the photoelectric conversion units arranged in the same row and adjacent to each other, and a charge is detected from each pixel amplifier to a different output signal line. Imaging device. The solid-state imaging device according to claim 1,
A solid-state imaging device, further comprising reset means for resetting the potential of the FD unit. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a region where the FD portion and the pixel amplifier are provided and a region where the readout wiring is provided are alternately arranged. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a power supply wiring of the pixel amplifier also serves as a light shielding film of the FD portion. The solid-state imaging device according to claim 1,
A solid-state imaging device further comprising a signal processing circuit for processing a signal on the output signal line.

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