JPH0697414A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To limit a thermal noise band generated in a transistor and minimize the thermal noise component simultaneously by installing a filter which limits the bands of an amplifier and a signal for every vertical CCD in order to minimize a frequency band of a signal. CONSTITUTION:Signal charges generated in a photodiode 108 are transferred by a vertical CCD resistor 101 and converted into voltage by a charge detector 102. Then, the frequency band of the signals is limited by a band limiting means 103 and then, a CDS circuit 104 suppresses reset noise generated in the charge detector 102. Then. a signal is selected and output by a row selection means 105 selected by a horizontal scanning circuit 109. As a result, this construction makes it possible to lower the signal band so that it may be possible to narrow the noise band with the band limiting means 103. It is, therefore, possible to provide a solid-state image sensing device with a better S/N ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device using a CCD register, and more particularly to a high sensitivity image pickup device.

[0002]

2. Description of the Related Art There is a strong demand for miniaturization and high resolution of video cameras and the like, so that the optical system of the image pickup device becomes smaller and the number of pixels increases. Therefore, the area of the pixel is reduced, and accordingly, the signal generated in the pixel is reduced. Therefore, in order to secure the same S / N, it is necessary to reduce the generated noise.

In the conventional solid-state image pickup device, charges carried by a vertical CCD are simultaneously transferred to a horizontal CCD for one line and read by one amplifier provided at the end of the horizontal CCD. For example, 1991 ISSCC DIGEST OF TECHNICAL
PAPERS (ISC seaseeding off technical paper)
Examples are those announced in pp208-209.

[0004]

The noise generated in the CCD type solid state image pickup device is dominated by the thermal noise generated in the MOS transistor of the output amplifier. This thermal noise can be expressed by the following equation. V2n = 4kT (2/3) (1 / gm) fB (V2) k is Boltzmann's constant, T is absolute temperature, gm is transconductance, and fB is frequency band. In the conventional method, one pixel detector converts all pixel signals into voltage,
The frequency band of the signal becomes large. Therefore, fB
The frequency band of the amplifier that can be expressed by must also be made larger than that, and the pass component of noise also becomes large.

[0005]

Therefore, in the present invention, in order to reduce the frequency band of the signal, an amplifier and a filter for limiting the band of the signal are provided for each vertical CCD.

[0006]

Since the amplifier is provided for each vertical CCD, the signal is input to the amplifier only once in one horizontal scanning period, and the frequency band of the signal is significantly reduced. Therefore,
The frequency band of the amplifier is limited by using a low pass filter. Accordingly, the band of thermal noise generated in the transistor can be limited at the same time, and the noise component can be reduced.

[0007]

Embodiment 1 First, the configuration will be described with reference to FIG. Where 1
01 is a vertical CCD register, 102 is a charge detector, 10
3 is a band limiting means, 104 is a CDS circuit, 105 is a column selecting means, 106 is a photodiode, 107 is a light receiving section, 10
Reference numeral 8 is an output signal line, and 109 is a horizontal scanning circuit. The present embodiment is characterized in that an amplifier is provided for each line and the signal band is limited.

Next, the overall operation will be described. In this figure, the signal charge generated in the photodiode 108 is
It is transferred by the vertical CCD register 101 and converted into a voltage by the charge detector 102. After that, band limiting means 1
The frequency band of the signal is limited by 03, and then the reset noise generated in the charge detector 102 is suppressed by the CDS circuit 104. Then, the signal is selected and output by the column selecting means 105 selected by the horizontal scanning circuit 109.

Next, the operation will be described with reference to FIG. 2 and FIG. 3, focusing on one line. Here, 21 is a floating diffusion for detecting charges. The signal charge immediately before, which was stored in the gate capacitance of the first-stage source follower at a certain time, is reset by giving a pulse to RG. At this time, the terminal A becomes the reset potential. At point B, the reset potential is fixed with a delay of a time constant determined by the output impedance of the first stage source follower and the band limiting capacitance Cout. When the reset potential is fixed at the point B, a pulse is input to the clamp pulse CLP and the reset potential is clamped. Next, the signal charge is input to the terminal A by the input pulse. Then, the potential of the terminal A decreases by the amount of the signal charge. Then, at the point B, the signal potential is fixed with a delay of the time constant as in the reset. At this time, a pulse is given to the hold pulse HP, and the potential at that time is stored at the point C. C
The potential of the difference between the signal potential and the reset potential is stored at the point. After that, a pulse is applied to the column selection pulse SP (n) and a signal is output to the output signal line 108. In this operation, the time for detecting the signal potential and the time for detecting the reset potential are the same. This is because when the difference between the signal potential and the reset potential is obtained in the CDS circuit in the subsequent stage, the two potentials must be limited in the same band and have the same level of noise components. That is, even if only one of them is a signal with a low noise component, the difference signal has a large noise component.

With such a configuration, the band can be limited by the low-pass filter composed of the output impedance of the first-stage source follower and the band limiting capacitance Cout, so that the noise component contained in the output signal can be reduced. Further, since this circuit has a built-in CDS circuit, it is possible to simultaneously suppress the reset noise generated due to the variation in the potential when the immediately preceding charge is reset. Externally mounted CDS as before
Since it is not necessary to configure a circuit, peripheral circuits can be reduced.

In this configuration, the amplifier may be operated only during the horizontal blanking period. In this case, it is not necessary to apply a pulse such as a reset pulse during the video signal period, so that noise caused by the pulse does not jump into the video signal.

In the above configuration, an amplifier is provided for each vertical CCD, but it goes without saying that one amplifier may be provided for a plurality of vertical CCDs and used in a time division manner. With this configuration,
Since the total number of amplifiers can be reduced, power consumption can be reduced.

Embodiment 2 Next, another embodiment of the present invention will be described with reference to FIG. In this embodiment, the negative feedback amplifier 4 is provided just before the band limiting capacitance 103.
The feature is that 1 is provided. Here, 42 is a feedback resistor and is otherwise the same as FIG. In this circuit, CDS
In the circuit 104 and the column selection means 105, reset noise is generated during the switching operation. In the present embodiment, in order to reduce the effect of this reset noise, amplification is performed by the negative feedback amplifier 41 provided in the previous stage. In this way, if the same reset noise occurs, the signal component becomes large, so the S / N becomes large. Moreover, the output impedance of the amplifier is increased by using a series-series feedback amplifier as the amplification stage. Specifically, without the feedback resistor 42, the output impedance of the amplifier is approximately the load resistance value RL. However, the output impedance becomes RL (1 + gmRF), which is (1 + gmRF) times, by limiting the same band by using the feedback resistor 42 having the value of RF to form a series-series feedback amplifier. The value of the band limiting capacity 103 can be reduced. Further, regarding the voltage gain as well, when the feedback resistor 42 is not provided, it is determined by gmRL, and the variation of gm due to the variation of the channel length affects the variation of the voltage gain. However, by using the feedback resistor 42 as a series-series feedback amplifier, the voltage gain is RL / R when gm is large.
It is determined by F, and the variation in voltage gain between columns can be reduced.

The above is a case of using a floating diffusion, but a floating gate (197391 ISSCC DIGEST OF TECHNICAL PAPERS pp154 to 15)
It is also possible to use (see 5). When the floating gate is used, a signal in which the DC component is cut can be obtained, so that the operating point can be easily brought to around half the power supply voltage in the amplifier at the next stage. Therefore, it is possible to obtain a dynamic range that maximizes the power supply voltage.

Embodiment 3 Another embodiment of the present invention will be described with reference to FIG.
The present embodiment is characterized in that the two band limiting capacitors 103 and 53 are used to limit the band of the signal component and the reset noise component separately. Here, 51 is a signal component selection MOS transistor, 52 is a reset noise component selection MOS transistor, 53 is a reset noise component band limiting capacitance, 54
Is a column noise selection MOS transistor for reset noise component,
Others are the same as in FIG. In the operation of the first embodiment, the terminal
When a signal component is input to A, the signal component selection MOS
When the transistor 51 is turned on and the reset noise component is input to the terminal A, the reset noise component selection MOS transistor 52 is turned on. Then, the signal component is accumulated in the signal component band limiting capacitor 103, and the reset noise component is accumulated in the reset noise component band limiting capacitor 53. And
When a column is selected, reset noise component column selection MOS transistor 54 and signal component column selection MOS transistor 1
05 are turned on in order. Then, the reset noise component and the signal component are sequentially output to the output signal line and input to the external CDS circuit.

The noise generated in the CDS circuit depends on the clamp capacitance CL and the hold capacitance Ch shown in FIG. If these capacitances are made as large as possible, the noise generated will be small. In this embodiment, the reset noise component and the signal component are sequentially output, so that CDS can be externally applied. By applying CDS externally, the values of the clamp capacitance CL and the hold capacitance Ch can be increased, so that the noise generated in the CDS circuit can be reduced.

Embodiment 4 Another embodiment of the present invention will be described with reference to FIGS. 6 and 9. The present embodiment is characterized in that light-shielding aluminum is used as the band limiting capacity. Here, 61 in FIG. 6 is a band limiting capacity, and the others are the same as in FIG. In FIG. 9, 91 is an n-type semiconductor substrate, 92 is a p-type well, 93 is an n-type layer forming a photodiode, and 94 is VCC.
A dark p-type well for D, 95 forms an embedded CCD
A mold layer, 96 is an electrode constituting a CCD, and 97 is a light-shielding aluminum. In order to reduce noise, it is necessary to narrow the bandwidth. For that purpose, a large value is required for the band limiting capacity. Therefore, the light-shielding aluminum 97 and the vertical CCD electrodes 9 covering the vertical CCDs in each column in FIG.
The capacitance formed between 6 is used. This area can be represented by 61 in FIG. In this way, the capacitance can be formed in a wide area without increasing the chip area. The above is the case where the capacitor is formed by using the light-shielding aluminum 97 and the vertical CCD electrode 96. Of course, as shown in FIG. 10, the capacitor-forming electrode 2 is further formed on the light-shielding aluminum.
01 may be provided. When tantalum oxide having a large dielectric constant is used as the interlayer film, a large capacitance can be obtained, and the frequency band can be limited and noise can be reduced accordingly.

Embodiment 5 Another embodiment of the present invention will be described with reference to FIG.
The present embodiment is characterized in that the band limiting capacitance is provided after the charge detector. Here, 81 is an amplifier, and the others are shown in FIG.
Is the same as. In such a configuration, the noise generated in the CDS circuit 104 and the column selection means 105 is
Therefore, it looks small, and the output impedance of the charge detector 102 and the band limiting capacitance 103 form a low-pass filter. Therefore, the noise component is limited by this filter, and the noise generated in the feedback resistor 42 is eliminated, so that the noise can be further reduced.

Embodiment 6 Another embodiment of the present invention will be described with reference to FIG.
The present embodiment is characterized in that the voltage generating means 71 is provided on the light-shielding aluminum forming the capacitor via the MOS switch 72. In order to obtain a larger capacitance, the film thickness between the light-shielding aluminum 97 and the vertical CCD electrode 96 running thereunder in FIG. 9 should be thin. However, the vertical CCD electrode 96 has an amplitude when reading a signal from a photodiode, for example.
Since a pulse of 15 (V) is applied, if the film thickness is too thin, the breakdown voltage will be exceeded. An appropriate potential is applied to the point B before the signal reading pulse is applied by using the voltage generating means 71. As a result, the voltage between the light-shielding aluminum 97 and the vertical CCD electrode 96 running thereunder becomes relatively small. Therefore, the film thickness can be reduced, and thus a large capacity can be obtained.

[0020]

Since the signal band can be lowered by the structure of the present invention, the noise band can be narrowed by the band limiting means, and a solid-state image pickup device having a good S / N ratio can be realized.

[0021]

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of the present invention.

FIG. 2 is a circuit diagram of one line.

FIG. 3 is a timing chart explaining the operation.

FIG. 4 is a diagram illustrating another embodiment in which a feedback amplifier is provided.

FIG. 5 is a diagram illustrating another embodiment that outputs both a signal potential and a reset potential.

FIG. 6 is an explanatory diagram for realizing a band limiting capacity by using light-shielding aluminum.

FIG. 7 is a diagram illustrating an embodiment in which a potential is applied to the band limiting capacitance in advance.

FIG. 8 is a diagram illustrating another embodiment.

FIG. 9 is a diagram illustrating a band limiting capacity.

FIG. 10 is a diagram for explaining another embodiment of the band limiting capacity.

[Explanation of symbols]

101-vertical CCD register, 102-charge detector, 1
03-Band limiting means 104-CDS circuit, 105-Column selecting means, 106-Photodiode 107-Light receiving part, 108-Output signal line, 109-Horizontal scanning circuit

Front Page Continuation (72) Hajime Akimoto Hajime Akimoto 1-280 Higashi Koigokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory

Claims (16)

[Claims] 1. A photoelectric conversion means formed two-dimensionally on a semiconductor substrate, a vertical CCD register formed adjacent to the plurality of photoelectric conversion means, and a charge detector provided for each CCD register. A solid-state image pickup device comprising: 2. The solid-state image pickup device according to claim 1, wherein a means for limiting a band is provided at an output end of the charge detector. 3. The solid-state imaging device according to claim 2, wherein the band limiting means is a capacitor provided at an output end of the charge detector. 4. The solid-state imaging device according to claim 3, wherein the capacitor uses the light shielding film on each of the vertical CCD registers as a first electrode. 5. The solid-state imaging device according to claim 3, wherein the capacitor has a second electrode formed above or below a light-shielding film formation region on each CCD register. 6. The solid-state imaging device according to claim 4, wherein the capacitor uses tantalum oxide between electrodes of the capacitor. 7. The method according to claim 4, wherein one electrode different from the electrode of the capacitor to which the signal voltage from the vertical CCD is applied is applied so that the voltage between the electrodes becomes small.
The solid-state imaging device according to. 8. The solid-state imaging device according to claim 1, further comprising a charge detection unit provided for each of the plurality of CCD registers. 9. The solid-state image pickup device according to claim 1, further comprising differential means for detecting a difference between an output when there is no signal and an output when there is a signal for each output amplifier of each column. . 10. The solid-state image pickup device according to claim 9, further comprising an amplifying means provided between the charge detector and the differential means. 11. The solid-state imaging device according to claim 10, wherein the amplifying means is a negative feedback amplifier. 12. The solid-state imaging device according to claim 9, wherein the output when there is no signal and the output when there is a signal are alternately output with the frequency bands limited by different band limiting means. 13. The solid-state image pickup device according to claim 1, wherein the charge detector comprises a floating gate. 14. The solid-state imaging device according to claim 1, wherein the charge detector is operated only during a horizontal synchronization period. 15. The solid-state imaging device according to claim 1, wherein in the charge detector, half of the horizontal scanning period is used as a feedthrough level detecting operation and the other half is used as a signal level detecting operation. 16. The solid-state imaging device according to claim 1, wherein horizontal scanning is performed by a shift register.