JP4526125B2 - 大電力用半導体装置 - Google Patents
大電力用半導体装置 Download PDFInfo
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- JP4526125B2 JP4526125B2 JP2005260034A JP2005260034A JP4526125B2 JP 4526125 B2 JP4526125 B2 JP 4526125B2 JP 2005260034 A JP2005260034 A JP 2005260034A JP 2005260034 A JP2005260034 A JP 2005260034A JP 4526125 B2 JP4526125 B2 JP 4526125B2
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- external lead
- out terminal
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- epoxy resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
DBC基板の上面の第1領域を介して前記半導体素子の下面に電気的に接続された第1外部導出端子と、
前記DBC基板の上面の第2領域と接続部材とを介して前記半導体素子の上面に電気的に接続された第2外部導出端子と、
前記DBC基板を支持する放熱板と、
外囲ケースと、
蓋と、
前記外囲ケースの内側の下側部分に配置されたゲル状充填材層と、
前記外囲ケースの内側の上側部分に配置されたエポキシ樹脂層とを具備する大電力用半導体装置において、
前記第1外部導出端子および前記第2外部導出端子のそれぞれに凸部を形成し、
前記凸部を前記エポキシ樹脂層内に配置し、
前記蓋を前記凸部の上面に突き当てることにより、前記蓋を位置決めすることを特徴とする大電力用半導体装置が提供される。
2 DBC基板
2a 第1領域
2b 第2領域
3 第1外部導出端子
3a 凸部
4 ジャンパープレート
5 第2外部導出端子
5a 凸部
6 放熱板
7 外囲ケース
8 蓋
9 ゲル状充填材層
10 エポキシ樹脂層
11 空気層
12 バルフロン線
Claims (7)
- 半導体素子と、
DBC基板の上面の第1領域を介して前記半導体素子の下面に電気的に接続された第1外部導出端子と、
前記DBC基板の上面の第2領域と接続部材とを介して前記半導体素子の上面に電気的に接続された第2外部導出端子と、
前記DBC基板を支持する放熱板と、
外囲ケースと、
蓋と、
前記外囲ケースの内側の下側部分に配置されたゲル状充填材層と、
前記外囲ケースの内側の上側部分に配置されたエポキシ樹脂層とを具備する大電力用半導体装置において、
前記第1外部導出端子および前記第2外部導出端子のそれぞれに凸部を形成し、
前記凸部を前記エポキシ樹脂層内に配置し、
前記蓋を前記凸部の上面に突き当てることにより、前記蓋を位置決めすることを特徴とする大電力用半導体装置。 - 前記第1外部導出端子の一部および前記第2外部導出端子の一部を折り曲げることにより前記凸部を形成したことを特徴とする請求項1に記載の大電力用半導体装置。
- 前記第1外部導出端子および前記第2外部導出端子の前記凸部以外の部分の外縁よりも外側に突出するように前記凸部を形成したことを特徴とする請求項1に記載の大電力用半導体装置。
- 前記第1外部導出端子の上端および前記第2外部導出端子の上端を折り曲げることにより、前記蓋を前記凸部の上面に突き当てることを特徴とする請求項1〜3のいずれか一項に記載の大電力用半導体装置。
- 前記外囲ケース上に前記蓋を載置する前にエポキシ樹脂を注入し、エポキシ樹脂が硬化する前に前記蓋を前記凸部の上面に突き当てることを特徴とする請求項1〜4のいずれか一項に記載の大電力用半導体装置。
- 前記蓋の下面と前記エポキシ樹脂層の上面との間に空気層を配置したことを特徴とする請求項1〜5のいずれか一項に記載の大電力用半導体装置。
- 前記蓋の下面のうち、前記凸部の上面に突き当てられる部分のみを前記エポキシ樹脂層と接触させたことを特徴とする請求項1〜6のいずれか一項に記載の大電力用半導体装置。
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JP2005260034A JP4526125B2 (ja) | 2005-09-08 | 2005-09-08 | 大電力用半導体装置 |
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JP2005260034A JP4526125B2 (ja) | 2005-09-08 | 2005-09-08 | 大電力用半導体装置 |
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JP2007073782A JP2007073782A (ja) | 2007-03-22 |
JP4526125B2 true JP4526125B2 (ja) | 2010-08-18 |
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Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4840314B2 (ja) * | 2007-09-26 | 2011-12-21 | 三菱電機株式会社 | 電力半導体モジュール |
JP5467933B2 (ja) | 2010-05-21 | 2014-04-09 | 株式会社東芝 | 半導体装置 |
JP5626472B2 (ja) * | 2011-07-28 | 2014-11-19 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP5659171B2 (ja) * | 2012-02-23 | 2015-01-28 | 株式会社 日立パワーデバイス | 半導体装置およびそれを用いたインバータ装置 |
JP5377733B2 (ja) * | 2012-09-21 | 2013-12-25 | 三菱電機株式会社 | 電力用半導体装置 |
JP6825306B2 (ja) * | 2016-11-02 | 2021-02-03 | 富士電機株式会社 | 半導体装置 |
JP2020141010A (ja) * | 2019-02-27 | 2020-09-03 | 株式会社豊田自動織機 | 半導体装置 |
JP7244339B2 (ja) * | 2019-04-19 | 2023-03-22 | 株式会社三社電機製作所 | 半導体モジュール用外部端子 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04206554A (ja) * | 1990-11-30 | 1992-07-28 | Hitachi Ltd | 半導体装置 |
JPH0738014A (ja) * | 1993-07-20 | 1995-02-07 | Fuji Electric Co Ltd | 半導体装置用基板 |
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- 2005-09-08 JP JP2005260034A patent/JP4526125B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04206554A (ja) * | 1990-11-30 | 1992-07-28 | Hitachi Ltd | 半導体装置 |
JPH0738014A (ja) * | 1993-07-20 | 1995-02-07 | Fuji Electric Co Ltd | 半導体装置用基板 |
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