JP4492679B2 - Power supply circuit, display driver, electro-optical device, and electronic device - Google Patents

Description

The present invention includes a power supply circuit, relates to a display driver, an electro-optical device and an electronic apparatus.

  Conventionally, as a liquid crystal display (LCD) panel (display panel in a broad sense) used in an electronic device such as a mobile phone, a simple matrix type LCD panel and a thin film transistor (hereinafter referred to as TFT) are used. An active matrix type LCD panel using a switch element such as (abbreviated) is known.

  The simple matrix method is easier to reduce power consumption than the active matrix method, but it is difficult to increase the number of colors and display a moving image. On the other hand, the active matrix method is suitable for multicolor and moving image display, but it is difficult to reduce power consumption.

  In recent years, in portable electronic devices such as mobile phones, there is an increasing demand for multi-color display and moving image display in order to provide high-quality images. For this reason, an active matrix LCD panel has been used in place of the simple matrix LCD panel that has been used so far.

  A simple matrix LCD panel or an active matrix LCD panel is driven so that the voltage applied to the liquid crystal constituting the pixel is an alternating current. As such AC driving methods, line inversion driving and field inversion driving (frame inversion driving) are known. In line inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted every one or more scanning lines. In the field inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted for each field (for each frame).

At that time, the voltage level applied to the pixel electrode is lowered by changing the counter electrode voltage (common voltage) supplied to the counter electrode (common electrode) facing the pixel electrode constituting the pixel in accordance with the inversion drive timing. Can be made.
JP 2004-184840 A

  However, the load on the counter electrode of the LCD panel is almost constant, and the power supply capability of the power supply circuit that supplies the counter electrode voltage is determined in consideration of the maximum amount of charge to be charged and discharged. For this reason, even when the power supply capability is unnecessary, a wasteful current is generated.

  In recent years, there has been a demand for higher resolution and higher gradation of LCD panels. Therefore, high accuracy and high driving capability are required, and more current must be consumed. Therefore, even a slight change in the voltage level affects the image quality of the LCD panel, and for example, the problem of lateral crosstalk has begun to occur.

  Further, with the increase in the number of gradations of the LCD panel, the gradation characteristics according to the LCD panel are diversified, and it is increasingly complicated to display a desired image. It is an important issue to display a desired image in accordance with such diversified gradation characteristics.

  The present invention has been made in view of the technical problems as described above, and an object thereof is to supply a voltage to the counter electrode according to the gradation characteristics without affecting the image quality with low power consumption. A power supply circuit, a display driver, an electro-optical device, an electronic apparatus, and a control method for the power supply circuit are provided.

In order to solve the above problems, the present invention
A power supply circuit for supplying a voltage to a counter electrode facing a pixel electrode with an electro-optic material interposed therebetween,
A high potential side voltage generating circuit for generating a high potential side voltage to be supplied to the counter electrode;
A low potential side voltage generation circuit for generating a low potential side voltage to be supplied to the counter electrode;
A switching circuit that alternately supplies one of the high potential side voltage and the low potential side voltage as a counter electrode voltage to the counter electrode,
The current drive capability of the high potential side voltage generation circuit according to the sum value generated based on the gradation data of the number of dots of one scanning line corresponding to the applied voltage of the pixel electrode. The counter electrode voltage supply capability for changing at least one of the output voltage level of the high potential side voltage generation circuit, the current drive capability of the low potential side voltage generation circuit, and the output voltage level of the low potential side voltage generation circuit Control
The total value is
The present invention relates to a power supply circuit that is a value obtained by sequentially adding the converted voltage values obtained by converting the grayscale data corresponding to the number of dots of one scanning line according to the given grayscale characteristics.

  In the present invention, the counter electrode to which a voltage is supplied is capacitively coupled to the pixel electrode. Then, the transmittance is changed according to the voltage between the counter electrode and the pixel electrode. For this reason, when the number of gradations increases, the voltage variation between the counter electrode and the pixel electrode affects the image quality.

  In the present invention, at least one of the current driving capability and the output voltage level for supplying the high potential side voltage and the low potential side voltage of the counter electrode voltage is changed. Then, focusing on the fact that the total value obtained by sequentially adding the converted voltage values obtained by converting each of the gradation data for the number of dots of one scanning line according to the gradation characteristics can be related to the applied voltage of the pixel electrode, One of these is controlled in accordance with the total value. Therefore, it is not necessary to determine the voltage supply capability of the counter electrode in consideration of the maximum value of the amount of charge to be charged / discharged by the counter electrode. Therefore, according to the present invention, wasteful power is not consumed even though the voltage supply capability is not so much required. Accordingly, it is possible to provide a power supply circuit that can set the voltage of the counter electrode with low power consumption and high accuracy according to the gradation characteristics.

In the power supply circuit according to the present invention,
A first auxiliary transistor of a first conductivity type, the source of which is supplied with the high-potential-side power supply voltage of the high-potential-side voltage generation circuit and the drain of which is electrically connected to the output of the switching circuit;
The supply capacity control can be performed by controlling the gate voltage of the first auxiliary transistor according to the total value.

  According to the present invention, the ability to set the high-potential-side voltage of the counter electrode voltage can be increased according to the total value, and wasteful current consumption can be reduced.

In the power supply circuit according to the present invention,
A second auxiliary transistor of a second conductivity type, the source of which is supplied with the low-potential-side power supply voltage of the low-potential-side voltage generation circuit and the drain of which is electrically connected to the output of the switching circuit;
The supply capability can be controlled by controlling the gate voltage of the second auxiliary transistor in accordance with the total value.

  According to the present invention, the ability to set the low-potential-side voltage of the counter electrode voltage can be increased according to the total value, and wasteful current consumption can be reduced.

In the power supply circuit according to the present invention,
The high potential side voltage generating circuit is
A first operational amplifier that outputs the high potential side voltage based on a high potential side input voltage can be included.

In the power supply circuit according to the present invention,
The supply capability control can be performed by changing at least one of the current driving capability and the slew rate of the first operational amplifier in accordance with the total value.

In the power supply circuit according to the present invention,
The supply capability control can be performed by changing the high-potential side input voltage according to the total value.

In the power supply circuit according to the present invention,
According to the sum value, the operating current of the first operational amplifier is stopped or limited, and the supply capacity control can be performed by electrically connecting the input and output of the first operational amplifier. .

  According to any one of the inventions described above, the ability to generate the high-potential-side voltage of the counter electrode voltage can be changed according to the total value, and wasteful current consumption can be reduced.

In the power supply circuit according to the present invention,
Including a first charge pump circuit that generates a high-potential-side power supply voltage of the high-potential-side voltage generation circuit by a charge pump operation synchronized with a first charge clock;
The supply capacity control can be performed by stopping the first charge clock or reducing the frequency thereof according to the total value.

  According to the present invention, since the high-potential side power supply voltage with high accuracy can be generated by consuming power only when the accuracy of the voltage level of the high-potential side power supply voltage is necessary, wasteful current consumption can be reduced.

In the power supply circuit according to the present invention,
The low potential side voltage generating circuit is
A second operational amplifier that outputs the low potential side voltage based on the low potential side input voltage can be included.

In the power supply circuit according to the present invention,
The supply capability control can be performed by changing at least one of the current driving capability and the slew rate of the second operational amplifier according to the total value.

In the power supply circuit according to the present invention,
The supply capability control can be performed by changing the low potential side input voltage in accordance with the total value.

In the power supply circuit according to the present invention,
According to the total value, the operating current of the second operational amplifier is stopped or limited, and the supply capacity control can be performed by electrically connecting the input and output of the second operational amplifier. .

  According to any one of the above inventions, the ability to generate the low-potential-side voltage of the counter electrode voltage can be changed according to the total value, and wasteful current consumption can be reduced.

In the power supply circuit according to the present invention,
A second charge pump circuit that generates a low potential side power supply voltage of the low potential side voltage generation circuit by a charge pump operation synchronized with a second charge clock;
The supply capacity control can be performed by stopping the second charge clock or reducing the frequency thereof according to the sum value.

  According to the present invention, power can be consumed only when accuracy of the voltage level of the low-potential-side power supply voltage is required, and a highly accurate low-potential-side power supply voltage can be generated, so that wasteful current consumption can be reduced.

The present invention also provides
A power supply circuit for supplying a voltage to a counter electrode facing a pixel electrode with an electro-optic material interposed therebetween,
A circuit for alternately supplying one of a high-potential side voltage and a low-potential side voltage to the counter electrode;
The current drive capability of the high potential side voltage generation circuit according to the sum value generated based on the gradation data of the number of dots of one scanning line corresponding to the applied voltage of the pixel electrode. The counter electrode voltage supply capability for changing at least one of the output voltage level of the high potential side voltage generation circuit, the current drive capability of the low potential side voltage generation circuit, and the output voltage level of the low potential side voltage generation circuit Control
The total value is
The present invention relates to a power supply circuit that is a value obtained by sequentially adding the converted voltage values obtained by converting the grayscale data corresponding to the number of dots of one scanning line according to the given grayscale characteristics.

  In the present invention, the total value obtained by sequentially adding the converted voltage values obtained by converting each of the gradation data for the number of dots of one scanning line according to the gradation characteristics can be associated with the applied voltage of the pixel electrode. Paying attention, the supply capability of the counter electrode voltage is controlled according to the total value. This eliminates the need to determine the voltage supply capability of the counter electrode in consideration of the maximum value of the amount of charge to be charged / discharged by the counter electrode. Therefore, wasteful power is not consumed even though the voltage supply capability is not so much required. Therefore, it is possible to provide a power supply circuit that can set the voltage of the counter electrode with low power consumption and high accuracy according to the gradation characteristics.

In the power supply circuit according to the present invention,
The supply capacity control can be performed only during a period determined based on the total value.

In the power supply circuit according to the present invention,
Instead of the total value, the supply capability control can be performed according to the change in the total value of the horizontal scanning period with respect to the total value of the immediately preceding horizontal scanning period.

In the power supply circuit according to the present invention,
The supply capability control can be performed only during a period corresponding to a change in the total value of the horizontal scanning period with respect to the total value of the immediately preceding horizontal scanning period.

In the power supply circuit according to the present invention,
When performing field inversion driving for switching the polarity of the counter electrode voltage with respect to a given reference potential for each vertical scanning period,
The change amount is obtained based on a value obtained by subtracting the total value of the immediately preceding horizontal scanning period from the total value of the horizontal scanning period.
When performing line inversion driving for switching the voltage polarity of the counter electrode with respect to a given reference potential every horizontal scanning period,
The amount of change may be obtained based on a value obtained by adding a correction value corresponding to the total value to the total value of the horizontal scanning period.

  ADVANTAGE OF THE INVENTION According to this invention, the power supply circuit which can drive a counter electrode with the optimal voltage supply capability according to the kind of polarity inversion drive can be provided.

In the power supply circuit according to the present invention,
When the gradation data of each dot is j (j is an integer of 2 or more) bits,
The total value is
Each conversion voltage value obtained by converting the upper k (k <j, k is a natural number) bit data of gradation data corresponding to the number of dots of one scanning line according to given gradation characteristics is sequentially added. It may be a value.

  In the power supply circuit according to the present invention, k may be 1.

In the power supply circuit according to the present invention,
When the value obtained by sequentially adding the conversion voltage values is p (p is an integer of 2 or more) bits,
The total value is
A value represented by upper q (q <p, q is a natural number) bits of a value obtained by sequentially adding the converted gradation data may be used.

  According to the above-described invention, the load on the counter electrode can be evaluated by the total value obtained with a simpler configuration. Therefore, it is possible to provide a power supply circuit that reduces power consumption while suppressing an increase in scale.

In the power supply circuit according to the present invention,
The number of bits of the gradation data may be smaller than the number of bits of data representing the converted voltage value.

  According to the present invention, since the conversion voltage value can be specified more finely, the conversion voltage value can be accurately aligned with the gradation characteristics. Then, the supply control of the counter electrode voltage can be performed using the conversion voltage value set with high accuracy.

The present invention also provides
A voltage value conversion circuit that generates a conversion voltage value obtained by converting gradation data of each dot corresponding to the applied voltage of the pixel electrode according to a given gradation characteristic;
A total value calculation circuit that generates the total value based on the converted voltage value for the number of dots of one scanning line;
A driving circuit for supplying a driving voltage corresponding to the gradation data to a data line electrically connected to the pixel electrode;
The present invention relates to a display driver including the power supply circuit according to any one of the above, which performs the supply capacity control using the total value generated by the total value calculation circuit.

  According to the present invention, it is possible to provide a display driver including a power supply circuit that supplies a voltage to the counter electrode according to the gradation characteristics without affecting the image quality with low power consumption.

The present invention also provides
A plurality of scan lines;
Multiple data lines,
A plurality of pixel electrodes each of which is specified by one of the plurality of scanning lines and one of the plurality of data lines;
A counter electrode opposed to the plurality of pixel electrodes with an electro-optic material interposed therebetween;
A display driver for driving the plurality of data lines;
The present invention relates to an electro-optical device including the power supply circuit according to any one of the above, which alternately supplies the high potential side voltage and the low potential side voltage to the counter electrode.

  According to the present invention, it is possible to provide an electro-optical device including a power supply circuit that supplies a voltage to the counter electrode according to gradation characteristics without affecting the image quality with low power consumption.

The present invention also provides
The present invention relates to an electronic device including any one of the power supply circuits described above.

  According to the present invention, it is possible to provide an electronic apparatus including a power supply circuit that supplies a voltage to the counter electrode according to the gradation characteristics without affecting the image quality with low power consumption.

The present invention also provides
A high-potential-side voltage generation circuit that generates a high-potential-side voltage to be supplied to a counter electrode facing the pixel electrode with an electro-optic material interposed therebetween;
A control method of a power supply circuit including a low potential side voltage generating circuit for generating a low potential side voltage to be supplied to the counter electrode,
The gradation data of each dot is converted into gradation voltage data corresponding to the number of dots of one scanning line corresponding to the applied voltage of the pixel electrode, and converted into converted voltage values according to given gradation characteristics.
According to the total value obtained by sequentially adding the converted voltage values, the current drive capability of the high potential side voltage generation circuit, the output voltage level of the high potential side voltage generation circuit, and the current drive capability of the low potential side voltage generation circuit And changing at least one of the output voltage levels of the low-side voltage generation circuit,
The present invention relates to a control method of a power supply circuit that alternately supplies one of the high potential side voltage and the low potential side voltage to the counter electrode.

In the control method of the power supply circuit according to the present invention,
At least one of the current drive capability of the high potential side voltage generation circuit, the output voltage level of the high potential side voltage generation circuit, the current drive capability of the low potential side voltage generation circuit, and the output voltage level of the low potential side voltage generation circuit Can be controlled to change only for a period determined based on the total value.

In the control method of the power supply circuit according to the present invention,
At least one of the current drive capability of the high potential side voltage generation circuit, the output voltage level of the high potential side voltage generation circuit, the current drive capability of the low potential side voltage generation circuit, and the output voltage level of the low potential side voltage generation circuit Can be controlled in accordance with the change in the total value of the horizontal scanning period with respect to the total value of the immediately preceding horizontal scanning period.

In the control method of the power supply circuit according to the present invention,
At least one of the current drive capability of the high potential side voltage generation circuit, the output voltage level of the high potential side voltage generation circuit, the current drive capability of the low potential side voltage generation circuit, and the output voltage level of the low potential side voltage generation circuit It is possible to perform control so as to change only one period corresponding to a change in the total value of the horizontal scanning period with respect to the total value of the immediately preceding horizontal scanning period.

In the control method of the power supply circuit according to the present invention,
When performing field inversion driving for switching the polarity of the voltage of the counter electrode with respect to a given reference potential every vertical scanning period,
The change amount is obtained based on a value obtained by subtracting the total value of the immediately preceding horizontal scanning period from the total value of the horizontal scanning period.
When performing line inversion driving for switching the polarity of the voltage of the counter electrode with respect to a given reference potential every one or a plurality of horizontal scanning periods,
The amount of change may be obtained based on a value obtained by adding a correction value corresponding to the total value to the total value of the horizontal scanning period.

In the control method of the power supply circuit according to the present invention,
When the gradation data of each dot is j (j is an integer of 2 or more) bits,
The total value is
Each conversion voltage value obtained by converting the upper k (k <j, k is a natural number) bit data of gradation data corresponding to the number of dots of one scanning line according to given gradation characteristics is sequentially added. It may be a value.

  In the method for controlling a power supply circuit according to the present invention, k may be 1.

In the control method of the power supply circuit according to the present invention,
When the value obtained by sequentially adding the conversion voltage values is p (p is an integer of 2 or more) bits,
The total value is
A value represented by upper q (q <p, q is a natural number) bits of a value obtained by sequentially adding the converted gradation data may be used.

In the control method of the power supply circuit according to the present invention,
The number of bits of the gradation data may be smaller than the number of bits of data representing the converted voltage value.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Display Device FIG. 1 shows an outline of the configuration of an active matrix liquid crystal display device to which a power supply circuit according to this embodiment is applied.

  The liquid crystal display device 10 includes an LCD panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The LCD panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of scanning lines (gate lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a plurality of data lines arranged in the X direction and extending in the Y direction, respectively. (Source line) DL1 to DLN (N is an integer of 2 or more) are arranged. Also, the pixel region corresponds to the intersection position of the scanning line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the data line DLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the scanning line GLm. The source of the TFT 22mn is connected to the data line DLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal (electro-optical material in a broad sense) is sealed between the pixel electrode 26 mn and a counter electrode 28 mn (counter electrode COM) facing the pixel electrode 26 mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24 mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage VCOM is supplied to the counter electrode 28mn.

  Such an LCD panel 20 includes, for example, a first substrate on which a pixel electrode and a TFT are formed and a second substrate on which a counter electrode is formed, and a liquid crystal as an electro-optical material is interposed between the two substrates. It is formed by enclosing.

  The liquid crystal display device 10 includes a data driver (display driver in a broad sense) 30. The data driver 30 drives the data lines DL1 to DLN of the LCD panel 20 based on the gradation data.

  The liquid crystal display device 10 can include a gate driver (display driver in a broad sense) 32. The gate driver 32 sequentially drives (scans) the scanning lines GL1 to GLM of the LCD panel 20 within one vertical scanning period.

  The liquid crystal display device 10 includes a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the data lines and supplies them to the data driver 30. The power supply circuit 100 generates, for example, power supply voltages VDD and VSS necessary for driving a data line of the data driver 30 and a voltage of a logic unit of the data driver 30. The power supply circuit 100 generates a voltage necessary for scanning the scanning line and supplies it to the gate driver 32.

  Further, the power supply circuit 100 generates a counter electrode voltage VCOM. That is, the power supply circuit 100 generates the counter electrode voltage VCOM at which the high potential side voltage VCOMH and the low potential side voltage VCOML are alternately switched in accordance with the timing of the polarity inversion signal POL generated by the data driver 30. Output to the counter electrode (common electrode). The counter electrode of each pixel has the same potential, for example, and is shown as the counter electrode COM in FIG.

  The liquid crystal display device 10 can include a display controller 38. The display controller 38 controls the data driver 30, the gate driver 32, and the power supply circuit 100 according to the contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 performs operation mode setting, polarity inversion driving setting, polarity inversion timing setting, and internally generated vertical synchronization signal and horizontal synchronization signal to the data driver 30 and the gate driver 32.

  In FIG. 1, the liquid crystal display device 10 is configured to include the power supply circuit 100 or the display controller 38, but at least one of these may be provided outside the liquid crystal display device 10. Good. Alternatively, the liquid crystal display device 10 may be configured to include a host.

  The data driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the data driver 30, the gate driver 32, the display controller 38, and the power supply circuit 100 may be formed on a glass substrate on which the LCD panel 20 is formed. For example, in FIG. 2, the data driver 30, the gate driver 32, and the power supply circuit 100 are formed on the LCD panel 20. As described above, the LCD panel 20 includes a plurality of scanning lines, a plurality of data lines, a pixel electrode specified by one of the plurality of scanning lines and one of the plurality of data lines, and a pixel electrode sandwiching the electro-optic material. And a counter driver that scans a plurality of scan lines, a data driver that drives a plurality of data lines, and a power supply circuit that supplies a counter electrode voltage to the counter electrode. . A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

1.1 Polarity Inversion Driving Method By the way, when driving a liquid crystal, it is necessary to periodically discharge the charge accumulated in the liquid crystal capacitor from the viewpoint of durability and contrast of the liquid crystal. Therefore, in the liquid crystal display device 10, the polarity of the voltage applied to the liquid crystal is reversed at a given period by polarity inversion driving. The polarity inversion driving method includes, for example, field inversion driving and line inversion driving according to the type of polarity inversion cycle.

  The field inversion driving is a method for inverting the polarity of the voltage applied to the liquid crystal for each field (every vertical scanning period). On the other hand, the line inversion driving is a method of inverting the polarity of the voltage applied to the liquid crystal for each line (for one horizontal scanning period or for each of a plurality of horizontal scanning periods). In the case of line inversion driving, if attention is paid to each line, the polarity of the voltage applied to the liquid crystal in the frame period is also inverted.

  3A and 3B are diagrams for explaining the operation of field inversion driving. FIG. 3A schematically shows waveforms of the data line supply voltage and the counter electrode voltage VCOM by field inversion driving. FIG. 3B schematically shows the polarity of the voltage applied to the liquid crystal corresponding to each pixel in one vertical scanning period when field inversion driving is performed.

  In the field inversion driving, as shown in FIG. 3A, the polarity of the voltage supplied to the data line is inverted every vertical scanning period. That is, the voltage Vs supplied to the source of the TFT connected to the data line is “+ V” in the frame f1 and “−V” in the subsequent frame f2. On the other hand, the counter electrode voltage VCOM supplied to the counter electrode facing the pixel electrode connected to the drain electrode of the TFT is also inverted in synchronization with the polarity inversion timing of the data line supply voltage.

  Since the voltage difference between the pixel electrode and the counter electrode is applied to the liquid crystal, the polarity of the voltage is inverted between the frame f1 and the frame f2, as shown in FIG.

  4A and 4B are diagrams for explaining the operation of line inversion driving. FIG. 4A schematically shows waveforms of the data line supply voltage and the counter electrode voltage VCOM by line inversion driving. FIG. 4B schematically shows the polarity of the voltage applied to the liquid crystal corresponding to each pixel for each vertical scanning period when line inversion driving is performed.

  In the line inversion driving, as shown in FIG. 4A, the polarity of the voltage supplied to the data line is inverted every horizontal scanning period (1H) and every vertical scanning period. That is, the voltage Vs supplied to the source of the TFT connected to the data line becomes “+ V” in 1H (one horizontal scanning period) of the frame f1, and becomes “−V” in the next 1H.

  3A and 4A, inversion of the voltage applied to the liquid crystal is realized by common inversion driving that changes the voltage level of the common electrode voltage VCOM.

  FIG. 5 shows a detailed explanatory diagram when line inversion driving and common inversion driving are used in combination.

  In FIG. 5, for example, a positive voltage is applied to the liquid crystal element in the mth scanning period (selection period of the scanning line GLm), and a negative voltage is applied in the (m + 1) th scanning period. ) During the scanning period, a positive voltage is applied. On the other hand, in the next frame, a negative voltage is applied to the liquid crystal element in the mth scanning period, a positive voltage is applied in the (m + 1) th scanning period, and the (m + 2) th scanning is performed. During the period, a negative polarity voltage is applied. In this line inversion driving, the voltage (common voltage) VCOM of the counter electrode COM is inverted every scanning period.

  More specifically, the common electrode voltage VCOM becomes the high potential side voltage VCOMH in the positive period T1 (first period), and becomes the low potential side voltage VCOML in the negative period T2 (second period).

  Here, the positive period T1 is a period in which the voltage Vs of the data line (pixel electrode) is higher than the counter electrode voltage VCOM. In this period T1, a positive voltage is applied to the liquid crystal element. On the other hand, the negative period T2 is a period in which the voltage Vs of the data line is lower than the counter electrode voltage VCOM. In this period T2, a negative voltage is applied to the liquid crystal element. The high potential side voltage VCOMH can be said to be a voltage obtained by inverting the polarity of the low potential side voltage VCOML with reference to a given voltage.

  Thus, by inverting the polarity of the counter electrode voltage VCOM, the voltage required for driving the LCD panel can be lowered. Thereby, the withstand voltage of the drive circuit of the LCD panel can be lowered, and the drive circuit manufacturing process can be simplified and the cost can be reduced.

2. Supply ability control The ability of the power supply circuit to supply the common electrode voltage VCOM is determined by the load of the common electrode COM. Insufficient power supply capability of the power supply circuit leads to degradation of image quality. Therefore, this capability is generally determined in consideration of the maximum amount of charge that the counter electrode COM should charge and discharge.

  However, the voltage Vs of the data line changes depending on the gradation value represented by the gradation data. Since the gradation value is different for each scan line, the data line voltage Vs is also different for each scan line. Since the counter electrode and the pixel electrode are capacitively coupled as described above, the supply capability of the counter electrode voltage VCOM is necessary or unnecessary depending on the applied voltage of the pixel electrode or the amount of change (change). There are cases.

  6A and 6B schematically show changes in power consumption of the power supply circuit that supplies the common electrode voltage VCOM.

  6A and 6B, it is assumed that polarity inversion driving is performed by line inversion driving in a general normally white active matrix type LCD panel. FIG. 6A shows a change in power consumption when black display is performed. FIG. 6B shows a change in power consumption when white display is performed.

  In the voltage change period in which the voltage level of the common electrode voltage VCOM changes, the power supply circuit needs to have a high supply capability because the voltage level of the common electrode COM of the high potential side voltage VCOMH needs to be the low potential side voltage VCOML. To do. Further, the power supply circuit needs to have a high supply capability because it is necessary to set the voltage level of the counter electrode COM of the low potential side voltage VCOML to the high potential side voltage VCOMH even in the next voltage change period. A large amount of power is consumed during these voltage change periods.

  In the gradation output period in which the voltage supply of the data line is performed after the voltage level of the counter electrode COM is changed, a voltage corresponding to the gradation value in the horizontal scanning period is written to the pixel electrode. At this time, the counter electrode COM capacitively coupled to the pixel electrode needs to be supplied or extracted with charges so as to cancel the fluctuation of the voltage applied to the pixel electrode.

  However, in the case of black display shown in FIG. 6A, it is necessary to increase the voltage applied to the pixel electrode as compared with the case of white display shown in FIG. This is because the difference between the counter electrode voltage VCOM and the applied voltage of the pixel electrode needs to be made larger in the case of FIG. 6A than in FIG. 6B.

  Therefore, in the case of FIG. 6 (A), power consumption increases compared with the case of FIG. 6 (B). That is, the power consumption of the power supply circuit that drives the counter electrode COM differs depending on the gradation value in the horizontal scanning period.

  However, in a general power supply circuit, as shown in FIG. 6A, it is determined in consideration of the maximum amount of charge that the counter electrode COM should charge and discharge. Therefore, in the case shown in FIG. 6B, wasteful power is consumed even though the power supply capability of the power supply circuit is not so much required.

  Therefore, the power supply circuit in the present embodiment can control the supply capability of the common electrode voltage VCOM. By doing so, the circuit scale of the power supply circuit can be reduced and the power consumption can be reduced without degrading the image quality of the LCD panel.

  FIG. 7 shows a configuration example of a power supply capability control system including a power supply circuit in the present embodiment.

  In FIG. 7, the same parts as those in FIG. 1 or FIG. In this power supply capability control system, the power supply circuit 100 supplies, for example, the power supply voltages VDD and VSS of the data driver 30. The power supply circuit 100 inverts the polarity of the common electrode voltage VCOM in synchronization with the polarity inversion signal POL from the data driver 30. Furthermore, the power supply circuit 100 receives the evaluation value from the data driver 30 and changes the supply capability of the common electrode voltage VCOM based on the evaluation value.

  As the evaluation value, gradation data (line data) for one scanning line in the horizontal scanning period and values (line values) obtained based on the gradation data for one scanning line can be employed. For example, the amount of charge to be charged / discharged from the counter electrode is predicted based on gradation data for one scan line in the horizontal scan period, and the supply capability of the counter electrode voltage VCOM is changed. Alternatively, the charge amount of the counter electrode to be charged / discharged is related to the fluctuation amount of the voltage applied to the pixel electrode, and the gradation data for one scanning line in the immediately preceding horizontal scanning period is equivalent to one scanning line in the horizontal scanning period. It is also possible to employ a change in gradation data.

  Further, when obtaining any one of the above evaluation values, each of the gradation data for the number of dots of one scanning line is converted into each conversion voltage value according to the gradation characteristics of the LCD panel 20, and each of the conversion values is converted. A total value obtained by sequentially adding voltage values may be used. By doing so, it is possible to realize the supply capability control of the counter electrode voltage in consideration of the voltage applied to the pixel electrode according to the gradation characteristic.

  Hereinafter, the data driver 30 and the power supply circuit 100 that realize the supply capability control of the counter electrode voltage according to the gradation characteristics will be described.

2.1 Data Driver FIG. 8 is a block diagram showing a configuration example of the data driver 30 shown in FIG.

  The data driver 30 includes a data latch 200, a line latch 210, a level shifter (L / S) 220, a reference voltage generation circuit 230, a DAC (Digital / Analog Converter) (voltage selection circuit in a broad sense) 240, and a drive circuit. 250.

  Data latch 200 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each output line of data driver 30, and each flip-flop is connected in series. Gradation data is taken into each flip-flop, and a voltage corresponding to the gradation data is supplied to each output line. Such gradation data is input from the display controller 38 serially in pixel units (or one dot unit) in synchronization with the dot clock DCK. The data latch 200 can take in the gradation data for one horizontal scan, for example, by shifting the gradation data in synchronization with the dot clock DCK. At this time, the dot clock DCK is supplied from the display controller 38. When one pixel is composed of 6-bit R signal, G signal, and B signal, one pixel (= 3 dots) is composed of 18 bits.

  Line latch 210 also includes a plurality of flip-flops in which each flip-flop is provided corresponding to each output line. Then, the gradation data fetched by the data latch 200 is latched by the line latch 210 at the change timing of the horizontal synchronization signal HSYNC.

  L / S 220 includes a plurality of level conversion circuits each provided corresponding to each output line. Each level conversion circuit converts a voltage level so that a gradation data signal that swings at a logic voltage of, for example, 1.8 volts is amplified at a voltage of, for example, 5 volts.

  The reference voltage generation circuit 230 generates a plurality of reference voltages corresponding to the respective gradation values represented by the gradation data. More specifically, the reference voltage generation circuit 230 has a plurality of reference voltages corresponding to, for example, 6-bit gradation data based on the high-potential-side power supply voltage VDD and the low-potential-side power supply voltage VSS. The reference voltages V0 to V63 can be generated. The power supply voltage VDD on the high potential side and the power supply voltage VSS on the low potential side are generated by the power supply circuit 100, for example.

  The DAC 240 includes a plurality of ROM decoder circuits each provided corresponding to each output line. Each ROM decoder circuit selects one of the reference voltages V0 to V63 from the reference voltage generation circuit 230 based on the signal of the gradation data whose voltage level is converted by the level conversion circuit of the L / S 220. Thereby, the DAC 240 can generate a data voltage corresponding to the gradation data for each output line.

  The drive circuit 250 drives a plurality of output lines in which each output line is connected to each data line of the LCD panel 20. More specifically, drive circuit 250 includes a plurality of impedance conversion circuits each provided corresponding to each output line. The plurality of impedance conversion circuits drive the plurality of output lines based on the data voltage generated for each output line by the DAC 240. Each impedance conversion circuit is constituted by an operational amplifier connected in a voltage follower.

  In the data driver 30 having such a configuration, for example, gradation data for one horizontal scan captured by the data latch 200 is latched by the line latch 210. Using the gradation data latched by the line latch 210, a data voltage is generated for each output line. Then, the drive circuit 250 drives each output line based on the data voltage generated by the DAC 240.

  FIG. 9 shows an outline of the configuration of the reference voltage generation circuit 230, the DAC 240, and the drive circuit 250. Here, only the configuration of one output line of the drive circuit 250 is shown, but the same applies to the other output lines. FIG. 9 shows only the configuration of the drive circuit 250-1 that drives the data line DL1 in the drive circuit 250.

  In the reference voltage generation circuit 230, a resistance circuit is connected between the high-potential side power supply voltage VDD and the low-potential side power supply voltage VSS. Then, the reference voltage generation circuit 230 generates a plurality of divided voltages obtained by dividing the voltage between the power supply voltages VDD and VSS by the resistor circuit as reference voltages V0 to V63. In the case of polarity inversion driving, the voltage is not symmetrical between the case of positive polarity and the case of negative polarity, so that a positive reference voltage and a negative reference voltage are generated. FIG. 9 shows one of them.

  The DAC 240-1 can be realized by a ROM decoder circuit. The DAC 240-1 selects any one of the reference voltages V0 to V63 based on the 6-bit gradation data, and outputs the selected voltage to the impedance conversion circuit DRV-1 as the selection voltage Vsel. Similarly, voltages selected based on the corresponding 6-bit gradation data are output to the other impedance conversion circuits DRV-2 to DRV-N.

  The DAC 240-1 includes an inverting circuit 242-1. The inversion circuit 242-1 inverts the data of each bit of the gradation data based on the polarity inversion signal POL. The ROM decoder circuit receives 6-bit gradation data D0 to D5 and 6-bit driving inversion gradation data XD0 to XD5. The inversion gradation data for driving XD0 to XD5 is obtained by logically inverting the data of each bit of the gradation data D0 to D5. In the ROM decoder circuit, any one of the multi-valued reference voltages V0 to V63 generated by the reference voltage generation circuit 230 is based on the gradation data D0 to D5 and the driving inverted gradation data XD0 to XD5. Selected.

  For example, when the polarity inversion signal POL is at the H level, the reference voltage V2 is selected corresponding to the 6-bit gradation data D0 to D5 “000010” (= 2). For example, when the polarity inversion signal POL is at the L level, the reference voltage is selected using the drive inversion gradation data XD0 to XD5 obtained by inverting the gradation data D0 to D5. That is, the driving inversion gradation data XD0 to XD5 is “111101” (= 61), and the reference voltage V61 is selected.

  The selection voltage Vsel selected by the DAC 240-1 in this way is supplied to the impedance conversion circuit DRV-1. Then, the impedance conversion circuit DRV-1 drives the output line OL-1 based on the selection voltage Vsel. At this time, as described above, the power supply circuit 100 changes the common electrode voltage VCOM in synchronization with the polarity inversion signal POL. In this way, driving is performed with the polarity of the voltage applied to the liquid crystal reversed.

  8 may further include a voltage value conversion circuit 258, a line value calculation circuit (total value calculation circuit) 260, and a line value output unit 270. The line value calculation circuit 260 generates a line value based on the converted voltage value converted by the voltage value conversion circuit 258 as an evaluation value supplied to the power supply circuit 100. The line value output unit 270 includes a buffer, adjusts the output timing of the line value generated by the line value calculation circuit 260, and supplies the line value after adjusting the output timing to the power supply circuit 100. By adjusting this output timing, the counter electrode voltage VCOM of the power supply circuit 100 can be changed in association with the converted voltage value for one scan line corresponding to the gradation data for one scan line.

  Although the data driver 30 and the power supply circuit 100 are described as being provided independently in FIG. 8, the data driver 30 in FIG. 8 may incorporate the power supply circuit 100.

2.2 Conversion Voltage Value FIG. 10 is a diagram for explaining gradation characteristics of a general LCD panel.

  In FIG. 10, to simplify the description, it is assumed that a maximum voltage of 5 volts is applied to the pixel electrodes of the 16-gradation LCD panel. Further, gradation characteristics are shown when the LCD panel is normally white and the counter electrode voltage VCOM is at L level. Therefore, white is displayed when the voltage is 0 volts, and black is displayed when the voltage is 5 volts. In the graph showing the gradation characteristics, the horizontal axis represents gradation, and the vertical axis represents voltage. The gradation is represented by gradation data. The voltage is a data voltage supplied to the data line.

  In the gradation characteristics shown in FIG. 10, the relationship between gradation and voltage is not a linear relationship. Therefore, for each gradation data, it is necessary to obtain a data voltage according to the gradation characteristics shown in FIG. 10 and supply the data voltage.

  Therefore, the voltage value conversion circuit 258 converts the gradation data of the number of dots corresponding to the number of dots of one scanning line corresponding to the applied voltage of the pixel electrode into the gradation data as shown in FIG. The conversion voltage value is converted according to And a line value is calculated | required based on this conversion voltage value. By doing so, the supply capability of the counter electrode voltage VCOM can be controlled in accordance with the voltage applied to the pixel electrode in accordance with the gradation characteristics shown in FIG.

  At this time, as shown in FIG. 10, the voltage difference per gradation greatly varies depending on the gradation value. For example, the data voltage difference ΔV1 between the gradation value 0 and the gradation value 1 is 1.0 volt. For example, the data voltage difference ΔV2 between the gradation value 6 and the gradation value 7 is 0.1 volt. . Therefore, it is necessary to obtain the data voltage applied to the pixel electrode with the accuracy of the minimum data voltage difference among the gradation characteristics shown in FIG.

  Therefore, when the voltage supply capability of the counter electrode is controlled in accordance with the applied voltage of the pixel electrode for one scan line, it is desirable that the evaluation value can be calculated with an accuracy substantially equal to the accuracy of the minimum data voltage difference of gradation characteristics. Therefore, it is desirable for the voltage value conversion circuit 258 to obtain the converted voltage value so that the number of bits of gradation data is smaller than the number of bits of data representing the converted voltage value.

  FIG. 11 is a diagram for explaining an example of the operation of the voltage value conversion circuit 258 that generates the converted voltage value in accordance with the gradation characteristics of FIG.

  FIG. 11 shows an example in which the gradation data is 4 bits and the data representing the converted voltage value is 6 bits. Thus, by converting the 4-bit gradation data into the converted voltage value represented by the 6-bit data, it becomes possible to generate a converted voltage value corresponding to the gradation characteristics shown in FIG.

  FIG. 12 shows a block diagram of a configuration example of the voltage value conversion circuit 258 of FIG.

  The voltage value conversion circuit 258 includes a gradation designation register 300, a gradation data determination circuit 310, and a conversion voltage value generation circuit 320. In FIG. 12, the voltage value conversion circuit 258 is configured to include the gradation designation register 300, but the gradation designation register 300 may be provided outside the voltage value conversion circuit 258.

In the gradation designation register 300, gradation designation information is set. This gradation designation information is information for designating 2 ^v (1 ≦ v <u, v is an integer) types of voltages from 2 ^u (u is an integer of 2 or more) types of voltages. In the following, it is assumed that u is 8 and v is 6, and 64 (= 2 ⁶ ) types of voltages are designated from 256 (= 2 ⁸ ) types of voltages. Such gradation designation information is set by the display controller 38 or the host. The gradation designation information set in the gradation designation register 300 is supplied to the gradation data determination circuit 310.

Gradation data determination circuit 310, based on the gradation designating information from the gradation designating register 300, determines whether the reference voltage corresponding to the 6-bit grayscale data is either the voltage of 2 ⁸ kinds of voltages . Then, the conversion voltage value generation circuit 320 generates a conversion voltage value represented by 8-bit data based on the determination result of the gradation data determination circuit 310.

That is, in the voltage value conversion circuit 258, the gradation value (gradation number) represented by 6-bit gradation data is any of 256 (= 2 ⁸ ) types of conversion voltage values represented by 8-bit data. Assigned to. Then, the voltage value conversion circuit 258 receives 6-bit gradation data and outputs an assigned converted voltage value corresponding to the gradation data.

  FIG. 13 shows a block diagram of a circuit configuration example of the voltage value conversion circuit 258 of FIG.

  However, in FIG. 13, blocks corresponding to the voltage value conversion circuit 258 of FIG.

In FIG. 13, the gradation designation information set in the gradation designation register 300 is 2 ^u bits. Therefore, when u is 8, it is 256 bits. Each bit is set with a flag indicating whether or not v-bit gradation data is assigned to each of 2 ^u types of voltages.

  FIG. 14 shows a configuration example of the gradation designation information set in the gradation designation register 300 of FIG.

In FIG. 14, each bit is assigned to 2 ^u types of voltage values. It is assumed that 1 is set to a bit to which a voltage value corresponding to v-bit gradation data is assigned, and 0 is set to a bit to which the voltage value is not assigned.

For example, u is 8, v is 6, if the voltage value corresponding to the 6-bit gradation data is assigned, is set only 2 ⁶ bits of the two ^8-bit gradation designating information of "1", the remaining Are set to “0”.

  In FIG. 13, the gradation data determination circuit 310 includes a designation information generation circuit 312 and a comparison circuit 314.

The designation information generation circuit 312 generates ^2v types of designation information based on the gradation designation information. When the number of bits of the gradation data is v, the designation information generation circuit 312 generates ^2v types of designation information based on the gradation designation information.

The comparison circuit 314 compares the gradation data with the designated information using the v-bit gradation data as the gradation number before conversion. Thereby, it is possible to determine whether the voltage value is assigned with v-bit gradation data among 2 ^u types of voltage values. Then, using the comparison result of the comparison circuit 314 as the determination result of the gradation data determination circuit 310, the conversion voltage value generation circuit 320 generates a conversion voltage value represented by u-bit data.

  Before describing the configuration of each block in FIG. 13, an outline of the operation of the circuit diagram of the configuration example in FIG. 13 will be described.

  FIG. 15 is an explanatory diagram outlining the operation of the circuit configuration example of the voltage value conversion circuit 258 of FIG.

  First, the gradation designation information is divided into a plurality of blocks. Then, for each block, it is determined whether or not the gradation number before conversion represented by the v-bit gradation data matches the designation information. Using this determination result, a process of generating a converted voltage value in units of blocks is performed.

For this purpose, each block is assigned unique block data. In Figure 15, it divides the 2 ^8-bit gradation designating information in 32 blocks in units of 8 bits, are allocated to the block data of five bits to each block. For example, in FIG. 15, the block data “00000” is allocated to the block GREG1 to which the 0th to 7th bits of the 256-bit gradation designation information belong. In FIG. 15, block data “00001” is allocated to the block GREG2 to which the 8th to 15th bits of the 256-bit gradation designation information belong. Similarly, in FIG. 15, block data “11111” is allocated to the block GREG 32 to which the 248th to 255th bits of the 256-bit gradation designation information belong.

  The designation information generation circuit 312 generates designation information in the direction from the 0th bit to the 255th bit of the gradation designation information based on the state of the flag set for each bit. More specifically, the designation information generation circuit 312 detects whether or not the flag set in the bit is set to 1 in the direction from the 0th bit to the 255th bit of the gradation designation information. Then, on condition that the flag is set to 1, the count value set to 0 by the 0th bit of the gradation designation information is counted up, and this count value is used as the designation information. For example, in the example shown in FIG. 15, the count value of 0 at the 0th bit of the gradation designation information is counted up to 1 at the 2nd bit, and further counted up to 2 at the 5th bit. Such a count-up is performed up to the 255th bit. When v is 6, the count value is 64 at the 255th bit.

  Next, the comparison circuit 314 obtains, as a matching block, a block in which the specified data matches the gradation data that is the gradation number before conversion. Further, the comparison circuit 314 obtains a bit position where the flag is set (specified) in the gradation designation information and the gradation data matches the designation information in the matching block. In FIG. 15, when 6-bit gradation data “0000011” is input, the comparison circuit 314 obtains the block GREG2 as a matching block, and uses the second bit of the block GREG2 (the gradation designation information) as the bit position. 10th bit). Bit data is assigned to the bit position of each block.

  In the gradation data determination circuit 310, it is desirable to count up the designated information after the comparison by the comparison circuit 314. By doing so, even when the 6-bit gradation data is 0, it is possible to correctly compare with the specified information.

  Then, the conversion voltage value generation circuit 320 generates a conversion voltage value based on the block data assigned to the matching block and the bit data corresponding to the bit position.

In FIG. 15, when 6-bit gradation data “000011” is input, block data “00001” of block GREG2 and bit data “010” corresponding to the second bit of block GREG2 (binary representation of 2) Based on the above, data “00001010” for specifying the converted voltage value is generated. That is, block data is set in the upper 5 bits of the data, and bit data is set in the lower 3 bits. Thus, 8-bit data specifying either the 2 ⁸ different voltage values are generated.

  Similarly, in the case of 6-bit gradation data “100000” in FIG. 15, it is determined that the designation information of this gradation data matches 32. Therefore, the comparison circuit 314 obtains the block GREG17 as the coincidence block and the sixth bit as the bit position. Since the block data of the block GREG17 is “10000” and the bit data corresponding to the bit position is “110” (binary representation of 6), 8-bit data “10000101” is generated.

  FIG. 16 shows a block diagram of a detailed circuit configuration example of the voltage value conversion circuit 258 of FIG.

  In FIG. 16, gradation designation information is supplied to each block in units of 8 bits by DATA <0: 7>. In the block GREGq (1 ≦ q ≦ 32, q is an integer), DATA <0: 7> is captured at the change point of the write clock CKq. Each block of the blocks GREG1 to GREG32 has the same configuration.

  Then, the 8-bit gradation designation information from the block GREGq is supplied to the block ADDRq configured as a block unit as the gradation data determination circuit 310. In this block ADDRq, 6-bit gradation data is input as ID <0: 5>, and the determination result is output as DO <0: 7>.

  The DO <0: 7> is input to the block ENCq configured as a block unit as the conversion voltage value generation circuit 320. Each of the blocks ENC1 to ENC32 is assigned 5-bit block data. Each block data is set with 5 bits of UP3 to UP7. Then, the block ENCq outputs AD <0: 7> as data for specifying the converted voltage value.

  FIG. 17 shows a circuit diagram of a configuration example of the block GREGq of FIG.

  The block GREGq has eight D-type flip-flops (hereinafter abbreviated as DFF) q0 to DFFq7. D <0: 7> is commonly supplied to DFFq0 to DFFq7, and the data of each bit of the gradation designation information is taken in based on the inverted signal of XC.

  FIG. 18 shows a circuit diagram of a configuration example of the block ADDRq of FIG.

  Block ADDRq includes comparison operation circuits PROq0 to PROq7 provided for each bit of DI <0: 7>. Comparison operation circuit PROqr (0 ≦ r ≦ 7, r is an integer) includes comparison circuit CMPqr and addition circuit ADDqr. That is, for example, the comparison operation circuit PROq0 is provided corresponding to DI <0>, and includes the comparison circuit CMPq0 and the addition circuit ADDq0. Similarly, for example, the comparison operation circuit PROq7 is provided corresponding to DI <7>, and includes a comparison circuit CMPq7 and an addition circuit ADDq7.

  IND <0: 5> is input to the comparison operation circuit PROq0 as a signal representing 6-bit gradation data. PI <0: 5> is a signal representing designation information, and is a comparison operation circuit according to the data of each bit of DI <0: 7> representing 8-bit gradation designation information out of 256 bits. Every time the value is counted as it is or incremented. A signal indicating that the designation information is 0 is input to PI <0: 5> of the comparison operation circuit PROq0.

  The comparison circuit CMPq0 compares the PI <0: 5> representing the designation information with the IND <0: 5> representing the gradation data, and becomes the H level when they match, and becomes the L level when they do not match. <0> is output.

  In comparison circuit CMPq0, when both coincide, mask control is performed so that DO <0> becomes H level on condition that DI <0> is H level. This is because PI <0: 5> represents designation information regardless of the assignment state of 6-bit gradation data among 256 gradations, and therefore 6-bit gradation data is assigned among 256 types of voltage values. This is to prevent DO <0> from being at the H level in the case of no gradation. For example, in FIG. 15, PI <0: 5> represents designation information, but represents 3 up to the 10th to 12th bits of 256-bit gradation designation information. At this time, in the 10th bit in which the flag flag of the gradation designation information is set to 1, the coincidence signal indicating that the gradation data coincides with the designation information is set to H level, and the 11th and 12th bits The coincidence signal can be set to L level.

  The adder circuit ADDq0 adds DI <0>, which is 1-bit data of the gradation designation information, and PI <0: 5>, and supplies the addition result as PI <0: 5> of the comparison operation circuit PROq1. To do.

  Similarly, the comparison operation circuit PROq1 compares PI <0: 5> from the addition circuit ADDq0 with the gradation data IND <0: 5> in the comparison circuit CMPq1, and outputs the comparison result as DO <1>. To do. Then, in the adder circuit ADDq1, PI <0: 5> and DI <1> are added, and the addition result is supplied as PI <0: 5> of the comparison operation circuit PROq2.

  In this way, DO <0: 7> output for each comparison operation circuit is supplied to the block ENCq. Then, the addition result of the addition circuit ADDq7 of the comparison operation circuit PROq7 is PO <0: 5>, and the comparison circuit CMP (q + 1) 0 and the addition circuit of the comparison operation circuit PRO (q + 1) 0 of the next block ADDR (q + 1). (Q + 1) 0 is supplied.

  FIG. 19 shows a circuit diagram of a configuration example of the block ENCq of FIG.

  DO <0: 7> from the block ADDRq is input to the block ENCq as IN <0: 7>. Then, the block ENCq encodes IN <0: 7> with 3-bit AD <0: 2>. Thereby, bit data corresponding to the bit position of each block can be output.

  The block ENCq determines whether any of the bits of IN <0: 7> is at the H level. As a result, it is possible to determine whether or not the block is a matching block in which the specified information matches the gradation data that is the gradation number before conversion. That is, output control of UP3 to UP7 is performed based on the result of logical OR operation of IN <0: 7> for each bit. UP3 to UP7 are data specific to the block ENCq as block data.

  With this configuration, when all IN <0: 7> are at the L level, the block ENCq sets AD <0: 2> to the high impedance state and AD <3: 7> is also set to the high impedance state. The

  On the other hand, when any bit of IN <0: 7> is at the H level, the encoding result is output to AD <0: 2>. For example, when IN <3> is at H level, “100” is output as AD <0: 2>. Then, the block data of the block ENCq is output as AD <3: 7>. For example, in the case of the block ENC10, “01001” is output as AD <3: 7>.

  In this way, the block ENCq bit-links AD <0: 2> and AD <3: 7>, and outputs AD <0: 7> as 8-bit data for specifying the converted voltage value.

  By the way, it is conceivable to realize a voltage value conversion circuit having the above functions by a so-called ROM (Read Only Memory) circuit. However, when the ROM circuit is employed, the circuit becomes large-scale, and the chip area of the data driver incorporating the ROM circuit increases, resulting in an increase in cost.

In this case, when manufactured by a 0.25 μm process as a general manufacturing process, the size of the ROM per cell is 15 μm ² . Therefore, 64 (address) × 15 (μm ² / cell) × 8 (cell) = 7680 μm ² is required as the cell area per color component. Furthermore, since an address decoder for decoding this address is required, a total of about 9000 μm ² is required.

  On the other hand, when the above-described circuit configuration is manufactured by the same manufacturing process, it has been found that only about 300 μm in width and about 15 μm in length are sufficient.

  As described above, in the circuit realized by the present embodiment, the circuit scale can be greatly reduced as compared with the case where the ROM is used. Further, it is not necessary to use a special manufacturing process to reduce the scale of the ROM circuit, and the manufacturing cost can be reduced.

2.3 Evaluation Method In this embodiment, the counter electrode voltage VCOM of the power supply circuit 100 is changed in association with gradation data (line data) for one scanning line corresponding to the applied voltage of the pixel electrode. Note that the counter electrode voltage VCOM of the power supply circuit 100 may be changed in association with the change in gradation data (line data) for one scan line corresponding to the change in the applied voltage of the pixel electrode.

  In the embodiment described below, the line value calculation circuit 260 of FIG. 8 converts the gradation data constituting the line data according to the gradation characteristics to obtain the converted voltage value. Then, a total value obtained by sequentially adding each conversion voltage value by one scanning line is obtained.

  The power supply circuit 100 predicts (evaluates) the applied voltage of the pixel electrode or the variation of the applied voltage based on the total value, and changes the supply capability of the counter electrode voltage VCOM based on the predicted result (evaluated result). Take control. In this way, wasteful current consumption of the power supply circuit 100 is reduced. The same applies to the case where the supply capability of the counter electrode voltage VCOM is changed based on the change in the total value.

  FIG. 20 shows a configuration example of data representing the converted voltage value per dot.

  FIG. 20 shows a configuration example of gradation data corresponding to the voltage supplied to the data line DL1 (output line OL-1). The data line DL1 is supplied with a voltage corresponding to R component gradation data constituting one pixel. A conversion voltage value obtained by converting the gradation data in accordance with the gradation characteristics of the LCD panel 20 is applied to the voltage applied to the pixel electrode.

Converting the voltage value data CR ₁ specifying the converted voltage value converted according to the gradation data of the R component to tone characteristic j (j is an integer of 2 or greater) shall be composed of bits. In this case, the upper k of the converted voltage value data CR ₁ (k <j, k is a natural number) data bits, comprises a converted voltage value data CR ₁ for MSB (Most Significant Bit), from the MSB side of the upper k bits Data UR ₁ . The most significant bit of the converted voltage value data CR ₁ is when k is 1, which is the MSB data MR ₁ in FIG.

  FIG. 21 is a diagram for explaining an example of the arithmetic processing of the line value arithmetic circuit 260 of FIG.

  In FIG. 21, it is assumed that one pixel is composed of 3 dots and the number of pixels for one scanning line is 240 (= 720 dots).

In the present embodiment, the drive circuit 250-1 drives the data line DL1 based on the R component gradation data constituting one pixel. Driving circuit 250-2 drives the data line DL2 based on grayscale data _{R 1} of the G component forming one pixel. Driving circuit 250-3 drives the data line DL3 based on grayscale data _{B 1} and B component making up one pixel. The gradation data for the pixel P ₁ is composed of gradation data R ₁ , G ₁ , B ₁ .

Similarly driving circuit 250-4 drives the data line DL4 based on grayscale data _{R 2} of the R component forming one pixel. Driving circuit 250-5 drives the data line DL5 based on the grayscale data _{G 2} of the G component forming one pixel. Driving circuit 250-6 drives the data line DL6 based on the grayscale data _{B 2} and B component making up one pixel. Tone data of the pixel _{P 2} minutes is composed of gray-scale data _{R 2, G 2, B 2} .

Further, similarly, the drive circuit 250-718 drives the data line DL718 based on grayscale data _{R 240} of the R component forming one pixel. Drive circuit 250-719 drives the data line DL719 based on grayscale data _{G 240} of the G component constituting one pixel. The drive circuit 250-720 drives the data line DL720 based on the B component gradation data B ₂₄₀ constituting one pixel. The gradation data for the pixel P ₂₄₀ is composed of gradation data R ₂₄₀ , G ₂₄₀ , and B ₂₄₀ .

  The line value calculation circuit 260 uses, as a line value, a total value TOTAL1 obtained by sequentially adding converted voltage value data obtained by converting each gradation data of gradation data corresponding to the number of dots (= 720) of one scanning line according to the gradation characteristics. Ask. For example, the line value arithmetic circuit 260 includes an adder and a register, sequentially adds gradation data input serially, stores the result in the register, and adds the value of the register and the next gradation data. repeat. In this case, the total value TOTAL1 can be expressed by the following equation.

TOTAL1 = CR ₁ + CG ₁ + CB ₁ + CR ₂ + CG ₂ + CB ₂ + ... + CR ₂₄₀ + CG ₂₄₀ + CB ₂₄₀ (1)
For example, the line value calculation circuit 260 converts the upper k bits of the converted voltage value data obtained by converting the gradation data of the gradation data corresponding to the number of dots (= 720) of one scanning line according to the gradation characteristics. You may obtain | require the total value TOTAL2 added sequentially as a line value. In this case, the total value TOTAL2 can be expressed by the following equation.

TOTAL2 = UR ₁ + UG ₁ + UB ₁ + UR ₂ + UG ₂ + UB ₂ + ... + UR ₂₄₀ + UG ₂₄₀ + UB ₂₄₀ (2)
Alternatively, for example, the line value calculation circuit 260 converts the gradation data of gradation data corresponding to the number of dots (= 720) of one scanning line into the most significant bit (k) of the converted voltage value data obtained by converting the gradation data according to the gradation characteristics. = 1) The total value TOTAL3 obtained by sequentially adding the data may be obtained as a line value. In this case, the total value TOTAL3 can be expressed by the following equation.

TOTAL3 = MR ₁ + MG ₁ + MB ₁ + MR ₂ + MG ₂ + MB ₂ + ... + MR ₂₄₀ + MG ₂₄₀ + MB ₂₄₀ (3)
The total values TOTAL1, TOTAL2, and TOTAL3 as described above can be associated with the sum of the magnitudes of voltages applied to the pixel electrodes of one scanning line according to the gradation characteristics, and have the ability to supply the counter electrode voltage VCOM. It can be used as a material for determining whether the voltage level does not fluctuate even if it needs to be raised or lowered.

  Further, when the value obtained by sequentially adding the converted voltage values is represented by p (p is an integer of 2 or more) bits of data, the upper q (q < A value represented by bits (p and q are natural numbers) may be adopted.

2.4 Power Supply Circuit FIG. 22 shows a configuration example of the power supply circuit 100 in FIG.

  The power supply circuit 100 supplies the counter electrode voltage VCOM to the counter electrode that faces the pixel electrode with the electro-optic material interposed therebetween. The power supply circuit 100 includes a VCOMH generation circuit (high potential side voltage generation circuit) 110, a VCOML generation circuit (low potential side voltage generation circuit) 120, and a switching circuit 130. The VCOMH generation circuit 110 generates a high potential side voltage VCOMH of the common electrode voltage VCOM. The VCOML generation circuit 120 generates a low potential side voltage VCOML of the common electrode voltage VCOM. The switching circuit 130 alternately supplies one of the high potential side voltage VCOMH and the low potential side voltage VCOML as the counter electrode voltage VCOM to the counter electrode COM.

  The switching circuit 130 includes a P-type (first conductivity type) output metal-oxide-semiconductor (MOS) transistor (hereinafter, MOS transistor is simply abbreviated as a transistor) OTrp1 and an N-type output transistor OTrn1. Can be included. The high potential side voltage VCOMH is supplied to the source of the output transistor OTrp1, and the drain of the output transistor OTrn1 is connected to the drain. A gate signal INP is supplied to the gate of the output transistor OTrp1. The low potential side voltage VCOML is supplied to the source of the output transistor OTrn1. A gate signal INN is supplied to the gate of the output transistor OTrn1. The drain voltage of the output transistor OTrp1 (the drain voltage of the output transistor OTrn1) is output as the common electrode voltage VCOM.

  FIG. 23 shows an example of the timing of the gate signals INP and INN in FIG.

  The output transistor OTrp1 is set to a conductive state when the gate signal INP is at the L level, and is set to a non-conductive state when the gate signal INP is at the H level. The output transistor OTrn1 is set to a non-conductive state when the gate signal INN is at the L level, and is set to a conductive state when the gate signal INN is at the H level.

  At this time, the gate signals INP and INN are generated so that the output transistors OTrp1 and OTrn1 are not simultaneously set to the conductive state (so that one or both of the output transistors OTrp1 and OTrn1 are set to the nonconductive state). Further, the gate signals INP and INN are generated so that the period in which the gate signal INP changes from the H level to the L level does not overlap with the period in which the gate signal INN changes from the H level to the L level. Furthermore, the gate signals INP and INN are generated so that the period during which the gate signal INP changes from L level to H level does not overlap with the period during which the gate signal INN changes from L level to H level.

  By doing so, a situation in which the source of the output transistor OTrp1 and the source of the output transistor OTrn1 are electrically connected can be avoided, and current consumption can be reduced.

  The power supply circuit 100 shown in FIG. 22 changes at least one of the current drive capability and the output voltage level of the VCOMH generation circuit (high potential side voltage generation circuit) 110 according to the total value obtained by sequentially adding the converted voltage values. Thus, the supply capability control of the counter electrode voltage VCOM is performed. Each conversion voltage value is obtained by converting each gradation data of gradation data corresponding to the number of dots of one scanning line corresponding to the applied voltage of the pixel electrode according to the gradation characteristics. Alternatively, the power supply circuit 100 supplies the common electrode voltage VCOM by changing at least one of the current drive capability and the output voltage level of the VCOML generation circuit (low potential side voltage generation circuit) 120 according to the total value. Perform capacity control. That is, the power supply circuit 100 determines the current drive capability of the VCOMH generation circuit (high potential side voltage generation circuit) 110, the output voltage level of the VCOMH generation circuit 110, and the VCOML generation circuit (low potential side voltage generation circuit) 120 according to the total value. By changing at least one of the current drive capability and the output voltage level of the VCOML generation circuit 120, it can be said that the supply capability control of the common electrode voltage VCOM is performed.

  The total value is obtained as a line value as described in FIG.

  The power supply circuit 100 can include a power supply control circuit 150. The power supply control circuit 150 controls the supply capability of the counter electrode voltage VCOM. The power supply control circuit 150 can generate a supply capability control signal for performing the supply capability control. More specifically, the power supply control circuit 150 can generate the supply capability control signal according to the line value from the data driver 30. The power supply control circuit 150 generates a supply capacity control signal based on the set value of the power supply capacity setting register 160, for example. The power supply capacity setting register 160 stores control information such as a supply capacity control signal to be output and its output timing in accordance with the line value from the data driver 30.

  The supply capability control signal of the common electrode voltage VCOM includes gate signals TRP1, TRP2, INP, INN, TRN1, TRN2, and voltage generation control signals CNTH, CNTL. The voltage generation control signal CNTH includes a high potential side input voltage LEVINP for generating the high potential side voltage VCOMH, a current drive capability control signal BOOSTP, slew rate control signals VREFN1, VREFN2, and a drive current source control signal REFN. The voltage generation control signal CNTL includes a low potential side input voltage LEVINN for generating the low potential side voltage VCOML, a current drive capability control signal BOOSTN, slew rate control signals VREFP1, VREFP2, and a drive current source control signal REFP.

  Further, the power supply circuit 100 is supplied with the high potential side power supply voltage VOUT of the VCOM generation circuit (high potential side voltage generation circuit) 110 at the source and is electrically connected to the drain of the output of the switching circuit 130 (first type). At least one first auxiliary transistor of conductivity type may be included. The supply capacity control may be performed by controlling the gate voltage of the first auxiliary transistor according to the line value. By doing so, the current drive capability of the power supply circuit 100 can be increased or the current drive capability can be lowered. In FIG. 13, P-type transistors CTrp1 and CTrp2 are provided in parallel as the first auxiliary transistors and controlled by gate signals TRP1 and TRP2.

  Further, the power supply circuit 100 is supplied with the low potential side power supply voltage VOUTM of the VCOML generation circuit (low potential side voltage generation circuit) 120 at the source and is electrically connected to the output of the switching circuit 130 at the N type (second type). At least one second auxiliary transistor of conductivity type may be included. The supply capacity control may be performed by controlling the gate voltage of the second auxiliary transistor according to the line value. By doing so, the current drive capability of the power supply circuit 100 can be increased or the current drive capability can be lowered. In FIG. 23, N-type transistors CTrn1 and CTrn2 are provided in parallel as second auxiliary transistors, and are controlled by gate signals TRN1 and TRN2.

  Further, the power supply circuit 100 can include a first operational amplifier in which the VCOMH generation circuit 110 (high potential side voltage generation circuit) outputs the high potential side voltage VCOMH based on the high potential side input voltage. Then, when controlling the supply capability of the common electrode voltage VCOM, at least one of the current driving capability and the slew rate of the first operational amplifier may be changed according to the line value. Further, the high potential side voltage VCOMH may be changed by changing the high potential side input voltage in accordance with the line value. Alternatively, the operating current of the first operational amplifier may be stopped or limited according to the line value, and the input and output of the first operational amplifier may be electrically connected.

  Further, the power supply circuit 100 can include a second operational amplifier in which the VCOML generation circuit 120 (low potential side voltage generation circuit) outputs the low potential side voltage VCOML based on the low potential side input voltage. When performing the supply capability control, at least one of the current driving capability and the slew rate of the second operational amplifier may be changed according to the line value. Further, the low potential side voltage VCOML may be changed by changing the low potential side input voltage in accordance with the line value. Alternatively, the operating current of the second operational amplifier may be stopped or limited according to the line value, and the input and output of the second operational amplifier may be electrically connected.

  In FIG. 22, the high potential side power supply voltage VOUT and the low potential side power supply voltage VOUTM are generated by the power supply voltage generation circuit 140 of the power supply circuit 100. More specifically, the power supply voltage generation circuit 140 includes a high potential side power supply voltage generation circuit (first charge pump circuit) 142 and a low potential side power supply voltage generation circuit (second charge pump circuit) 144. Then, the high potential power supply voltage generation circuit 142 generates the high potential power supply voltage VOUT based on the power supply voltages VDD and VSS. The low potential side power supply voltage generation circuit 144 generates the low potential side power supply voltage VOUTM based on the power supply voltages VDD and VSS.

  The high-potential-side power supply voltage generation circuit 142 sets the voltage between the power supply voltages VDD and VSS in the high potential direction (positive direction) with reference to the power supply voltage VSS by a charge pump operation synchronized with the first charge clock. A boosted high potential side power supply voltage VOUT is generated. In this case, the supply capability of the common electrode voltage VCOM may be controlled by stopping the first charge clock or reducing the frequency thereof according to the line value.

  The low-potential-side power supply voltage generation circuit 144 sets the voltage between the power supply voltages VDD and VSS in the low potential direction (negative direction) with reference to the power supply voltage VSS by a charge pump operation synchronized with the second charge clock. A low-potential side power supply voltage VOUTM that has been boosted (stepped down) is generated. In this case, the supply capacity control may be performed by stopping the second charge clock or reducing the frequency thereof according to the line value.

  FIG. 24 is a schematic explanatory diagram of an operation example of the power supply voltage generation circuit 140 of FIG.

  The high-potential-side power supply voltage generation circuit 142 generates 3 volts, which is a voltage between the power supply voltages VDD and VSS, based on a potential of 0 volt (= VSS) by a charge pump operation synchronized with the first charge clock. A 6-volt high-potential-side power supply voltage VOUT that is doubled in the high-potential direction is generated.

  The low-potential-side power supply voltage generation circuit 144 uses the charge pump operation synchronized with the second charge clock to generate 3 volts, which is a voltage between the power supply voltages VDD and VSS, with reference to a potential of 0 volts (= VSS). A low potential side voltage VOUTM of -3 volts boosted by 1 (= -1) in the low potential direction is generated.

  In FIG. 22, the first and second charge clocks are shared, and the high-potential-side power supply voltage generation circuit 142 and the low-potential-side power supply voltage generation circuit 144 perform a charge pump operation synchronized with one charge clock CK. Like to do.

  In addition, the power supply circuit 100 can perform at least one of the above supply capability controls only for a period obtained based on the line value.

  Further, the power supply circuit 100 may perform at least one of the above-described supply capacity control in accordance with a change in the line value in the horizontal scanning period with respect to the line value in the immediately preceding horizontal scanning period. Furthermore, at least one of the above supply capability controls may be performed only during a period corresponding to the change in the line value of the horizontal scanning period with respect to the line value of the immediately preceding horizontal scanning period.

  When the gradation data of each dot is j (j is an integer of 2 or more) bits, the above-described line value is the upper k of the data representing the converted voltage value obtained by converting the gradation data of each dot according to the gradation characteristics. (K <j, k is a natural number) Bit data may be sequentially added. Further, k may be 1.

  Hereinafter, a configuration main part of the power supply circuit 100 of FIG. 22 will be specifically described.

  FIG. 25 shows a circuit diagram of a configuration example of the power supply voltage generation circuit 140 of FIG.

  The high-potential-side power supply voltage generation circuit 142 includes a level shifter LSH, inverters INVH1, INVH2, and switching transistors pTr1, pTr2. In FIG. 26, the flying capacitor FCH and the storage capacitor CsH are connected to the outside of the power supply circuit 100. However, at least one of these capacitors may be built in the power supply circuit 100 (high potential side power supply voltage generation circuit 142). .

  FIG. 26 is a timing chart for explaining the operation of the high potential side power supply voltage generation circuit 142.

  The level shifter LSH is supplied with a charge clock CK having an amplitude voltage between the power supply voltages VDD and VSS. When one of the two N-type transistors constituting the level shifter LSH is turned on, the other is turned off. For example, the drain voltage of the P-type transistor is determined so that the drain current of the N-type transistor supplied with the charge clock CK is generated. The logic level of the output signal of the level shifter LSH is inverted by the inverter INVH1 and becomes the output signal LSO. The logic level of the output signal LSO is inverted again by the inverter INVH2. The output signal LSO is supplied to the gate of the P-type transistor pTr1. An inverted signal of the output signal LSO is supplied to the gate of the P-type transistor pTr2.

  A period when the logic level of the output signal LSO is H level is PH1, and a period when the logic level is L level is PH2. In the period PH1, the transistor pTr1 is off and the transistor pTr2 is on. Therefore, the voltage VSS of the inverted charge clock CKX is supplied to one end of the flying capacitor FCH, and the voltage VDD is supplied to the other end. In the period PH2, the transistor pTr1 is turned on and the transistor pTr2 is turned off. Therefore, the voltage VDD of the inverted charge clock CKX is supplied to one end of the flying capacitor FCH, and the other end is electrically connected to the high potential side output power line. Since the charge corresponding to the voltage between the power supply voltages VDD and VSS is accumulated in the flying capacitor FCH in the period PH1, the voltage of the high potential side output power supply line becomes the voltage VDD × 2 in the period PH2. The voltage of the high potential side output power supply line is output as the voltage VOUT. The voltage level of the high potential side output power supply line is held by the storage capacitor CsH even in the period PH1.

  The low-potential-side power supply voltage generation circuit 144 includes a level shifter LSL, inverters INVL1 and INVL2, and switching transistors nTr1 and nTr2. In FIG. 16, the flying capacitor FCL and the storage capacitor CsL are connected to the outside of the power supply circuit 100. However, at least one of these capacitors may be built in the power supply circuit 100 (low potential side power supply voltage generation circuit 144). .

  Since the operation of the low-potential-side power supply voltage generation circuit 144 is the same charge pump operation as that of the high-potential-side power supply voltage generation circuit 142, detailed description thereof is omitted. Since the low-potential-side power supply voltage generation circuit 144 stores charges corresponding to the voltage between the power supply voltages VDD and VSS in the flying capacitor FCL, the voltage VOUTM in the negative direction with respect to the voltage VSS is set to the low-potential side. Supply to the output power line. The voltage of the low potential side output power supply line becomes the voltage VOUTM, and the voltage level is held by the storage capacitor CsL.

  In the high-potential-side power supply voltage generation circuit 142 and the low-potential-side power supply voltage generation circuit 144 having such a configuration, control is performed so that the charge clock is stopped or its frequency is reduced in accordance with the line value or a change amount thereof. Thus, the supply capability control of the common electrode voltage VCOM is realized by changing the voltage supply capability of the high potential side voltage VCOMH or the low potential side voltage VCOML.

  27A and 27B show configuration examples for realizing charge clock control of the power supply voltage generation circuit 140 in FIG.

  FIG. 27A shows a configuration in which the mask control of the original clock CKO is performed by the mask signal MASK generated based on the above-described line value or its change. In this case, the operation of the charge clock CK or its stop is controlled by the mask signal MASK.

  FIG. 27B shows a configuration in which the frequency reduction control of the charge clock CK is performed by the select signal SELC generated based on the line value or its change. The frequency divider DIV divides the frequency of the original clock CKO by 1 (S is a number of 2 or more). Then, one of the output of the original clock CKO and the frequency divider DIV selected based on the select signal SELC is output as the charge clock CK.

  Next, configuration examples of the VCOMH generation circuit 110 and the VCOML generation circuit 120 will be described.

  FIG. 28 shows a circuit diagram of a configuration example of the VCOMH generation circuit 110 of FIG.

  The VCOMH generation circuit 110 includes a differential unit OP1 and an output unit OD1 that constitute a first operational amplifier.

  The differential part OP1 includes a current mirror circuit CM1, a differential transistor pair DT1, and a current source CS1. The current mirror circuit CM1 includes P-type transistors PT1 and PT2 whose source is supplied with the power supply voltage VOUT. The gates of the transistors PT1 and PT2 are connected to each other, and the gate and drain of the transistor PT1 are connected.

  Differential transistor pair DT1 includes N-type transistors NT1 and NT2. The output voltage VCOMH of the output unit OD1 is supplied to the gate of the transistor NT1. The high potential side input voltage LEVINP is supplied to the gate of the transistor NT2. The drain of the transistor NT1 is connected to the drain of the transistor PT1. The drain of the transistor NT2 is connected to the drain of the transistor PT2.

  The current source CS1 is inserted between the sources of the N-type transistors NT1 and NT2 and the power supply line to which the power supply voltage VSS is supplied. In such a current source CS1, each of the two N-type transistors NT3 and NT4 is connected in parallel. Slew rate control signals VREFN1 and VREFN2 are supplied to the gates of the N-type transistors NT3 and NT4. Accordingly, the current value of the current source CS1 is controlled according to the slew rate control signals VREFN1 and VREFN2.

  The output unit OD1 includes a P-type drive transistor PDT1 and an N-type current source transistor NS1. The high potential side power supply voltage VOUT is supplied to the source of the P-type drive transistor PDT1. The low potential side power supply voltage VSS is supplied to the source of the N-type current source transistor NS1. The voltage of the connection node between the transistor NT2 and the transistor PT2 is supplied to the gate of the P-type drive transistor PDT1. A drive current source control signal REFN is supplied to the gate of the N-type current source transistor NS1. The drain of the P-type drive transistor PDT1 and the drain of the N-type current source transistor NS1 are connected, and this drain voltage becomes the output voltage VCOMH.

  The output unit OD1 is provided with boost P-type drive transistors PBT1 and PBT2 connected in series in parallel with the P-type drive transistor PDT1. More specifically, the boost P-type drive transistors PBT1 and PBT2 are connected in parallel with the P-type drive transistor PDT1 when the current drive capability control signal BOOSTP is at the L level. Thereby, according to the current drive capability control signal BOOSTP, the capability of flowing current to the output can be enhanced.

  Further, the VCOMH generation circuit 110 may include a bypass switch BPSW1 that bypasses the input and output of the differential unit OP1. The high potential side voltage VCOMH can be set to the high potential side input voltage LEVINP by making the bypass switch BPSW1 conductive by a bypass control signal BPC1 that performs on / off control of the bypass switch BPSW1. At this time, it is desirable to stop the currents of the current source CS1 and the N-type current source transistor NS1 by the slew rate control signals VREFN1 and VREFN2 and the drive current source control signal REFN.

  The high potential side input voltage LEVINP, the slew rate control signals VREFN1, VREFN2, the current drive capability control signal BOOSTP, the drive current source control signal REFN, and the bypass control signal BPC1 input to the VCOMH generation circuit 110 as described above are shown in FIG. Is supplied from the power supply control circuit 150.

  With respect to the VCOMH generation circuit 110 having such a configuration, let us consider a case where the bypass switch BPSW1 is non-conductive, the boost P-type drive transistor PBT1 is non-conductive, and the high-potential side input voltage LEVINP is higher than the output voltage VCOMH. In this case, since the impedance of the transistor NT1 is larger than that of the transistor NT2, the gate voltages of the transistors PT1 and PT2 are increased, and the impedance of the transistor PT2 is increased. For this reason, the gate voltage of the P-type drive transistor PDT1 decreases, and the P-type drive transistor PDT1 is turned on. Therefore, the output voltage VCOMH increases.

  Conversely, consider the case where the high potential side input voltage LEVINP is lower than the output voltage VCOMH. In this case, since the impedance of the transistor NT1 is smaller than that of the transistor NT2, the gate voltages of the transistors PT1 and PT2 are lowered and the impedance of the transistor PT2 is reduced. For this reason, the gate voltage of the P-type drive transistor PDT1 rises, and the P-type drive transistor PDT1 is turned off. Therefore, the output voltage VCOMH is lowered.

  As a result of the above operation, the VCOMH generation circuit 110 shifts to an equilibrium state in which the high potential side input voltage LEVINP and the output voltage VCOMH are substantially equal.

  At this time, in the differential unit OP1, as the current value of the current source CS1 is increased, the reaction speed of each transistor constituting the current mirror circuit CM1 and the differential transistor pair DT1 can be increased. Therefore, the VCOMH generation circuit The slew rate of 110 can be increased. Here, the slew rate can be said to be a value indicating the maximum gradient of the output voltage per unit time.

  In addition, in the output unit OD1, the boost P-type drive transistor PBT1 is turned on, so that the ability to flow current to the node to which the output voltage VCOMH is supplied can be enhanced.

  FIG. 29 shows a circuit diagram of a configuration example of the VCOML generation circuit 120 of FIG.

  The VCOML generation circuit 120 includes a differential unit OP2 and an output unit OD2 that constitute a second operational amplifier.

  The differential part OP2 includes a current mirror circuit CM2, a differential transistor pair DT2, and a current source CS2. The current mirror circuit CM2 includes N-type transistors NT11 and NT12 whose source is supplied with the power supply voltage VOUTM. The gates of the transistors NT11 and NT12 are connected to each other, and the gate and drain of the transistor NT11 are connected.

  The differential transistor pair DT2 includes P-type transistors PT11 and PT12. The output voltage VCOML of the output unit OD2 is supplied to the gate of the transistor PT11. The low potential side input voltage LEVINN is supplied to the gate of the transistor PT12. The drain of the transistor PT11 is connected to the drain of the transistor NT11. The drain of the transistor PT12 is connected to the drain of the transistor NT12.

  The current source CS2 is inserted between the sources of the P-type transistors PT11 and PT12 and the power supply line to which the power supply voltage VSS is supplied. In such a current source CS2, each of the two P-type transistors PT13 and PT14 is connected in parallel. Slew rate control signals VREFP1 and VREFP2 are supplied to the gates of the P-type transistors PT13 and PT14. Accordingly, the current value of the current source CS2 is controlled according to the slew rate control signals VREFP1 and VREFP2.

  The output unit OD2 includes an N-type drive transistor NDT1 and a P-type current source transistor PS1. A power supply voltage VOUTM is supplied to the source of the N-type drive transistor NDT1. The power supply voltage VSS is supplied to the source of the P-type current source transistor PS1. The voltage of the connection node between the transistor PT12 and the transistor NT12 is supplied to the gate of the N-type drive transistor NDT1. A drive current source control signal REFP is supplied to the gate of the P-type current source transistor PS1. The drain of the N-type drive transistor NDT1 and the drain of the P-type current source transistor PS1 are connected, and this drain voltage becomes the output voltage VCOML.

  The output unit OD2 is provided with boost N-type drive transistors NBT1 and NBT2 connected in series in parallel with the N-type drive transistor NDT1. More specifically, boost N-type drive transistors NBT1 and NBT2 are connected in parallel with N-type drive transistor NDT1 when current drive capability control signal BOOSTN is at the H level. As a result, the ability to draw current from the output can be increased in accordance with the current drive capability control signal BOOSTN.

  Further, the VCOML generation circuit 120 can be provided with a bypass switch BPSW2 that bypasses the input and output of the differential section OP2. The low potential side voltage VCOML can be set to the low potential side input voltage LEVINN by making the bypass switch BPSW2 conductive by the bypass control signal BPC2 for performing on / off control of the bypass switch BPSW2. At this time, it is desirable to stop the currents of the current source CS2 and the P-type current source transistor PS1 by the slew rate control signals VREFP1 and VREFP2 and the drive current source control signal REFP.

  The low potential side input voltage LEVINN, the slew rate control signals VREFP1, VREFP2, the current drive capability control signal BOOSTN, the drive current source control signal REFP, and the bypass control signal BPC2 input to the VCOML generation circuit 120 as described above are shown in FIG. Is supplied from the power supply control circuit 150.

  With respect to the VCOML generation circuit 120 having such a configuration, let us consider a case where the bypass switch BPSW2 is non-conductive, the boost N-type drive transistor NBT1 is non-conductive, and the low-potential side input voltage LEVINN is higher than the output voltage VCOML. In this case, since the impedance of the transistor PT11 is smaller than that of the transistor PT12, the gate voltages of the transistors NT11 and NT12 are increased, and the impedance of the transistor NT12 is decreased. For this reason, the gate voltage of the N-type drive transistor NDT1 decreases, and the N-type drive transistor NDT1 is turned off. Therefore, the output voltage VCOML increases.

  Conversely, consider a case where the low potential side input voltage LEVINN is lower than the output voltage VCOML. In this case, since the impedance of the transistor PT11 is larger than that of the transistor PT12, the gate voltages of the transistors NT11 and NT12 are lowered and the impedance of the transistor NT12 is increased. Therefore, the gate voltage of the N-type drive transistor NDT1 rises, and the N-type drive transistor NDT1 is turned on. Therefore, the output voltage VCOML is lowered.

  As a result of the above operation, the VCOML generation circuit 120 shifts to an equilibrium state in which the low potential side input voltage LEVINN and the output voltage VCOML are substantially equal.

  At this time, in the differential unit OP2, as the current value of the current source CS2 is increased, the reaction speed of each transistor constituting the current mirror circuit CM2 and the differential transistor pair DT2 can be increased. Therefore, the VCOML generation circuit The slew rate of 120 can be increased.

  In the output unit OD2, the boosting N-type drive transistor NBT1 is turned on, so that the ability to draw current from the node to which the output voltage VCOML is supplied can be enhanced.

2.4.1 Power Supply Capacity Setting Register The power supply control circuit 150 controls the supply capacity of the common electrode voltage VCOM as described above based on the set value of the power supply capacity setting register 160.

  FIG. 30 shows an example of the power supply capability setting register 160 of FIG.

  FIG. 30 shows an example in which the gate signals of the first and second auxiliary transistors CTrp1, CTrp2, CTrn1, CTrn2, the slew rate control signals VREFN1, VREFN2, the offset of the high potential side input voltage LEVINP, and the charge clock CK are controlled. ing. The same applies to other control signals and the like, and all the control signals may be set or only a part thereof may be set.

  The power supply capability setting register 160 holds control information for generating a control signal for performing the supply capability control of the common electrode voltage VCOM in association with the line value from the data driver 30. Such control information is set by the host or the display controller.

  In FIG. 30, the control information is stored in association with the line value, but the control information may be held in association with the change in the line value.

  FIG. 31 shows another example of the power supply capacity setting register 160.

  In FIG. 31, the control information set in the power supply capability setting register 160 is information specifying the on timing and the off timing of the control signal for performing the supply capability control of the common electrode voltage VCOM.

  FIG. 32 is an explanatory diagram of control information of the power supply capability setting register of FIG.

  For example, as control information, an ON timing designated by the number of dot clocks DCK based on the falling edge of the horizontal synchronization signal HSYNC, and an OFF timing designated by the number of clocks of the dot clock DCK based on the falling edge, Can be included.

  In FIG. 31, the control information is stored in association with the line value, but the control information may be held in association with the change in the line value.

  By doing so, it is possible to control the supply capability of the common electrode voltage VCOM only during a period obtained based on the line value or its change.

  In the power supply capability setting register as described above, the type of control signal to be controlled and the control information including the time are determined by the load on the counter electrode of the LCD panel 20 and the output configuration of the data driver 30.

2.5 First Configuration Example The first configuration example is an example of the supply capability control of the counter electrode voltage VCOM when line inversion driving is performed. In the first configuration example, the line value is received from the data driver 30 to control the supply capability of the common electrode voltage VCOM.

  FIG. 33 shows a block diagram of a configuration example of the power supply control circuit in the first configuration example. This power supply control circuit corresponds to the power supply control circuit 150 of FIG.

  When line inversion driving is performed, the supply capability control of the counter electrode voltage VCOM according to the line value or the like is made different between the voltage change period immediately after the counter electrode voltage VCOM changes and the subsequent gradation output period.

  Therefore, the power supply capability setting register has control information for the voltage change period and the gradation output period at the positive polarity, and for the voltage change period and the gradation output period at the negative polarity. Then, the line value for the voltage change period and the line value for the gradation output period are respectively acquired from the data driver 30, and the supply capability of the common electrode voltage VCOM is controlled based on the acquired line value.

  In FIG. 33, the power supply capacity setting registers include first and second voltage change period setting registers REG1, REG2, first and second gradation output period setting registers REG3, REG4, current source setting register REG5, A VCOM setting register REG6 is included. For the voltage change period at the time of positive polarity, the setting information of the first voltage change period setting register REG1 is used. For the gradation output period at the time of positive polarity, the setting information of the first gradation output period setting register REG3 is used. For the voltage change period at the negative polarity, the setting information of the second voltage change period setting register REG2 is used. For the gradation output period at the negative polarity, the setting information in the second gradation output period setting register REG4 is used.

  The current source setting register REG5 holds control information for generating the drive current source control signals REFN and REFP. That is, the DAC 1 generates a signal having a voltage level corresponding to the control information in the current source setting register REG5 and outputs it as drive current source control signals REFN and REFP.

  The VCOM setting register REG6 holds control information for generating the high potential side input voltage LEVINP and the low potential side input voltage LEVINN. After the offset value is added to this control information, the high potential side input voltage LEVINP and the low potential side input voltage LEVINN are generated. This offset value is also generated according to the line value as shown in FIG.

  The control information of the first and second voltage change period setting registers REG1, REG2, first and second gradation output period setting registers REG3, REG4, current source setting register REG5, VCOM setting register REG6 is the host or Set by the display controller. The host or display controller outputs address data AD and chip select CS that specify one of the registers. When the chip select CS is active, the address decoder ADEC sets the access data D from the host or the display controller for one of the registers specified based on the address data AD. This access data D is control information.

  In the first configuration example, the line value LD2 for the voltage change period and the line value LD1 for the gradation output period are separately supplied from the data driver 30.

  FIG. 34 shows an example of line values for each period supplied from the data driver 30.

  In the voltage change period, the line value is the previous line value. The previous line value is a line value in the horizontal scanning period immediately before the horizontal scanning period. The line value is obtained as shown in FIG. In this period, the voltage is not yet applied to the pixel electrode based on the line data in the horizontal scanning period, and the line value in the horizontal scanning period is not considered.

  On the other hand, in the gradation output period, the line value is obtained based on the value obtained by adding the current line value to the value obtained by adding the correction value corresponding to the previous line value. Here, the current line value is a line value in the horizontal scanning period.

  FIG. 35 is an explanatory diagram of the correction value corresponding to the previous line value.

  If the previous line value is x, the correction value corresponds to f (x) as shown in FIG. This correction value can be said to be a value that takes into account the amount of charge remaining in the horizontal scanning period since the charges supplied to the pixel electrodes or data lines in the previous horizontal scanning period cannot be removed. This residual charge amount can be associated with the voltage applied to the pixel electrode in the immediately preceding horizontal scanning period. Therefore, the correction value can be associated with the previous line value.

In FIG. 35, f (x) is linearly approximated with the previous line values as a ₁ and a ₂ as boundaries. The previous line value a ₁ is determined according to the gradation characteristics of the LCD panel 20. In general, in this gradation characteristic, a voltage change per gradation is large in a region where the gradation value is large and a region where the gradation value is small, and the voltage change is small in an intermediate region of the gradation value. The previous line value a ₁ is a value corresponding to a boundary between a region where the gradation value having a large voltage change is small and an intermediate region where the voltage change is small in the gradation characteristic.

On the other hand, pre-line value a ₂ is a value corresponding to the voltage is clamped by the diode or the like for output protection of the data driver 30 for driving the data lines. That is, a voltage higher than the voltage generated by the gradation data corresponding to the previous line value a _2, since the resulting current flows through the diode or the like, with different slope of the linear approximation.

  In FIG. 33, the line value LD2 for the voltage change period is supplied to the first and second voltage change period control information generation units GEN1 and GEN2. The first voltage change period control information generation unit GEN1 extracts control information corresponding to the line value LD2 from the control information in the first voltage change period setting register REG1. The second voltage change period control information generation unit GEN2 extracts control information corresponding to the line value LD2 from the control information in the first voltage change period setting register REG2.

  Based on the polarity inversion signal POL from the data driver 30, the output of the first voltage change period control information generation unit GEN1 is selected from the selector SEL1 at the positive polarity, and for the second voltage change period at the negative polarity. The output of the control information generation unit GEN2 is selected.

  The line value LD1 for the gradation output period is supplied to the first and second gradation output period control information generation units GEN3 and GEN4. The first gradation output period control information generation unit GEN3 extracts control information corresponding to the line value LD1 from the control information in the first gradation output period setting register REG3. The second gradation output period control information generation unit GEN4 extracts control information corresponding to the line value LD1 from the control information in the second gradation output period setting register REG4.

  Based on the polarity inversion signal POL, the selector SEL2 selects the output of the first gradation output period control information generation unit GEN3 at the positive polarity, and generates the second gradation output period control information at the negative polarity. The output of the part GEN4 is selected.

  The counter COUT increments a counter value initialized by the edge of the horizontal synchronization signal HSYNC or the edge of the reset signal XRES in synchronization with the dot clock DCK.

  The comparator CMP1 compares the control information selected by the selector SEL1 with the counter value, and outputs a pulse when they match. The comparator CMP2 compares the control information selected by the selector SEL2 with the counter value, and outputs a pulse when they match. Then, the set / reset flip-flop is set or reset based on the logical sum operation result of both pulses. The output of the set / reset flip-flop is subjected to voltage level conversion by a level shifter and then output as various control signals for realizing the supply capacity control of the common electrode voltage VCOM.

  In FIG. 33, only the configuration for generating one control signal is shown, but the same configuration is provided for each control signal for realizing the supply capability control of the common electrode voltage VCOM.

  In FIG. 33, period designation information for designating the voltage change period and the gradation output period for each polarity includes, for example, first and second voltage change period setting registers REG1, REG2, first and second gradation outputs. It is held in one of the period setting registers REG3 and REG4. Then, the period specifying information in the output of the set / reset flip-flop is supplied to the selector SEL3. The selector SEL3 is supplied with control information for changing an offset value for changing the high potential side voltage VCOMH and the low potential side voltage VCOML from the selectors SEL1 and SEL2. The selector SEL3 outputs any control information based on the period designation information.

  This control information is added to the control information in the VCOM setting register REG6 in the adder ADD. The DAC 2 generates a signal having a voltage level corresponding to the addition result of the adder ADD, and outputs the signal as a high potential side input voltage LEVINP and a low potential side input voltage LEVINN. By doing so, the high-potential side input voltage LEVINP or the low-potential side input voltage LEVINN can be changed according to the line value or its change, and as a result, the voltage level of the common electrode voltage VCOM can be changed. it can.

  The polarity inversion signal POL is supplied to the switching timing generation circuit SWC. The switching timing generation circuit SWC generates gate signals INP and INN that change at the timing shown in FIG. 14 based on the polarity inversion signal POL, and outputs the gate signals INP and INN to the switching circuit 130 after voltage level conversion.

  FIG. 36 is an explanatory diagram of an operation example in the first configuration example.

  FIG. 36 shows an example of line inversion driving in which polarity inversion is performed every horizontal scanning period.

When the common electrode voltage VCOM changes to the H level, a voltage change period is started. The line value LD2 of this period and _{A 0.} A ₀ is a line value (previous line value) in the horizontal scanning period immediately before the counter electrode voltage VCOM changes from the L level to the H level. Therefore, among the control information of the power supply capability setting register 160, controls the supply capability of the high-potential-side voltage VCOMH based on the control information line value corresponds to A _0. This supply capacity control includes at least one of the above-described controls.

In the subsequent gradation output period, (B ₀ + f (A ₀ )) is input as the line value LD1. Here, B ₀ is a line value in the horizontal scanning period. Therefore, the supply capability control of the high potential side voltage VCOMH is performed based on the control information corresponding to the line value (B ₀ + f (A ₀ )) in the control information of the power supply capability setting register 160. This supply capacity control includes at least one of the above-described controls.

When the counter electrode voltage VCOM changes to the L level, the voltage change period starts again. As line value LD2 of this period, the preceding line value B ₀ is input. Accordingly, the supply capability control of the low potential side voltage VCOML is performed based on the control information corresponding to the line value B ₀ in the control information of the power supply capability setting register 160. This supply capacity control includes at least one of the above-described controls.

In the subsequent gradation output period, (B ₁ + f (B ₀ )) is input as the line value LD1. Here, B ₁ is a line value in the horizontal scanning period. Therefore, the supply capability control of the low potential side voltage VCOML is performed based on the control information corresponding to the line value (B ₁ + f (B ₀ )) in the control information of the power supply capability setting register 160. This supply capacity control includes at least one of the above-described controls.

2.6 Second Configuration Example The second configuration example is an example of the supply capability control of the common electrode voltage VCOM when performing field inversion driving.

  FIG. 37 shows a block diagram of a configuration example of the power supply control circuit in the second configuration example. This power supply control circuit corresponds to the power supply control circuit 150 in FIG. However, in FIG. 37, the same parts as those in FIG.

  Therefore, in FIG. 37, the control information for the voltage change period during the positive polarity and the negative polarity is omitted from the power supply capability setting register shown in FIG. Then, the line value LD1 for the gradation output period is acquired from the data driver 30, and the supply capability of the common electrode voltage VCOM is controlled based on the acquired line value.

  When performing field inversion driving, the supply capability control of the counter electrode voltage VCOM is performed only in the gradation output period according to the line value and the like. In the field inversion driving, the polarity of the counter electrode voltage VCOM does not change between the immediately preceding horizontal scanning period and the horizontal scanning period. Therefore, the line value can be a value obtained by subtracting the previous line value from the current line value, or a value obtained by correcting the subtracted value.

  The rest is the same as the control information for the gradation output period in FIG. Therefore, detailed description is omitted.

  FIG. 38 is an explanatory diagram of an operation example in the second configuration example.

A grayscale output period starts after a while after the common electrode voltage VCOM changes to the H level. In this gradation output period, (C ₀ + f (A ₀ )) is input as the line value LD1. Here, C ₀ is a line value in the horizontal scanning period. A ₀ is the previous line value. Therefore, the supply capability control of the high potential side voltage VCOMH is performed based on the control information corresponding to the line value (C ₀ + f (A ₀ )) in the control information of the power supply capability setting register 160. This supply capacity control includes at least one of the above-described controls.

The next horizontal scanning period is also a gradation output period. Therefore, (C ₁ -C ₀ ) is input as the line value LD1. Here, C ₁ is a line value in the horizontal scanning period. Therefore, the supply capability control of the high potential side voltage VCOMH is performed based on the control information corresponding to the line value (C ₁ -C ₀ ) in the control information of the power supply capability setting register 160. This supply capacity control includes at least one of the above-described controls.

  Similarly, supply capability control of the high potential side voltage VCOMH is performed in each gradation output period in the vertical scanning period.

When the next vertical scanning period starts, the counter electrode voltage VCOM changes to the L level. In the gradation output period, (E ₀ + f (D ₀ )) is input as the line value LD1. Here, E ₀ is a line value in the horizontal scanning period. D ₀ is the previous line value. Therefore, the supply capability of the low potential side voltage VCOML is controlled based on the control information corresponding to the line value (E ₀ + f (D ₀ )) among the control information of the power supply capability setting register 160. This supply capacity control includes at least one of the above-described controls.

  Thereafter, similarly, the supply capability of the high potential side voltage VCOMH is controlled in each gradation output period in the vertical scanning period.

  In the voltage change period in which the counter electrode voltage VCOM changes, the control may be performed in the same manner as the voltage change period control during the line inversion driving described with reference to FIGS.

  FIG. 36 shows an example in which polarity inversion is performed for each horizontal scanning period. However, when polarity inversion is performed for each of a plurality of horizontal scanning periods, the field shown in FIG. What is necessary is just to perform supply capability control similarly to inversion drive.

3. Electronic Device FIG. 39 shows a block diagram of a configuration example of the electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 39, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  Mobile phone 900 includes LCD panel 20. The LCD panel 20 is driven by a data driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of scanning lines, a plurality of source lines, and a plurality of pixels.

  The display controller 38 is connected to the data driver 30 and the gate driver 32, and supplies RGB data gradation data to the data driver 30.

  The power supply circuit 100 is connected to the data driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. The counter electrode voltage VCOM is supplied to the counter electrode of the LCD panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 causes the data driver 30 and the gate driver 32 to display on the LCD panel 20 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the LCD panel 20 based on operation information from the operation input unit 970.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation implementation is possible within the range of the summary of this invention. In the present embodiment, the power supply circuit that supplies the voltage to the counter electrode has been described. However, the present invention is not limited to the circuit that supplies the voltage to the counter electrode.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a block diagram of a configuration example of a liquid crystal display device to which a power supply circuit according to an embodiment is applied. The block diagram of the other structural example of the liquid crystal display device of FIG. 3A and 3B are explanatory diagrams of polarity inversion driving. 4A and 4B are explanatory diagrams of polarity inversion driving. Explanatory drawing at the time of using line inversion drive and common inversion drive together. 6A and 6B are diagrams for explaining a difference in power consumption according to gradation data. The figure of the structural example of the power supply capability control system containing the power supply circuit in this embodiment. The block diagram of the structural example of the data driver in this embodiment. FIG. 9 is an operation explanatory diagram of a main part of the data driver of FIG. 8. The figure explaining the gradation characteristic of a general LCD panel. The figure explaining an example of operation | movement of a voltage value converter circuit. The block diagram of the structural example of the voltage value conversion circuit of FIG. The block diagram of the circuit structural example of the voltage value conversion circuit of FIG. The figure which shows the structural example of the gradation designation | designated information of FIG. Explanatory drawing of the outline | summary of operation | movement of the circuit structural example of the voltage value conversion circuit of FIG. FIG. 14 is a block diagram of a detailed circuit configuration example of the voltage value conversion circuit of FIG. 13. FIG. 17 is a circuit diagram of a configuration example of a block GREGq in FIG. 16. FIG. 17 is a circuit diagram of a configuration example of a block ADDRq in FIG. 16. Circuit diagram of configuration example of block ENCq of FIG. The figure which shows the structural example of the data showing the conversion voltage value per dot. The figure explaining an example of the arithmetic processing of the line value arithmetic circuit of FIG. The block diagram which shows the structural example of the power supply circuit of FIG. The figure which shows an example of the timing of the gate signal of FIG. FIG. 23 is a schematic explanatory diagram of an operation example of the power supply voltage generation circuit of FIG. 22. FIG. 23 is a circuit diagram of a configuration example of a power supply voltage generation circuit in FIG. 22. FIG. 5 is a timing chart for explaining the operation of the high-potential-side power supply voltage generation circuit. 27A and 27B are diagrams illustrating configuration examples for realizing charge clock control of the power supply voltage generation circuit of FIG. FIG. 23 is a circuit diagram of a configuration example of the VCOMH generation circuit of FIG. 22. FIG. 23 is a circuit diagram of a configuration example of a VCOML generation circuit in FIG. 22. The figure which shows an example of a power supply capability setting register. The figure which shows the other example of a power supply capability setting register | resistor. Explanatory drawing of the control information of the power supply capability setting register | resistor of FIG. The block diagram of the structural example of the power supply control circuit in a 1st structural example. The figure which shows an example of the line value of each period supplied from a data driver. Explanatory drawing of the correction value corresponding to the previous line value. Explanatory drawing of the operation example in a 1st structural example. The block diagram of the structural example of the power supply control circuit in a 2nd structural example. Explanatory drawing of the operation example in a 2nd structural example. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal display device, 20 LCD panel, 30 data driver,
32 gate driver, 38 display controller, 100 power supply circuit,
110 VCOMH generation circuit, 120 VCOML generation circuit, 130 switching circuit,
140 power supply voltage generation circuit, 142 high potential side power supply voltage generation circuit,
144 low potential side power supply voltage generation circuit, 150 power supply control circuit,
160 power supply capacity setting register, 200 data latch,
210 line latch, 220 L / S, 230 reference voltage generation circuit,
240 DAC, 250 drive circuit, 258 voltage value conversion circuit,
260 line value arithmetic circuit, 270 line value output unit, CK charge clock,
CNTH, CNTL voltage generation control signal,
CTrp1, CTrp2 first auxiliary transistor,
CTrn1, CTrn2 Second auxiliary transistor INP, INN gate signal,
OTrp1 P-type output MOS transistor,
OTrn1 N-type output MOS transistor, POL polarity inversion signal,
TRP1, TRP2, TRN1, TRN2 gate signal, VCOM counter electrode voltage,
VCOMH high potential side voltage, VCOMML low potential side voltage,
VDD, VOUT High potential side power supply voltage, VOUTM, VSS Low potential side power supply voltage

Claims (23)

A power supply circuit for supplying a counter electrode voltage to the counter electrode of an electro-optical device including a pixel electrode and a counter electrode,
A high potential side voltage generating circuit including a first operational amplifier and generating a high potential side voltage;
A low potential side voltage generation circuit including a second operational amplifier and generating a low potential side voltage;
A switching circuit that alternately outputs one of the high potential side voltage and the low potential side voltage as the counter electrode voltage ,
In the electro-optical device, the high-potential-side voltage generation circuit has a high-voltage-side voltage generation circuit according to a total value obtained by adding the converted voltage values obtained by converting the grayscale data corresponding to the number of pixels of one scanning line according to given grayscale characteristics. Changing at least one of current drive capability, output voltage of the high potential side voltage generation circuit, current drive capability of the low potential side voltage generation circuit, and output voltage of the low potential side voltage generation circuit;
Power circuit according to claim Rukoto changing at least one of the first current driving capability and the slew rate of the operational amplifier in response to the total value. In claim 1,
A first auxiliary transistor of a first conductivity type, the source of which is supplied with the high-potential-side power supply voltage of the high-potential-side voltage generation circuit and the drain of which is electrically connected to the output of the switching circuit;
A power supply circuit that controls a gate voltage of the first auxiliary transistor in accordance with the total value. In claim 1 or 2,
A second auxiliary transistor of a second conductivity type, the source of which is supplied with the low-potential-side power supply voltage of the low-potential-side voltage generation circuit and the drain of which is electrically connected to the output of the switching circuit;
A power supply circuit that controls a gate voltage of the second auxiliary transistor in accordance with the total value. In any one of Claims 1 thru | or 3 ,
The first operational amplifier generates the high potential side voltage based on a first input voltage,
The power supply circuit according to claim 1, wherein the first input voltage changes in accordance with the sum value. In any one of Claims 1 thru | or 4 ,
A power supply circuit that stops or restricts an operating current of the first operational amplifier according to the total value and electrically connects an input and an output of the first operational amplifier. In any one of Claims 1 thru | or 5 ,
Including a first charge pump circuit that generates a high-potential-side power supply voltage of the high-potential-side voltage generation circuit by a charge pump operation synchronized with a first charge clock;
A power supply circuit that stops or reduces the frequency of the first charge clock according to the total value. In any one of Claims 1 thru | or 6 .
The power supply circuit according to claim 1, wherein at least one of a current driving capability and a slew rate of the second operational amplifier is changed in accordance with the total value. In any one of Claims 1 thru | or 7 ,
The second operational amplifier generates the low potential side voltage based on a second input voltage,
The power supply circuit according to claim 1, wherein the second input voltage changes according to the sum value. In any one of Claims 1 thru | or 8 .
A power supply circuit characterized by stopping or limiting an operating current of the second operational amplifier according to the total value, and electrically connecting an input and an output of the second operational amplifier. In any one of Claims 1 thru | or 9 ,
A second charge pump circuit that generates a low potential side power supply voltage of the low potential side voltage generation circuit by a charge pump operation synchronized with a second charge clock;
A power supply circuit that stops or reduces the frequency of the second charge clock according to the total value. A power supply circuit for supplying a voltage to the counter electrode of an electro-optical device including a pixel electrode and a counter electrode,
Including a circuit that alternately outputs one of a high-side voltage and a low-side voltage generated by a circuit including an operational amplifier;
In accordance with a total value obtained by adding converted voltage values obtained by converting each gradation data of gradation data corresponding to the number of pixels of one scanning line in the electro-optical device according to given gradation characteristics, the high potential side Changing at least one of a current driving capability and an output voltage of a circuit that alternately outputs one of a voltage and a low-side voltage ;
Power circuit according to claim Rukoto changing at least one of the current driving capability and the slew rate of the operational amplifier in response to the total value. In any one of Claims 1 thru | or 11 ,
The power supply circuit, wherein the current driving capability or the output voltage is changed only during a period obtained based on the total value. In any one of Claims 1 to 12 ,
A power supply circuit that changes the current driving capability or the output voltage in accordance with a change in the total value of the horizontal scanning period with respect to the total value of the immediately preceding horizontal scanning period instead of the total value. In claim 13 ,
A power supply circuit characterized by changing the current driving capability or the output voltage only during a period corresponding to a change in the total value of the horizontal scanning period with respect to the total value of the immediately preceding horizontal scanning period. In claim 13 or 14 ,
When performing field inversion driving for switching the polarity of the counter electrode voltage with respect to a given reference potential for each vertical scanning period,
The change amount is obtained based on a value obtained by subtracting the total value of the immediately preceding horizontal scanning period from the total value of the horizontal scanning period.
When performing line inversion driving for switching the voltage polarity of the counter electrode with respect to a given reference potential every horizontal scanning period,
The power supply circuit, wherein the change amount is obtained based on a value obtained by adding a correction value corresponding to the total value to the total value of the horizontal scanning period. In any one of Claims 1 thru | or 15 ,
When the gradation data of each dot is j (j is an integer of 2 or more) bits,
The total value is
A value obtained by adding a conversion voltage value obtained by converting upper k (k <j, k is a natural number) bit data of gradation data corresponding to the number of pixels of one scanning line according to given gradation characteristics. A power supply circuit characterized by the above. In claim 16 ,
A power supply circuit, wherein k is 1. In any one of Claims 1 thru | or 15 ,
When the value obtained by adding the converted voltage values is p (p is an integer of 2 or more) bits,
The total value is
The power supply circuit according to claim 1, wherein the power supply circuit is a value represented by upper q (q <p, q is a natural number) bits of a value obtained by adding the converted voltage values. In any one of Claims 1 thru | or 18 .
The power supply circuit according to claim 1, wherein the number of bits of the gradation data is smaller than the number of bits of data representing the converted voltage value. A voltage value conversion circuit that generates a converted voltage value obtained by converting the gradation data of each dot corresponding to the applied voltage of the pixel electrode according to a given gradation characteristic;
A total value calculation circuit that generates the total value based on the converted voltage values for the number of pixels of one scanning line;
A driving circuit for supplying a driving voltage corresponding to the gradation data to a data line electrically connected to the pixel electrode;
Display driver, characterized in that it comprises a power supply circuit according to any one of claims 1 to 19 to vary the current driving capability to the output voltage by using the sum value generated by the total value calculation circuit. A plurality of scan lines;
Multiple data lines,
A plurality of pixel electrodes each of which is specified by one of the plurality of scanning lines and one of the plurality of data lines;
A counter electrode opposed to the plurality of pixel electrodes with an electro-optic material interposed therebetween;
A display driver for driving the plurality of data lines;
Electro-optical device which comprises a power supply circuit according to any one of claims 1 to 19 outputs the high-potential-side voltage and the low-potential-side voltage alternately. An electronic apparatus comprising a power supply circuit according to any one of claims 1 to 19. A power supply circuit for supplying a voltage to the counter electrode of an electro-optical device including a pixel electrode and a counter electrode,
A high potential side voltage generating circuit including a first operational amplifier and generating a high potential side voltage;
A low potential side voltage generation circuit including a second operational amplifier and generating a low potential side voltage;
A switching circuit that alternately outputs one of the high potential side voltage and the low potential side voltage,
In accordance with the value based on the gradation data for the number of pixels of one scanning line in the electro-optical device, the current drive capability of the high potential side voltage generation circuit, the output voltage of the high potential side voltage generation circuit, the low potential side Changing at least one of the current driving capability of the voltage generation circuit and the output voltage of the low-potential side voltage generation circuit ;
Power circuit according to claim Rukoto changing at least one of the current driving capability and the slew rate of the one scan line of the in accordance with a value based on grayscale data for the number of pixels first operational amplifier.

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