JP2008083286A - Load measuring instrument, drive circuit, electro-optical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a load measuring instrument capable of measuring the load on a display panel to be driven, a driving circuit capable of suitably driving the display panel according to the load, and an electrooptical device and an electronic apparatus. <P>SOLUTION: The load measuring instrument for measuring the load on the display panel 12 includes a counter electrode driver 100, which supplies a counter electrode voltage VCOM to a counter electrode CE electrically connected to a counter electrode connecting point via a counter electrode connection point CEP provided to the display panel 12; and a panel load measuring unit 110, which receives a signal FBC for measurement through a connection point for counter electrode load measurement provided to the display panel 12 and electrically connected to the counter electrode CE and then finds the load on the display panel 12 by using the signal FBC for measurement. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a load measuring device, a drive circuit, an electro-optical device, and an electronic apparatus.

  Conventionally, as a liquid crystal display (LCD) panel (display panel in a broad sense, an electro-optical device in a broad sense) used for an electronic device such as a cellular phone, a simple matrix type LCD panel and a thin film transistor ( 2. Description of the Related Art An active matrix type LCD panel using a switching element such as a thin film transistor (hereinafter abbreviated as TFT) is known.

  The simple matrix method is easier to reduce power consumption than the active matrix method, but it is difficult to increase the number of colors and display a moving image. On the other hand, the active matrix method is suitable for multicolor and moving image display, but it is difficult to reduce power consumption.

  In a simple matrix type LCD panel and an active matrix type LCD panel, driving is performed so that an applied voltage to liquid crystal (electro-optical material in a broad sense) constituting a pixel is an alternating current. As such AC driving methods, line inversion driving and field inversion driving (frame inversion driving) are known. In line inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted every one or more scanning lines. In the field inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted for each field (for each frame).

  At that time, the voltage level applied to the pixel electrode is lowered by changing the counter electrode voltage (common voltage) supplied to the counter electrode (common electrode) facing the pixel electrode constituting the pixel in accordance with the inversion drive timing. Can be made.

When such AC driving is performed, an increase in power consumption accompanying charging / discharging of the liquid crystal is caused. Therefore, for example, in Patent Document 1, during inversion driving, the electric charge accumulated in the liquid crystal is initialized by short-circuiting the two electrodes sandwiching the liquid crystal, and the transition is made to the intermediate voltage of the voltage before the short-circuiting of the electrode, thereby reducing the consumption. A technique for achieving the above is disclosed. In Patent Document 2, a counter electrode is provided by applying a precharge potential to a source line in a first precharge period before writing to a pixel electrode and a second precharge period before switching of the counter electrode voltage. A technique for reducing power consumption by suppressing potential fluctuation of a source line at the time of voltage switching is disclosed.
JP 2002-244622 A JP 2004-354758 A

  However, the techniques disclosed in Patent Document 1 and Patent Document 2 have a problem that the power consumption reduction effect depends on the voltage applied to the source line. Therefore, there may be a case where the effect of reducing the charge amount for charging and discharging the counter electrode whose polarity is reversed cannot be expected so much. Further, in the technique disclosed in Patent Document 1, depending on the relationship between the voltage applied to the source line and the polarity of the counter electrode voltage, the amount of charge to be charged / discharged can be reduced by short-circuiting the two electrodes sandwiching the liquid crystal. There is a problem that the effect of lowering power consumption may be diminished. Therefore, when reusing the charge once supplied, it is desirable that the source line and the counter electrode can be driven while reliably reducing power consumption with a simple configuration.

  On the other hand, depending on the application field of the drive circuit, there is a case where priority should be given to reducing the chip size and mounting area of the drive circuit, etc. at the expense of a certain power consumption reduction effect. For example, this is a case where a customer (electronic device manufacturer) applies the drive circuit or the like to a product that places top priority on cost reduction of the drive circuit and the LCD panel including the drive circuit. As described above, it is desirable to provide a drive circuit or the like that can prioritize low power consumption or prioritize cost reduction according to the customer. In other words, with a simple configuration, we pursue low power consumption at the expense of a certain cost reduction effect (priority for low power consumption), or pursue cost reduction at the expense of a certain power consumption reduction effect. It is desirable to be able to (prioritize cost reduction). If such a drive circuit or the like can be provided, it means that one type of drive circuit satisfies various user requirements, and as a result, the manufacturing cost can be further reduced.

  Further, in the technique disclosed in Patent Document 1, since electric charges are reused by short-circuiting to equalize potentials, there is no means for driving a load, and the time required for reuse of electric charges is long. Become. For this reason, if the writing time of the pixel electrode given within one horizontal scanning period is shortened, there is a problem that the time for reusing charges becomes insufficient. In order to increase the writing time of the pixel electrode, for example, it is considered that a precharge technique as disclosed in Patent Document 2 is effective. However, as described above, according to the customer, There is no disclosure of a configuration of a drive circuit or the like that can prioritize lower power consumption or prioritize cost reduction.

  With the recent increase in the number of pixels in the LCD panel, the pixel writing period tends to be shortened, and it is desirable that the charge re-use time and precharge period are as short as possible. Accordingly, it is necessary to minimize the charge recycle time and precharge period according to the load such as the screen size of the LCD panel, the number of pixels, and manufacturing variations. Therefore, if the load on the LCD panel to be driven can be measured, the charge reuse time and precharge period can be optimized.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a load measuring device capable of measuring the load of a display panel to be driven, and to perform optimum driving according to the load. It is an object to provide a drive circuit, an electro-optical device, and an electronic apparatus that can be realized.

In order to solve the above problems, the present invention
A plurality of source lines, a plurality of gate lines, a plurality of switch elements each of which is specified by each source line and each gate line, a plurality of pixel electrodes each of which is connected to each of the switch elements, A load measuring device for measuring a load of a display panel including a counter electrode provided facing the plurality of pixel electrodes,
A counter electrode driver for supplying a counter electrode voltage to the counter electrode electrically connected to the counter electrode connection point via the counter electrode connection point provided on the display panel;
A panel load measurement unit that receives a measurement signal through a counter electrode load measurement connection point that is provided in the display panel and is electrically connected to the counter electrode, and obtains the load of the display panel using the measurement signal Related to a load measuring device.

  According to the present invention, since the load on the display panel to be driven can be measured by considering the load on the display panel by the load on the counter electrode, for example, the charge recycle time and the precharge period are optimized, It is not necessary to wastefully shorten the pixel writing time. As a result, it is possible to contribute to the provision of a drive circuit that reduces power consumption by optimizing the charge recycle time and the precharge period, and prevents image quality deterioration by securing a sufficient pixel writing time.

In the load measuring device according to the present invention,
The panel load measuring unit is
Based on the change timing of the counter electrode voltage, a load corresponding to the time required for the level of the measurement signal to reach a predetermined threshold can be obtained as the load of the display panel.

In the load measuring device according to the present invention,
The measurement signal from the counter electrode load measurement connection point provided on the display panel can be used so that the load on the counter electrode is maximized with reference to the counter electrode connection point.

  According to any one of the above-described inventions, the measurement signal can be reliably obtained by using the measurement signal from the common electrode load measurement connection point, and the load of the common electrode can be reliably obtained. become. As a result, the load on the display panel can be determined with high accuracy.

The present invention also provides
A load measuring device for measuring a load of a display panel including a plurality of source lines, a plurality of gate lines, and a plurality of pixels each pixel being specified by each source line and each gate line,
A source line driver for supplying a source voltage to a source line electrically connected to the source line connection point via a source line connection point provided on the display panel;
A panel load measuring unit which receives a measurement signal via a connection point for measuring a source load provided in the display panel and electrically connected to the source line, and obtains a load of the display panel using the measurement signal; Related to a load measuring device including

  According to the present invention, since the load on the display panel to be driven can be measured by considering the load on the display panel based on the load on the source line, for example, the charge recycle time and the precharge period are optimized, It is not necessary to wastefully shorten the pixel writing time. As a result, it is possible to reduce power consumption by optimizing the charge reuse time and the precharge period, and to prevent image quality deterioration by securing a sufficient pixel writing time.

In the load measuring device according to the present invention,
The panel load measuring unit is
Based on the change timing of the source voltage, a load corresponding to the time required for the level of the measurement signal to reach a predetermined threshold can be obtained as the load of the display panel.

In the load measuring device according to the present invention,
The measurement signal from the source load measurement connection point provided on the display panel can be used so that the load on the source line is maximized with reference to the source line connection point.

  According to any one of the above-described inventions, by using the measurement signal from the source load measurement connection point, the measurement signal can be reliably obtained, and the load of the counter electrode can be reliably obtained. Become. As a result, the load on the display panel can be determined with high accuracy.

The present invention also provides
A plurality of source lines, a plurality of gate lines, a plurality of switch elements each of which is specified by each source line and each gate line, a plurality of pixel electrodes each of which is connected to each of the switch elements, A drive circuit for driving a display panel including the plurality of pixel electrodes and a counter electrode provided to face the pixel electrode;
The load measuring device according to any one of the above, for obtaining a load on the display panel;
A source line driving unit that drives the plurality of source lines based on a gradation voltage corresponding to gradation data,
The source line driver is
The present invention relates to a drive circuit that drives the plurality of source lines based on the load of the display panel obtained by the load measuring device.

The present invention also provides
A display including a plurality of source lines, a plurality of gate lines, a plurality of switch elements in which each switch element is specified by each source line and each gate line, and a plurality of pixels in which each pixel is connected to each switch element A driving circuit for driving a panel,
The load measuring device according to any one of the above, for obtaining a load on the display panel;
A source line driving unit that drives the plurality of source lines based on a gradation voltage corresponding to gradation data,
The source line driver is
The present invention relates to a drive circuit that drives the plurality of source lines based on the load of the display panel obtained by the load measuring device.

  According to any one of the above-described inventions, it is possible to provide a drive circuit capable of realizing optimum drive according to the load of the display panel to be driven. As a result, it is possible to contribute to the provision of a drive circuit that reduces power consumption by optimizing the charge recycle time and the precharge period, and prevents image quality deterioration by securing a sufficient pixel writing time.

In the driving circuit according to the present invention,
The source line driver is
After short-circuiting the counter electrode and at least one of the plurality of source lines only during a charge recycling period corresponding to the load, the plurality of source lines are connected based on a gradation voltage corresponding to gradation data of each source line. Can be driven.

In the driving circuit according to the present invention,
The source line driver is
After at least one of the plurality of source lines is short-circuited with one end of a capacitor only during a charge recycling period corresponding to the load, the gray scale data of each source line is handled in a state of being electrically disconnected from the capacitor. The plurality of source lines can be driven based on the gradation voltage.

In the driving circuit according to the present invention,
The source line driver is
After the plurality of source lines are precharged for a precharge period corresponding to the load, the plurality of source lines can be driven based on the gradation voltage corresponding to the gradation data of each source line.

In the driving circuit according to the present invention,
The source line driver is
After short-circuiting the counter electrode and at least one of the plurality of source lines only during a charge recycling period corresponding to the load, precharging the plurality of source lines only during a precharge period corresponding to the load, The plurality of source lines can be driven based on the gradation voltage corresponding to the gradation data of each source line.

In the driving circuit according to the present invention,
The source line driver is
After short-circuiting at least one of the plurality of source lines with one end of a capacitor for a charge recycle period corresponding to the load, precharging the plurality of source lines for a precharge period corresponding to the load, The plurality of source lines can be driven based on the gradation voltage corresponding to the gradation data of each source line while being electrically disconnected from the capacitor.

  According to any one of the above inventions, the charge recycle period and the precharge period can be optimized according to the load of the display panel. Therefore, it is possible to realize low power consumption by reusing charges and high-speed writing of pixels by precharging without providing a useless charge reusing period and precharging period within a limited horizontal scanning period.

The present invention also provides
Multiple source lines,
Multiple gate lines,
A plurality of switch elements, each switch element being specified by each source line and each gate line;
A plurality of pixel electrodes, each pixel electrode being connected to each switch element;
A counter electrode provided to face the plurality of pixel electrodes;
A gate driver that scans the plurality of gate lines;
A source driver for driving the plurality of source lines based on gradation data;
The present invention relates to an electro-optical device including any one of the load measuring devices described above.

The present invention also provides
Multiple source lines,
Multiple gate lines,
A plurality of switch elements, each switch element being specified by each source line and each gate line;
A plurality of pixels, each pixel connected to each switch element;
A gate driver that scans the plurality of gate lines;
A source driver for driving the plurality of source lines based on gradation data;
The present invention relates to an electro-optical device including any one of the load measuring devices described above.

The present invention also provides
Multiple source lines,
Multiple gate lines,
A plurality of switch elements, each switch element being specified by each source line and each gate line;
A plurality of pixel electrodes, each pixel electrode being connected to each switch element;
A gate driver that scans the plurality of gate lines;
The present invention relates to an electro-optical device including any one of the drive circuits described above that drives the plurality of source lines.

  According to any one of the above-described inventions, it is possible to provide an electro-optical device including a drive circuit that can realize optimum driving according to the load of the display panel to be driven.

The present invention also provides
The present invention relates to an electronic device including any one of the load measuring devices described above.

The present invention also provides
The present invention relates to an electronic device including any one of the drive circuits described above.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to any one of the above-described inventions, it is possible to provide an electronic apparatus to which a drive circuit, an electro-optical device, or the like that can realize optimal driving according to the load of the display panel to be driven is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Device FIG. 1 shows an example of a block diagram of a liquid crystal device of this embodiment.

  The liquid crystal device 10 (liquid crystal display device; display device in a broad sense) includes a display panel 12 (LCD (Liquid Crystal Display) panel in a narrow sense), a source driver 20 (a source line driver circuit in a broad sense), and a gate driver 30 (in a broad sense). Includes a display controller 40, a power supply circuit 50, and a source voltage setting circuit (voltage setting circuit in a broad sense) 70. Note that it is not necessary to include all these circuit blocks in the liquid crystal device 10, and some of the circuit blocks may be omitted. Note that FIG. 1 illustrates an active matrix liquid crystal device as an example, but those skilled in the art can apply the embodiments described below to a simple matrix liquid crystal device.

  Here, in the display panel 12 (electro-optical device in a broad sense), a plurality of gate lines (scanning lines), a plurality of source lines (data lines), and each pixel electrode are specified by each gate line and each source line. A plurality of pixel electrodes are included. In this case, an active matrix liquid crystal device can be configured by connecting a thin film transistor TFT (Thin Film Transistor, a switching element in a broad sense) to a source line and connecting a pixel electrode to the TFT.

More specifically, the display panel 12 is formed on an active matrix substrate (for example, a glass substrate). In this active matrix substrate, a plurality of gate lines G _{1 to} G _M (M is a natural number of 2 or more) arranged in the Y direction and extending in the X direction, and a plurality of sources arranged in the X direction and extending in the Y direction, respectively. Lines S _{1 to} S _N (N is a natural number of 2 or more) are arranged. A thin film transistor TFT _KL (switch in a broad sense) is provided at a position corresponding to the intersection of the gate line G _K (1 ≦ K ≦ M, K is a natural number) and the source line S _L (1 ≦ L ≦ N, L is a natural number). Element).

The gate electrode of the thin film transistor TFT _KL is connected with the gate line _{G K,} a source electrode of the _{thin film transistor TFT KL} is connected with the source line _{S L,} the drain electrode of the _{thin film transistor TFT KL} is connected with a pixel electrode _{PE KL.} A liquid crystal capacitor CL _KL (liquid crystal element) is _disposed between the pixel electrode PE _KL and the counter electrode CE (common electrode, common electrode) opposed to the pixel electrode PE _KL with the liquid crystal (electro-optical material in a broad sense) interposed therebetween. In addition, an auxiliary capacitor CS _KL is formed. Then, liquid crystal is formed between the active matrix substrate on which the TFT _KL , the pixel electrode PE _{KL, and the} like are formed and the counter substrate on which the counter electrode CE is formed, and the pixel electrode PE _KL , the counter electrode CE, The transmittance of the pixel is changed in accordance with the applied voltage between.

  The voltage level (high potential side voltage VCOMH, low potential side voltage VCOML) of the counter electrode voltage VCOM applied to the counter electrode CE is generated by a counter electrode voltage generation circuit (counter electrode driver) included in the power supply circuit 50. Further, the counter electrode CE may be formed in a strip shape so as to correspond to each gate line without being formed on the entire surface of the counter substrate.

The source driver 20 drives the source lines S _{1 to} S _N of the display panel 12 based on the gradation data. The gate driver 30 scans the gate lines _G 1 ~G _M of the display panel 12 (sequential drive).

  The display controller 40 controls the source driver 20, the gate driver 30, and the power supply circuit 50 in accordance with the contents set by a host such as a central processing unit (CPU) (not shown). More specifically, the display controller 40 sets, for example, an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 20 and the gate driver 30, and supplies to the power supply circuit 50. Thus, the polarity inversion timing of the voltage level of the common electrode voltage VCOM applied to the common electrode CE is controlled.

  The power supply circuit 50 generates various voltage levels (gradation voltages) necessary for driving the display panel 12 and the voltage level of the counter electrode voltage VCOM of the counter electrode CE based on a reference voltage supplied from the outside.

Source voltage setting circuit 70, prior to the source driver 20 drives the source lines S ₁ to S _N, performing at least one of the recycling and precharging the source lines S ₁ to S _N of the charge. Thereby, the power consumption accompanying charging / discharging of the source line can be reduced while realizing high-speed writing of the pixel electrode.

  In the liquid crystal device 10 having such a configuration, the source driver 20, the gate driver 30, the power supply circuit 50, and the source voltage setting circuit 70 cooperate based on gradation data supplied from the outside under the control of the display controller 40. Then, the display panel 12 is driven.

  In FIG. 1, a source driver 20, a gate driver 30, a power supply circuit 50, and a source voltage setting circuit 70 are integrated to form a display driver (driving circuit in a broad sense) 60 as a semiconductor device (integrated circuit, IC). Can do. The display driver 60 in FIG. 1 may have a configuration in which the gate driver 30 is omitted. In FIG. 1, the display driver 60 in the present embodiment may be configured to include the source driver 20, the counter electrode voltage generation circuit of the power supply circuit 50, and the source voltage setting circuit 70.

  By the way, in this embodiment, the power supply circuit 50 implement | achieves the function as a load measuring apparatus of the display panel 12. FIG. That is, the power supply circuit 50 pays attention to the fact that the load of the counter electrode CE is correlated with the load of the display panel 12, and calculates the load of the display panel 12 by obtaining the load of the counter electrode CE. Then, by providing a charge recycle period or a precharge period according to the load of the display panel 12, a pixel writing period is ensured as long as possible within one limited horizontal scanning period.

  Charge reuse and precharge are realized by the following configuration of the display driver 60.

That is, the display driver 60 can further include a plurality of source output switching circuits SSW _{1 to} SSW _{N in} which each source output switching circuit is provided between the source line and an output buffer that drives the source line. The output of each output buffer is connected to the first terminal of each source output switching circuit. Each source line is connected to the second terminal of each source output switching circuit. One end of the shared line COL is connected to the third terminal of each source output switching circuit. The plurality of source output switching circuits SSW _{1 to} SSW _N are simultaneously turned on and off by a common control signal (not shown). Alternatively, the on / off control may be performed individually by a control signal supplied to each source output switching circuit.

  Each source output switching circuit may include a source short circuit switch (source short circuit switch circuit, source short circuit) by performing output enable control for setting the output of each output buffer to a high impedance state. . Each source short-circuit switch circuit is inserted between the output of each output buffer and the common line COL.

  The display driver 60 can include a first capacitor element connection terminal TL1 and a counter electrode charge storage switch (a counter electrode charge storage switch circuit, a counter electrode charge storage short circuit) VSW. The common electrode charge storage switch VSW includes an output of the common electrode voltage generation circuit of the power supply circuit 50 (a common electrode voltage output node to which the common electrode voltage VCOM is supplied) and a first capacitor element connection terminal TL1 (a common electrode charge). Storage node C1ND). One end of the first capacitor element CCV (counter electrode capacitor) is electrically connected to the first capacitor element connection terminal TL1. A predetermined power supply voltage (for example, the system ground power supply voltage VSS) is supplied to the other end of the first capacitor element CCV. In FIG. 1, the first capacitor element CCV is provided outside the display driver 60, but the first capacitor element CCV may be built in the display driver 60.

  Further, the display driver 60 can include a second capacitor element connection terminal TL2 for source charge storage and a source charge storage switch (source charge storage switch circuit, source charge storage short circuit) CSW. . The source charge storage switch CSW is provided between one end of the shared line COL and the second capacitor element connection terminal TL2. Here, the output of the source voltage setting circuit 70 is connected to the common line COL via the source charge storage switch CSW.

  It can be said that the shared line COL includes a second capacitor element connection node. One end of a second capacitor element CCS (source capacitor) is electrically connected to the second capacitor element connection terminal TL2. A predetermined power supply voltage (for example, the system ground power supply voltage VSS) is supplied to the other end of the second capacitor element CCS. In FIG. 1, the second capacitor element CCS is provided outside the display driver 60, but the second capacitor element CCS may be built in the display driver 60.

  When the counter electrode charge storage switch (counter electrode charge storage switch circuit, counter electrode charge storage short circuit) VSW is set to the conductive state, the output of the counter electrode voltage generation circuit of the power supply circuit 50 is set to the high impedance state. Is done.

  Furthermore, the display driver 60 can include a node short circuit switch (node short circuit circuit, node short circuit) HSW. The node short-circuit switch HSW is provided between the common line COL and the common electrode voltage output node.

Prior to driving the source lines S _{1 to} S _N , the display driver 60 performs at least one of reusing and precharging the charges from the counter electrode CE or the source lines S _{1 to} S _N.

For example, the source driver 20 serving as the source line drive unit includes the common electrode CE and the plurality of source lines S ₁ to S through the node short-circuit switch HSW only during the charge recycle period corresponding to the load of the display panel 12 obtained by the power supply circuit 50. After short-circuiting at least one of S _N , the source output switching circuits SSW _{1 to} SSW _N are switched to the source output side, and a plurality of source lines S ₁ to S based on the gradation voltage corresponding to the gradation data of each source line S _N can be driven.

Further, for example, the source driver 20 as the source line driving unit includes a plurality of source lines S _{1 to} S by the source charge storage switch CSW only during the charge recycle period corresponding to the load of the display panel 12 obtained by the power supply circuit 50. _After at least one of _N is short-circuited to one end of the second capacitive element CCS (capacitor), the source output switching circuits SSW _{1 to} SSW _N are sourced while being electrically disconnected from the second capacitive element capacitor. The plurality of source lines S _{1 to} S _N can be driven based on the gradation voltage corresponding to the gradation data of each source line by switching to the output side.

Further, for example, the source driver 20 as the source line driving unit switches the source output switching circuits SSW _{1 to} SSW _N to the shared line side only during the precharge period corresponding to the load of the display panel 12 obtained by the power supply circuit 50. After precharging by applying a precharge voltage to the plurality of source lines S _{1 to} S _N , the source output switching circuits SSW _{1 to} SSW _N are switched to the source output side to correspond to the gradation data of each source line. A plurality of source lines S _{1 to} S _N can be driven based on the regulated voltage.

Furthermore, for example, the source driver 20 serving as the source line driving unit has the node short-circuit switch HSW and the counter electrode CE and the plurality of source lines S only during the charge recycling period corresponding to the load of the display panel 12 obtained by the power supply circuit 50. After short-circuiting at least one of _{1 to} S _N , the source output switching circuits SSW _{1 to} SSW _N are switched to the shared line side during the precharge period corresponding to the load, and the plurality of source lines S _{1 to} S _N are switched to each other. A precharge voltage is applied to perform precharge, and then the source output switching circuits SSW _{1 to} SSW _N are switched to the source output side, and a plurality of source lines S are based on the gradation voltages corresponding to the gradation data of each source line. _{1 to SN} can be driven.

FIG. 2 is an explanatory diagram of an example of drive control of the source line within one horizontal scanning period in the present embodiment. FIG. 2 shows an example of a voltage change of the source line S _L.

(More specifically, the source driver 20) display driver 60 drives the source lines _S 1 to S _N within one horizontal scanning period. At this time, charge is first reused prior to the driving period in which the gradation voltage corresponding to the gradation data is supplied to the source lines S _{1 to} S _N. Reusing charge, without performing charge and discharge of electric charge from an external power source, it changes the potential of the source line S _L.

In the precharge period provided after the charge reuse period, the display driver 60 precharges the source lines S _{1 to} S _N. That is, the display driver 60 supplies a given precharge voltage to the source lines S _{1 to} S _N. Thus, the period for changing the potential of the source line after the driving period is shortened, and the potentials of the source lines S _{1 to} S _N are changed at high speed. In addition, by reusing the charge, the charge / discharge amount of the charge necessary for precharging can be reduced.

In this way, the gradation voltage corresponding to each source line is supplied to the source lines S _{1 to} S _N in the driving period after the precharge period. In the precharge period, since the potential of the source line is changed to the vicinity of a given precharge voltage, the voltage to be changed in the driving period can be lowered, and the grayscale voltage can be supplied to the source lines S _{1 to} S _N at high speed. .

  In FIG. 2, at least one of the charge recycle period and the precharge period may be omitted.

In the present embodiment, when this charge recycling is performed, the display driver 60 uses the counter electrode charge storage switch VSW, the source charge storage switch CSW, and the node short-circuit switch HSW according to the operation mode. The charge from the CE or the source lines S _{1 to} S _N is reused.

Among the above operation modes, in the operation mode in which the charge reuse is performed by the on / off control of the node short-circuit switch HSW, the display driver 60 performs the control while keeping the common electrode charge storage switch VSW in the non-conductive state. In the above operation modes, in the operation mode in which charge reuse is performed by the on / off control of the common electrode charge storage switch VSW and the source charge storage switch CSW, the display driver 60 turns off the node short-circuit switch HSW. Control is performed as it is. When precharging is performed, the source output switching circuits SSW _{1 to} SSW _N are connected to the shared line side (source short-circuit switch is conductive), the source charge storage switch CSW is conductive, and the node short-circuit switch HSW is non-conductive. Take control.

  Detailed control examples of these switches will be described later.

  At this time, the display driver 60 performs the above-described charge reuse control with the period determined according to the load of the display panel 12 obtained by the power supply circuit 50 as the charge reuse period. Further, the display driver 60 performs the above-described precharge control with a period determined according to the load of the display panel 12 obtained by the power supply circuit 50 as a precharge period. Therefore, the power supply circuit 50 supplies the common electrode voltage VCOM to the common electrode CE electrically connected to the common electrode connection point CEP via the common electrode connection point CEP provided on the display panel 12. The power supply circuit 50 receives the measurement signal FBC via the common electrode load measurement connection point CZP provided on the display panel 12 and electrically connected to the common electrode CE, and displays the measurement signal FBC. The load on the panel 12 is obtained.

  Here, the counter electrode load measurement connection point CZP is provided on the display panel 12 separately from the counter electrode connection point CEP. More specifically, it is desirable that the connection point CZP for measuring the counter electrode load is provided on the display panel 12 so that the load on the counter electrode CE is maximized with reference to the counter electrode connection point CEP. By using the measurement signal FBC from the counter electrode load measurement connection point CZP, the delay time of the measurement signal FBC is increased, and the load of the counter electrode CE (the load of the display panel 12) is reliably obtained. Will be able to.

  In FIG. 1, the liquid crystal device 10 includes the display controller 40, but the display controller 40 may be provided outside the liquid crystal device 10. Alternatively, the host may be included in the liquid crystal device 10 together with the display controller 40. Further, some or all of the source driver 20, gate driver 30, display controller 40, power supply circuit 50, and source voltage setting circuit 70 may be formed on the display panel 12.

  FIG. 3 is a block diagram showing another configuration example of the liquid crystal device according to this embodiment.

  In FIG. 3, a display driver 60 including a source driver 20, a gate driver 30, and a power supply circuit 50 is formed on the display panel 12 (panel substrate). As described above, the display panel 12 includes a plurality of switching elements specified by the plurality of gate lines, the plurality of source lines, the gate lines of the plurality of gate lines and the source lines of the plurality of source lines, and the pixels. A plurality of pixel electrodes whose electrodes are connected to each switch element, a source driver that drives a plurality of source lines, and a gate driver that scans a plurality of gate lines can be included. A plurality of pixels are formed in the pixel formation region 44 of the display panel 12. Each pixel can include a TFT (switch element) having a source line connected to the source and a gate line connected to the gate, and a pixel electrode connected to the drain of the TFT.

  In FIG. 3, the gate driver 30 may be omitted from the display panel 12.

2. Measurement of Panel Load FIG. 4 shows a configuration main part for measuring the load of the display panel 12 in the present embodiment. 4, the same parts as those in FIG. 1 or FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 4, the power supply circuit 50 includes a counter electrode driving unit 100 and a panel load measuring unit 110.

  The counter electrode driving unit 100 drives the counter electrode CE of the display panel 12. That is, the counter electrode driver 100 supplies the counter electrode voltage VCOM that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML to the counter electrode CE by polarity inversion driving. At this time, the counter electrode driver 100 supplies the counter electrode voltage VCOM to the counter electrode CE via the counter electrode connection point CEP of the display panel 12.

  The panel load measuring unit 110 receives the measurement signal FBC from the display panel 12 and obtains the load on the display panel 12 based on the delay time of the measurement signal FBC.

  FIG. 5 is an explanatory diagram of the delay time of the measurement signal FBC in FIG.

  The potential of the common electrode voltage VCOM is switched to the high potential side voltage VCOMH or the low potential side voltage VCOML at a timing defined by the polarity inversion signal POL. The panel load measurement unit 110 uses the change timing of the polarity inversion signal POL as the change timing of the common electrode voltage VCOM, and the voltage of the measurement signal FBC is a given threshold voltage VTHc (for example, based on the change timing of the common electrode voltage VCOM) The time required to reach the voltage half the amplitude of the measurement signal FBC) is determined as a delay time Δt1.

  The panel load measuring unit 110 stores in advance a control signal tEQ that defines a charge recycle period and a control signal tPR that defines a precharge period corresponding to the delay time, and the delay obtained as shown in FIG. Control signals tEQ and tPR corresponding to the time Δt1 are output. The source driver 20 performs charge recycle control and precharge control only during a period corresponding to the control signals tEQ and tPR.

  In FIG. 5, the rising timing of the common electrode voltage VCOM has been described as an example, but the same applies to the falling timing of the common electrode voltage VCOM.

  FIG. 6 shows a block diagram of a configuration example of the panel load measurement unit 110 of FIG.

  The panel load measuring unit 110 can include a comparator 112, a counter 114, and a period table 116. The comparator 112 compares the voltage of the measurement signal FBC with the threshold voltage VTHc, and outputs a pulse when the voltage of the measurement signal FBC reaches the threshold voltage VTHc, for example. The counter 114 counts up the count value in synchronization with the reference clock. The counter 114 initializes the count value at the rising edge and falling edge of the polarity inversion signal POL. Further, the counter 114 latches the count value with the pulse from the comparator 112 and outputs it to the period table 116 as the count value CNT.

  FIG. 7 shows an outline of the configuration of the period table 116 of FIG.

  In the period table 116, the length of the charge recycle period and the length of the precharge period are stored in advance for each count value CNT from the counter 114, and charge recycle is performed according to the count value CNT from the counter 114. A control signal tEQ that defines a use period and a control signal tPR that defines a precharge period are output. Thus, the period table 116 regards the delay time corresponding to the load of the counter electrode CE as the count value of the counter 114, and contributes to the drive control of the source line in the charge recycle period and the precharge period corresponding to the count value. It can be done.

  In FIG. 7, the period table 116 stores the precharge voltage PV supplied to the source line during the precharge period in advance for each count value CNT from the counter 114, and the count value CNT from the counter 114. Accordingly, a control signal designating a precharge voltage can be output. Therefore, the period table 116 can consider the delay time corresponding to the load of the counter electrode CE as the count value of the counter 114, and can change the precharge voltage corresponding to the count value.

  In FIG. 7, the charge reuse period and the precharge period are designated. However, any one of the charge reuse period and the precharge period may be used. Even if the precharge period is specified, the precharge voltage may be fixedly applied.

  As described above, the panel load measuring unit 110 displays the load corresponding to the time required for the measurement signal FBC to reach the predetermined threshold voltage VTHc (threshold) with reference to the change timing of the common electrode voltage VCOM. It can be obtained as a load on the panel 12. Therefore, the counter electrode load measuring connection point CZP is provided so that the load on the counter electrode CE is maximized when viewed from the counter electrode connection point CEP, so that the delay time Δt1 can be easily and reliably obtained. As a result, the load on the display panel 12 can be obtained with higher accuracy.

3. Specific Configuration Example Next, a specific configuration example of the display driver 60 in the present embodiment will be described.

3.1 Source Driver FIGS. 8 and 9 show block diagrams of configuration examples of the source driver 20 of FIG. 1 or FIG.

  The source driver 20 includes a shift register 22, line latches 24 and 26, a reference voltage generation circuit 27, a DAC 28 (Digital-to-Analog Converter) (data voltage generation circuit in a broad sense), an output buffer 29, and a charge reuse control unit 150. The precharge control unit 160 is included.

  The shift register 22 includes a plurality of flip-flops provided corresponding to each source line and sequentially connected. When the shift register 22 holds the enable input / output signal EIO in synchronization with the clock signal CLK, the shift register 22 sequentially shifts the enable input / output signal EIO to the adjacent flip-flops in synchronization with the clock signal CLK.

  Gradation data (DIO) is input to the line latch 24 from the display controller 40 in units of 18 bits (6 bits (gradation data) × 3 (each RGB color)), for example. The line latch 24 latches the gradation data (DIO) in synchronization with the enable input / output signal EIO sequentially shifted by each flip-flop of the shift register 22.

  The line latch 26 latches the grayscale data for one horizontal scan latched by the line latch 24 in synchronization with the horizontal synchronization signal LP supplied from the display controller 40.

  The reference voltage generation circuit 27 generates 64 types of reference voltages. The 64 types of reference voltages generated by the reference voltage generation circuit 27 are supplied to the DAC 28.

  A DAC (data voltage generation circuit) 28 generates an analog data voltage to be supplied to each source line. Specifically, the DAC 28 selects one of the reference voltages from the reference voltage generation circuit 27 based on the digital gradation data from the line latch 26, and outputs an analog data voltage corresponding to the digital gradation data. Output.

The output buffer 29 buffers the data voltage from the DAC 28 and outputs it to the source line to drive the source line. Specifically, the output buffer 29 includes operational amplifier circuit blocks OPC _{1 to} OPC _N each including a voltage follower-connected operational amplifier circuit provided for each source line, and these operational amplifier circuit blocks are connected to the DAC 28. Is converted to impedance and output to each source line. The output buffer 29 has the source output switching circuit (or source short circuit switch) of FIG. 1 or FIG. 3, and each source output switching circuit is provided at the output of each operational amplifier circuit block.

  The charge recycle control unit 150 generates a control signal for performing the above charge recycle control for a period defined by the control signal tEQ, and outputs the control signal to the output buffer 29. The precharge control unit 160 generates a control signal for performing the above-described precharge control only for a period specified by the control signal tPR, and outputs the control signal to the output buffer 29.

  In FIG. 8, the digital gradation data is converted from digital to analog and output to the source line via the output buffer 29. However, the analog video signal is sampled and held and output. A configuration of outputting to the source line via the buffer 29 can also be adopted.

The reference voltage generation circuit 27 divides the voltages VDDH and VSSH generated by the power supply circuit 50 by resistance and generates 64 types of reference voltages. Each reference voltage corresponds to each gradation value represented by 6-bit gradation data. Each reference voltage is commonly supplied to the source lines S _{1 to} S _N.

The DAC 28 includes a decoder provided for each source line, and each decoder outputs a reference voltage corresponding to the gradation data to the operational amplifier circuit blocks OPC _{1 to} OPC _N.

  8 and 9 show the configuration example in the case where the gradation data is supplied line by line, the display driver 60 may incorporate a display memory for storing gradation data for at least one screen. .

3.2 Gate Driver FIG. 10 shows a configuration example of the gate driver 30 shown in FIG.

  The gate driver 30 includes an address generation circuit 32, an address decoder 34, a level shifter 36, and an output circuit 38.

Address generating circuit 32 generates an address corresponding to the gate line to be selected among the gate lines G ₁ ~G _M. Address generating circuit 32 can generate an address to scan and select the gate line G ₁ ~G _M one by one. When one vertical scanning period is started in synchronization with the vertical synchronization signal from the display controller 40, the address generation circuit 32 generates an address so that one line is selected in synchronization with the horizontal synchronization signal.

The address decoder 34 decodes the address generated by the address generation circuit 32 selects the decoded signal lines corresponding to the gate lines G ₁ ~G _M based on the decoding result.

  The level shifter 36 shifts the voltage level of the signal on the decode signal line from the address decoder 34 to a voltage level corresponding to the liquid crystal element of the display panel 12 and the transistor capability of the TFT. Since this voltage level requires a high voltage level, a high breakdown voltage process different from other logic circuit units is used.

  The output circuit 38 buffers the scanning voltage shifted by the level shifter 36 and outputs it to the gate line to drive the gate line.

3.3 Power Supply Circuit FIG. 11 shows a configuration example of the power supply circuit 50 shown in FIG.

  The power supply circuit 50 includes a positive direction double booster circuit 52, a scanning voltage generation circuit 54, a counter electrode voltage generation circuit (a counter electrode drive unit in a broad sense) 56, and a panel load measurement unit 58. The counter electrode voltage generation circuit 56 realizes the function of the counter electrode driver 100 of FIG. The panel load measuring unit 58 realizes the function of the panel load measuring unit 110 of FIG. The power supply circuit 50 is supplied with the system ground power supply voltage VSS and the system power supply voltage VDD.

  The system ground power supply voltage VSS and the system power supply voltage VDD are supplied to the positive direction double booster circuit 52. Then, the positive direction double boosting circuit 52 generates a power supply voltage VDDHS obtained by boosting the system power supply voltage VDD twice in the positive direction on the basis of the system ground power supply voltage VSS. That is, the positive direction double boosting circuit 52 boosts the voltage difference between the system ground power supply voltage VSS and the system power supply voltage VDD twice. Such a positive direction double boosting circuit 52 can be constituted by a known charge pump circuit. The power supply voltage VDDHS is supplied to the source driver 20, the scanning voltage generation circuit 54, and the counter electrode voltage generation circuit 56. It is desirable that the positive direction double booster circuit 52 outputs a power supply voltage VDDHS obtained by boosting the system power supply voltage VDD twice in the positive direction by adjusting the voltage level with a regulator after boosting at a boosting factor of 2 or more. .

  The scan voltage generation circuit 54 is supplied with the system ground power supply voltage VSS and the power supply voltage VDDHS. The scan voltage generation circuit 54 generates a scan voltage. The scanning voltage is a voltage applied to the gate line selected by the gate driver 30. The high potential side voltage of this scanning voltage is VDDHG, and the low potential side voltage is VEE.

  The counter electrode voltage generation circuit 56 generates a counter electrode voltage VCOM. The common electrode voltage generation circuit 56 outputs the high potential side voltage VCOMH or the low potential side voltage VCOML as the common electrode voltage VCOM based on the polarity inversion signal POL. The polarity inversion signal POL is generated by the display controller 40 in accordance with the polarity inversion timing.

  The panel load measuring unit 58 obtains the load of the display panel 12 based on the measurement signal FBC as shown in FIG. 6, and outputs control signals tEQ and tPR according to the load.

  FIG. 12 shows an example of the drive waveform of the display panel 12 of FIG. 1 or FIG.

  A gradation voltage DLV corresponding to the gradation value of the gradation data is applied to the source line. In FIG. 12, a gradation voltage DLV having an amplitude of 5 V is applied with respect to the system ground power supply voltage VSS (= 0 V).

  A scanning voltage GLV of a low potential side voltage VEE (= −10 V) when not selected and a high potential side voltage VDDHG (= 15 V) when selected is applied to the gate line.

  The counter electrode CE is applied with the counter electrode voltage VCOM of the high potential side voltage VCOMH (= 3 V) and the low potential side voltage VCOML (= −2 V). The polarity of the voltage level of the counter electrode voltage VCOM with respect to a given voltage is inverted in accordance with the polarity inversion timing. FIG. 12 shows the waveform of the counter electrode voltage VCOM during so-called scanning line inversion driving. In accordance with the polarity inversion timing, the polarity of the grayscale voltage DLV of the source line is also inverted with reference to a given voltage.

  By the way, the liquid crystal element has a property that it deteriorates when a DC voltage is applied for a long time. For this reason, a driving method is required in which the polarity of the voltage applied to the liquid crystal element is inverted every predetermined period. Such driving methods include frame inversion driving, scanning (gate) line inversion driving, data (source) line inversion driving, dot inversion driving, and the like.

  Among these, the frame inversion drive has a disadvantage that the image quality is not so good although the power consumption is low. Data line inversion driving and dot inversion driving have good image quality, but have the disadvantage that a high voltage is required to drive the display panel.

  In the scanning line inversion drive, the polarity of the voltage applied to the liquid crystal element is inverted every scanning period (each gate line). For example, a positive voltage is applied to the liquid crystal element in the first scanning period (gate line), a negative voltage is applied in the second scanning period, and a positive voltage is applied in the third scanning period. The On the other hand, in the next frame, a negative voltage is applied to the liquid crystal element in the first scanning period, a positive voltage is applied in the second scanning period, and a negative voltage is applied in the third scanning period. Voltage is applied.

  In this scan line inversion drive, the voltage level of the counter electrode voltage VCOM of the counter electrode CE is inverted every scan period.

  More specifically, as shown in FIG. 13, the voltage level of the common electrode voltage VCOM becomes the low potential side voltage VCOML in the positive period T1 (first period), and in the negative period T2 (second period). The high potential side voltage VCOMH is obtained. The polarity of the gradation voltage applied to the source line in accordance with this timing is also reversed. The low potential side voltage VCOML is a voltage level obtained by inverting the polarity of the high potential side voltage VCOMH with reference to a given voltage level.

  Here, the positive period T1 is a period in which the voltage level of the pixel electrode to which the grayscale voltage of the source line is supplied is higher than the voltage level of the counter electrode CE. In this period T1, a positive voltage is applied to the liquid crystal element. On the other hand, the negative period T2 is a period in which the voltage level of the pixel electrode to which the grayscale voltage of the source line is supplied is lower than the voltage level of the counter electrode CE. In this period T2, a negative voltage is applied to the liquid crystal element.

  Thus, by reversing the polarity of the counter electrode voltage VCOM, the voltage necessary for driving the display panel can be lowered. As a result, the withstand voltage of the drive circuit can be lowered, and the manufacturing process of the drive circuit can be simplified and the cost can be reduced.

4). Charge Reuse and Precharge in the Present Embodiment Next, charge recycle control and precharge control in the present embodiment in the configuration of FIG. 1 or FIG. 3 will be described.

  FIG. 14 shows the main components of the display driver 60 of this embodiment.

In FIG. 14, the same parts as those in FIG. 1 or FIG. In FIG. 14, the source output switch circuit of the source output switch circuit _{SSW 1 ~SSW N SSW j (1} ≦ j ≦ N, j is an _{integer), SSW k (1 ≦ k} ≦ N, k ≠ j, k is Only an integer) is shown, but the other source output switching circuits have the same configuration. In FIG. 14, each source output switching circuit includes a source short-circuit switch.

The source short circuit switch of the source output switching circuit SSW _j as the first source short circuit includes a source line S _j (output of an operational amplifier for source output that drives the source line S _j ) and a source short circuit node SVND (shared line COL). Between. The source short circuit switch of the source output switching circuit SSW _k as the second source short circuit includes a source line S _k (output of an operational amplifier for source output that drives the source line S _k ) and a source short circuit node SVND (shared line COL). Between.

  The source charge storage switch CSW is provided between the source charge storage node C2ND to which one end of the second capacitor element (source capacitor) CCS is connected and the source short-circuit node SVND (shared line COL).

  The node short-circuit switch HSW includes a common electrode voltage output node VND to which a voltage output to a common electrode CE provided across a pixel electrode of the display panel 12 (electro-optical device) and an electro-optical element (liquid crystal element) is applied, and a source. It is provided between the short-circuit node SVND.

  The source voltage setting circuit 70 includes, for example, a voltage follower-connected operational amplifier OPS, and a voltage setting switch (voltage setting switch circuit) PSW between the output of the operational amplifier OPS and the second capacitor element connection terminal TL2. be able to. When performing output enable control for setting the output of the operational amplifier OPS to a high impedance state, a configuration in which the voltage setting switch PSW is unnecessary can be employed. Since the output voltage of the operational amplifier OPS is supplied to one end of the first capacitive element CCS, an effect of preventing oscillation of the operational amplifier OPS can be obtained.

A voltage (precharge voltage) that can be arbitrarily set between the highest voltage and the lowest voltage of the source voltage supplied to the source lines S _{1 to} S _N is supplied to the input of the operational amplifier OPS. As such a voltage, an off-voltage of the display panel 12 as an electro-optical device can be adopted, but it is desirable that the voltage be changed according to the load of the display panel 12 as shown in FIG. Note that the off-voltage is a voltage at which the voltage between the pixel electrode and the counter electrode through the liquid crystal element is lower than a given threshold value and the transmittance of the pixel is almost zero.

  The operational amplifier OPS can impedance-convert the voltage and supply the output voltage to the source charge storage node C2ND. The system power supply voltage VDD is supplied as the high potential side power supply voltage of the operational amplifier OPS, and the system ground power supply voltage VSS is supplied as the low potential side power supply voltage of the operational amplifier OPS.

On the other hand, the operational amplifier circuit block OPC _j for driving the source line S _j based on the grayscale voltage corresponding to the source line S _j includes a source output operational amplifier (first source output operational amplifier). The high potential side power supply voltage VDDHS is supplied as the high potential side power supply voltage of the source output operational amplifier, and the system ground power supply voltage VSS is supplied as the low potential side power supply voltage of the source output operational amplifier. The operational amplifier circuit block OPC _k for driving the source line S _k based on the grayscale voltage corresponding to the source line S _k includes a source output operational amplifier (second source output operational amplifier). The high potential side power supply voltage VDDHS is supplied as the high potential side power supply voltage of the source output operational amplifier, and the system ground power supply voltage VSS is supplied as the low potential side power supply voltage of the source output operational amplifier.

  Here, the high-potential-side power supply voltage VDDHS is a voltage obtained by boosting the high-potential-side power supply voltage VDD of the operational amplifier OPS of the source voltage setting circuit 70.

  FIG. 15 shows the relationship between the power supply voltages VDD and VDDHS.

  The positive direction double boosting circuit 52 of the power supply circuit 50 generates a power supply voltage VDDHS obtained by boosting the voltage between the system power supply voltage VDD and the system ground power supply voltage VSS in the positive direction twice with respect to the system ground power supply voltage VSS. Generate.

Here, the power consumption P1 when the operational amplifier OPS charges or discharges a predetermined charge Q from its output, and the operational amplifier of the operational amplifier circuit block OPC _j (OPC _k ) charges or discharges the charge amount Q from its output. Consider the power consumption P2 in the case of. When the operational amplifier of the operational amplifier circuit block OPC _j (OPC _k ) to which the power supply voltage VDDHS is supplied as the high potential power supply voltage drives the predetermined current I, the operational amplifier to which the power supply voltage VDD is supplied as the high potential power supply voltage Compared with the case where the OPS drives a predetermined current I to its output, the current consumption is halved. This is because the power supply voltage VDD is one half of the power supply voltage VDDHS. That is, P1 is half of P2. In particular, since the charge charged / discharged from the power supply line to which the power supply voltage VDDHS is supplied is charged / discharged from the power supply line to which the power supply voltage VDD is supplied, the power consumption can be reduced by the above.

  By the way, in this embodiment, the display driver 60 or the display panel 12 includes an operation mode setting register (not shown), and performs charge reuse control and precharge control in an operation mode corresponding to control data of the operation mode setting register. Alternatively, the display driver 60 or the display panel 12 includes an operation mode setting terminal (external setting terminal) (not shown), and controls and pre-uses charge recycle in an operation mode corresponding to a signal state externally applied to the operation mode setting terminal. Charge control is performed.

  FIG. 16 is an explanatory diagram of a control example of the display driver 60 of the present embodiment.

  In the present embodiment, switch control of various switches shown in FIG. 14 is performed, so that charge is reused when driving the counter electrode, and charge is reused or precharged when driving the source line. Can be. The charge reuse period during which charge reuse is controlled is determined according to the load on the display panel 12 obtained by the power supply circuit 50. Further, the precharge period in which the precharge control is performed is determined according to the load of the display panel 12 obtained by the power supply circuit 50. The charge reuse control unit 150 and the precharge control unit 160 of the source driver 20 generate a switch control signal that turns on or off each switch in FIG. 14 in each period defined by the control signals tEQ and tPR. .

  The display driver 60 according to the present embodiment performs control specified by one of the following first to fourth control methods based on the control data set by the operation mode setting register.

  In the first control method, the display driver 60 recycles charges in the first operation mode prior to driving the counter electrode. In addition, the display driver 60 performs charge re-use in the first operation mode prior to driving the source line, and then pre-charges the source line, and then the gradation corresponding to the gradation data. A source line is driven using a voltage.

  In the second control method, the display driver 60 recycles charges in the second operation mode prior to driving the counter electrode. In addition, the display driver 60 precharges the source line after reusing charges in the second operation mode prior to driving the source line, and then performs gradation corresponding to the gradation data. A source line is driven using a voltage.

  In the third control method, the display driver 60 reuses charges in the second operation mode prior to driving the counter electrode. Prior to driving the source line, the display driver 60 precharges the source line without reusing the charge, and then uses the gradation voltage corresponding to the gradation data to change the source line. To drive.

  In the fourth control method, the display driver 60 does not reuse charges prior to driving the counter electrode. On the other hand, prior to driving the source line, the display driver 60 precharges the source line without reusing the charge, and then uses the gradation voltage corresponding to the gradation data. Drive.

4.1 First Control Method FIG. 17 shows an example of the control timing of the first control method shown in FIG.

In FIG. 17, each source output switching circuit of the source output switching circuits SSW _{1 to} SSW _N includes a source short circuit switch, and the control state of the source short circuit switch included in each source output switching circuit is set as the control state of each source output switching circuit. Show. In FIG. 17, “ON” of each switch indicates that the switch is in a conductive state, and “OFF” of each switch indicates that the switch is in a non-conductive state.

  In the first control method, a charge recycle period and a precharge period are provided prior to a drive period in which the source output operational amplifier drives the source line based on the grayscale voltage corresponding to the grayscale data.

In the charge recycle period, the source output switching circuits SSW _{1 to} SSW _N are turned on (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned on), the source charge storage switch CSW is turned off, the counter electrode charge storage switch VSW is turned off, the node short-circuit switch HSW is turned on, and the voltage setting switch PSW is turned off. That is, in FIG. 14, the source short circuit switch circuit of the source output switching circuits SSW _j and SSW _k , the node short circuit switch HSW is on, the source charge storage switch CSW is off, the counter electrode charge storage switch VSW is off, and the voltage setting switch PSW Is set to off.

As a result, in the charge recycle period, the source lines S _{1 to SN} and the shared line COL are short-circuited, and the common electrode voltage output node VND and the source short-circuit node SVND are short-circuited. Therefore, the charges are reused by moving the charges so that the source lines S _{1 to} S _N and the counter electrode have the same potential.

Next, in the precharge period, the source output switching circuits SSW _{1 to} SSW _N are turned on (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned on), and the source charge is accumulated. Switch CSW is turned on, counter electrode charge storage switch VSW is turned off, node short circuit switch HSW is turned off, and voltage setting switch PSW is turned on. That is, in FIG. 14, the source short circuit switches of the source output switching circuits SSW _j and SSW _k are set to ON, the node short circuit switch HSW is OFF, the source charge storage switch CSW is ON, and the counter electrode charge storage switch VSW is OFF. The Then, the source voltage setting circuit 70 supplies the precharge voltage PV to the source charge storage node C2ND.

As a result, the precharge voltage is applied to the source lines S _{1 to} S _N via the shared line COL.

In the drive period after the precharge period, the source output switching circuits SSW _{1 to} SSW _N are turned off (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned off), and the source charge The storage switch CSW is turned off, the counter electrode charge storage switch VSW is turned off, the node short-circuit switch HSW is turned off, and the voltage setting switch PSW is turned off. Then, the operational amplifier circuit block _OPC 1 _{~OPC N} supplies a gradation voltage corresponding to the grayscale data to the source line _S 1 to S _N.

  FIG. 18 shows a waveform diagram of an operation example of the liquid crystal device 10 controlled by the first control method.

FIG. 18 shows changes in the potentials of the gate lines G _K , G _{K + 1} , the source line S _j, and the counter electrode CE, but the same applies to other gate lines and source lines. 18, a selection period of the pixel that is connected with the gate line G _K within one horizontal scanning period (1H), the scan voltage is applied to the gate line G _K, the selection of pixels is connected with the gate line G _{K + 1} A scanning voltage is applied to the gate line _{GK + 1} within one horizontal scanning period. Each horizontal scanning period includes a charge recycle period, a precharge period, and a drive period.

In the charge recycling period (TT1), in the source output switching circuits SSW _j and SSW _k , the source lines S _j and S _k are electrically connected to the shared line COL including the second capacitor element connection node, respectively. In addition, the node short circuit switch HSW is turned on while the source charge storage switch CSW, the counter electrode charge storage switch VSW, and the voltage setting switch PSW are in a non-conductive state, and the common line COL is output from the counter electrode voltage generation circuit (the counter electrode). The counter electrode voltage output node to which the voltage VCOM is supplied is electrically connected. Therefore, in the charge recycling period, the shared line COL and the source lines S _j and S _k are electrically connected, and the source lines S _j and S _k and the counter electrode CE have the same potential, and follow the law of charge conservation. The charge accumulated in the parasitic capacitances of the source lines S _j and S _k supplements the counter electrode CE, or the charges accumulated in the counter electrode CE supplements the parasitic capacitances of the source lines S _j and S _k. Or That is, in the charge recycle period, the potentials of the source line and the counter electrode CE are changed without replenishing charges from the power supply circuit 50 at all.

Next, in the precharge period (TT2) after the charge reuse period, in the source output switching circuits SSW _j and SSW _k , as in the charge reuse period, the source lines S _j and S _k are connected to the second capacitor element. Each is electrically connected to a common line COL including a connection node. Further, the source charge storage switch CSW and the voltage setting switch PSW are set to a conductive state, and the node short-circuit switch HSW is set to a non-conductive state. Therefore, in the precharge period, for example, the high potential side voltage VCOMH is supplied to the counter electrode CE. On the other hand, the precharge voltage PV is supplied to the common line COL. In the precharge period, the common line COL is the source line _S j, to be connected _{S k} and electrically, the source line _S j, the precharge voltage PV is supplied to _{S k.}

At this time, the source voltage setting circuit 70 charges and discharges the charge on the source line until each source line reaches the potential of the precharge voltage PV with reference to the potential after the change in the charge reuse period TT1. Therefore, in the precharge period after the charge recycling period, the source line voltage to be changed by the source voltage setting circuit 70 is often low. That is, based on the potential of the source line in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection period of pixels connected to the gate line _GK) is used as it is. 18), the source voltage setting circuit 70 needs to charge / discharge the source line charges by ΔVs01 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the source voltage setting circuit 70 may charge and discharge the source line charges by ΔVs02 (ΔVs02 <ΔVs01) as shown in FIG. For example, as shown in FIG. 18, by precharging to the precharge voltage PV, the amount of charge to be charged / discharged from the source line may increase, but the source line is charged / discharged as in the next 1H. In some cases, the amount of charge to be reduced can be significantly reduced.

  Furthermore, even when the charge cannot be sufficiently charged / discharged only by the charge recycle period, by providing the precharge period, it is possible to shorten the writing time of the pixel electrode to be completed within 1H.

Next, in the drive period (TT3) after the precharge period, in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _L and S _{L + 1} are electrically connected to the output of the output buffer of the source driver 20, respectively. The Further, the source charge storage switch CSW, the counter electrode charge storage switch VSW, and the voltage setting switch PSW are set in a non-conducting state. Then, the node short-circuit switch HSW is set to a non-conductive state. Therefore, in the driving period, the source lines S _j and S _k are driven by the output buffer of the source driver 20.

Similarly, in the drive period (TT3) after the precharge period, the counter electrode CE is electrically connected to the output of the counter electrode voltage generation circuit 56 of the power supply circuit 50. Therefore, in the driving period, the common electrode voltage VCOM is supplied to the common electrode CE and the common electrode voltage generation circuit 56. At this time, the common electrode voltage generation circuit 56 charges and discharges the common electrode CE until the high potential side voltage VCOMH is reached with reference to the potential after the change in the charge reuse period TT1. Therefore, in the driving period after the charge recycling period, the voltage of the counter electrode CE that should be changed by the counter electrode voltage generation circuit 56 may be low. That is, based on the potential of the counter electrode CE in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection of pixels connected to the gate line _GK) is used as it is. When it is attempted to set the potential of the counter electrode CE during (period), the counter electrode voltage generation circuit 56 needs to charge / discharge the charge of the counter electrode CE by ΔVc01 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the counter electrode voltage generation circuit 56 only needs to charge / discharge the charge of the counter electrode CE by ΔVc02 (ΔVc02 <ΔVc01) as shown in FIG.

  That is, charges are reused by charging and discharging charges from the first capacitor element CCV by repeatedly turning on and off the counter electrode charge storage switch VSW while the node short-circuit switch HSW is off.

  In the next horizontal scanning period, a charge recycle period, a precharge period, and a drive period are provided, and the same is performed in each period. The operation in the charge recycle period in FIG. 18 is control in the first operation mode.

4.2 Second Control Method FIG. 19 shows an example of the control timing of the second control method shown in FIG.

In FIG. 19, each source output switching circuit of the source output switching circuits SSW _{1 to} SSW _N includes a source short-circuit switch, and the control state of the source short-circuit switch included in each source output switching circuit is set as the control state of each source output switching circuit. Show. In FIG. 19, “ON” of each switch indicates that the switch is in a conductive state, and “OFF” of each switch indicates that the switch is in a non-conductive state.

  In the second control method, a charge recycle period and a precharge period are provided prior to a drive period in which the source output operational amplifier drives the source line based on the grayscale voltage corresponding to the grayscale data.

In the charge recycle period, the source output switching circuits SSW _{1 to} SSW _N are turned on (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned on), the source charge storage switch CSW is turned on, the counter electrode charge storage switch VSW is turned on, the node short-circuit switch HSW is turned off, and the voltage setting switch PSW is turned off. That is, in FIG. 14, the source short circuit switch and the source charge storage switch CSW of the source output switching circuits SSW _j and SSW _k are turned on while the output of the source voltage setting circuit 70 is set to the high impedance state, and the counter electrode charge storage switch VSW is turned on and the node short circuit switch HSW is turned off.

As a result, during the charge recycling period, the source lines S _{1 to SN} and the shared line COL are short-circuited, and the shared line COL is electrically connected to one end of the second capacitor element CCS. Further, the common electrode voltage output node VND is electrically connected to one end of the first capacitor element CCV. Therefore, the charges are reused by moving the charges so that the source lines S _{1 to} S _N and one end of the second capacitor element CCS have the same potential. Further, the charge is reused by moving the charge so that the common electrode voltage output node VND and one end of the first capacitor element CCV have the same potential.

Next, in the precharge period, the same control as in the precharge period of FIG. 17 is performed. That is, the source output switching circuits SSW _{1 to} SSW _N are turned on (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned on), the source charge storage switch CSW is turned on, The common electrode charge storage switch VSW is turned off, the node short circuit switch HSW is turned off, and the voltage setting switch PSW is turned on. That is, in FIG. 14, the source short circuit switch of the source output switching circuits SSW _j and SSW _k is set to OFF, the node short circuit switch HSW is OFF, the source charge storage switch CSW is ON, and the counter electrode charge storage switch VSW is OFF. The Then, the source voltage setting circuit 70 supplies the precharge voltage PV to the source charge storage node C2ND.

As a result, the precharge voltage is applied to the source lines S _{1 to} S _N via the shared line COL.

In the drive period after the precharge period, the source output switching circuits SSW _{1 to} SSW _N are turned off (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned off), and the source charge The storage switch CSW is turned off, the counter electrode charge storage switch VSW is turned off, the node short-circuit switch HSW is turned off, and the voltage setting switch PSW is turned off. Then, the operational amplifier circuit block _OPC 1 _{~OPC N} supplies a gradation voltage corresponding to the grayscale data to the source line _S 1 to S _N.

  FIG. 20 shows a waveform diagram of an operation example of the liquid crystal device 10 controlled by the second control method.

FIG. 20 shows changes in the potentials of the gate lines G _K , G _{K + 1} , the source line S _j, and the counter electrode CE, but the same applies to other gate lines and source lines. In FIG 20, a selection period of the pixel that is connected with the gate line G _K within one horizontal scanning period (1H), the scan voltage is applied to the gate line G _K, the selection of pixels is connected with the gate line G _{K + 1} A scanning voltage is applied to the gate line _{GK + 1} within one horizontal scanning period. Each horizontal scanning period includes a charge recycle period, a precharge period, and a drive period.

In the charge recycle period (TT10), in the source output switching circuits SSW _j and SSW _k , the source lines S _j and S _k are electrically connected to the shared line COL including the second capacitor element connection node, respectively. Further, the source charge storage switch CSW becomes conductive, and the shared line COL is electrically connected to one end of the second capacitor element CCS via the second capacitor element connection terminal TL2. Further, the voltage setting switch PSW is set to a non-conductive state. Therefore, in the charge recycling period, one end of the second capacitor element CCS and the source lines S _j and S _k are at the same potential, and the charge accumulated in the parasitic capacitance of the source line is in accordance with the law of charge conservation. The charge is replenished to one end of the capacitive element CCS, or the charge accumulated in the second capacitive element CCS is supplemented to the parasitic capacitance of the source lines S _j and S _k . That is, in the charge recycle period, the potential of the source line is changed without replenishing charges from the power supply circuit 50 at all.

  Similarly, in the charge recycle period, the output of the counter electrode voltage generation circuit (not shown) is set to a high impedance state, and the counter electrode charge storage switch VSW is set to a conductive state. Is electrically connected to one end of the first capacitor element CCV via the capacitor element connection terminal TL1. Therefore, in the charge recycle period, one end of the first capacitor element CCV and the counter electrode CE have the same potential, and the charge accumulated in the parasitic capacitance of the counter electrode CE replenishes one end of the first capacitor element CCV. Or charge accumulated in the first capacitor element CCV is supplemented to the parasitic capacitance of the counter electrode CE. That is, in the charge recycling period, the potential of the counter electrode CE is changed without replenishing charges from the power supply circuit 50 at all.

Next, in the precharge period (TT20) after the charge reuse period, in the source output switching circuits SSW _j and SSW _k , as in the charge reuse period, the source lines S _j and S _k are connected to the second capacitor element. Each is electrically connected to a common line COL including a connection node. Further, the source charge storage switch CSW and the voltage setting switch PSW are set to a conductive state, and the node short-circuit switch HSW is set to a non-conductive state. Therefore, in the precharge period, for example, the high potential side voltage VCOMH is supplied to the counter electrode CE. On the other hand, the precharge voltage PV is supplied to the common line COL. In the precharge period, the common line COL is the source line _S j, to be connected _{S k} and electrically, the source line _S j, the precharge voltage PV is supplied to _{S k.}

At this time, the source voltage setting circuit 70 charges and discharges the charge on the source line until each source line reaches the potential of the precharge voltage PV with reference to the potential after the change in the charge reuse period TT10. Therefore, in the precharge period after the charge recycling period, the source line voltage to be changed by the source voltage setting circuit 70 is often low. That is, based on the potential of the source line in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection period of pixels connected to the gate line _GK) is used as it is. 20), the source voltage setting circuit 70 needs to charge / discharge the source line charges by ΔVs1 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the source voltage setting circuit 70 may charge and discharge the source line charges by ΔVs2 (ΔVs2 <ΔVs1) as shown in FIG. For example, as shown in FIG. 20, by precharging to the precharge voltage PV, the amount of charge to be charged / discharged from the source line may increase, but the source line is charged / discharged as in the next 1H. In some cases, the amount of charge to be reduced can be significantly reduced.

  Furthermore, even when the charge cannot be sufficiently charged / discharged only by the charge recycle period, by providing the precharge period, it is possible to shorten the writing time of the pixel electrode to be completed within 1H.

Next, in the drive period (TT30) after the precharge period, in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _j and S _k are electrically connected to the output of the output buffer of the source driver 20, respectively. The Further, the source charge storage switch CSW and the voltage setting switch PSW are set in a non-conducting state. Therefore, in the driving period, the source lines S _j and S _k are driven by the output buffer of the source driver 20.

Similarly, in the drive period (TT30) after the precharge period, the common electrode charge storage switch VSW is set in a non-conductive state, and the common electrode CE is electrically connected to the output of the common electrode voltage generation circuit 56 of the power supply circuit 50. Connected to. Therefore, in the driving period, the common electrode voltage VCOM is supplied to the common electrode CE and the common electrode voltage generation circuit 56. At this time, the common electrode voltage generation circuit 56 charges and discharges the common electrode CE until the high potential side voltage VCOMH is reached with reference to the potential after the change in the charge recycle period TT10. Therefore, in the driving period after the charge recycling period, the voltage of the counter electrode CE that should be changed by the counter electrode voltage generation circuit 56 may be low. That is, based on the potential of the counter electrode CE in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection of pixels connected to the gate line _GK) is used as it is. In order to set the potential of the counter electrode CE during (period), the counter electrode voltage generation circuit 56 needs to charge / discharge the charge of the counter electrode CE by ΔVc1 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the counter electrode voltage generation circuit 56 only needs to charge / discharge the charge of the counter electrode CE by ΔVc2 (ΔVc2 <ΔVc1) as shown in FIG.

  In the next horizontal scanning period, a charge recycle period, a precharge period, and a drive period are provided, and the same is performed in each period. The operation in the charge recycling period in FIG. 20 is control in the second operation mode.

  Since the power consumption accompanying the drive of the source line in the charge reuse period depends on the voltage (that is, the gradation data) to be set by the source driver 20 in the drive period, the effect of reducing the power consumption by the charge reuse is obtained. It will fade. However, since the counter electrode CE is set to either the high potential side voltage VCOMH or the low potential side voltage VCOML, the power consumption can be reliably reduced with a simple configuration without depending on the display data. The effect of reducing power consumption by reusing charges is remarkable.

  As described above, in the first operation mode, charge reuse can be achieved without using the first and second capacitor elements CCS and CCV, so that the chip size and mounting area of the display driver 60 can be reduced. On the other hand, since a voltage corresponding to the display data is applied to the source line, the effect of charge reuse depends on the display data.

  On the other hand, in the second operation mode, since the counter electrode voltage is binary, the effect of reusing the charge of the counter electrode CE appears, so that the effect of low power consumption can be obtained with certainty. On the other hand, since the charge is reused without using the first or second capacitor elements CCS and CCV, the chip size and mounting area of the display driver 60 cannot be reduced.

  According to this embodiment, when reusing charges, it is possible to realize charge recycle in any one of the above operation modes by simply providing the node short-circuit switch HSW. As a result, the manufacturing cost can be further reduced.

  Furthermore, by providing the source voltage setting circuit 70, it is possible to reduce the power consumption accompanying the precharge of the source line by reusing the charge, and to shorten the writing time of the pixel electrode by reusing the charge. It can be said.

4.3 Third Control Method FIG. 21 shows an example of the control timing of the third control method shown in FIG.

In FIG. 21, it is assumed that each source output switching circuit of the source output switching circuits SSW _{1 to} SSW _N includes a source short-circuit switch, and the control state of the source short-circuit switch included in each source output switching circuit is set as the control state of each source output switching circuit. Show. In FIG. 21, “ON” of each switch indicates that the switch is in a conductive state, and “OFF” of each switch indicates that the switch is in a non-conductive state.

  In the third control method, a charge recycle period and a precharge period are provided prior to a drive period in which the source output operational amplifier drives the source line based on the grayscale voltage corresponding to the grayscale data.

In the charge recycle period, the source output switching circuits SSW _{1 to} SSW _N are turned off (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned off), the source charge storage switch The CSW is turned off, the counter electrode charge storage switch VSW is turned on, the node short-circuit switch HSW is turned off, and the voltage setting switch PSW is turned off. That is, in FIG. 14, the source short circuit switches of the source output switching circuits SSW _j and SSW _k are set to OFF, the source charge accumulation switch CSW is turned off, the counter electrode charge accumulation switch VSW is turned on, and the node short circuit switch HSW is turned off.

As a result, in the charge recycling period, the source lines S _{1 to SN} and the shared line COL are not short-circuited, and the charges of the source lines S _{1 to SN} are not reused. On the other hand, the common electrode voltage output node VND is electrically connected to one end of the first capacitor element CCV. Therefore, the charge is reused by the charge moving so that the common electrode voltage output node VND and one end of the first capacitor element CCV have the same potential.

Next, in the precharge period, the same control as in the precharge period of FIG. 17 or FIG. 19 is performed. That is, the source output switching circuits SSW _{1 to} SSW _N are turned on (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned on), the source charge storage switch CSW is turned on, The common electrode charge storage switch VSW is turned off, the node short circuit switch HSW is turned off, and the voltage setting switch PSW is turned on. That is, in FIG. 14, the source short circuit switches of the source output switching circuits SSW _j and SSW _k are set to ON, the node short circuit switch HSW is OFF, the source charge storage switch CSW is ON, and the counter electrode charge storage switch VSW is OFF. The Then, the source voltage setting circuit 70 supplies the precharge voltage PV to the source charge storage node C2ND.

As a result, the precharge voltage is applied to the source lines S _{1 to} S _N via the shared line COL.

In the drive period after the precharge period, the source output switching circuits SSW _{1 to} SSW _N are turned off (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned off), and the source charge The storage switch CSW is turned off, the counter electrode charge storage switch VSW is turned off, the node short-circuit switch HSW is turned off, and the voltage setting switch PSW is turned off. Then, the operational amplifier circuit block _OPC 1 _{~OPC N} supplies a gradation voltage corresponding to the grayscale data to the source line _S 1 to S _N.

4.4 Fourth Control Method FIG. 22 shows an example of the control timing of the fourth control method shown in FIG.

In FIG. 22, each source output switching circuit of the source output switching circuits SSW _{1 to} SSW _N includes a source short-circuit switch, and the control state of the source short-circuit switch included in each source output switching circuit is set as the control state of each source output switching circuit. Show. In FIG. 22, “ON” of each switch indicates that the switch is in a conductive state, and “OFF” of each switch indicates that the switch is in a non-conductive state.

  In the fourth control method, a precharge period is provided prior to the driving period in which the source output operational amplifier drives the source line based on the gradation voltage corresponding to the gradation data.

In the precharge period, the same control as in the precharge period of FIG. 17, FIG. 19 or FIG. 21 is performed. That is, the source output switching circuits SSW _{1 to} SSW _N are turned on (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned on), the source charge storage switch CSW is turned on, The common electrode charge storage switch VSW is turned off, the node short circuit switch HSW is turned off, and the voltage setting switch PSW is turned on. That is, in FIG. 14, the source short circuit switches of the source output switching circuits SSW _j and SSW _k are set to ON, the node short circuit switch HSW is OFF, the source charge storage switch CSW is ON, and the counter electrode charge storage switch VSW is OFF. The Then, the source voltage setting circuit 70 supplies the precharge voltage PV to the source charge storage node C2ND.

As a result, the precharge voltage is applied to the source lines S _{1 to} S _N via the shared line COL.

In the drive period after the precharge period, the source output switching circuits SSW _{1 to} SSW _N are turned off (more specifically, the source short circuit switches of the source output switching circuits SSW _{1 to} SSW _N are turned off), and the source charge The storage switch CSW is turned off, the counter electrode charge storage switch VSW is turned off, the node short-circuit switch HSW is turned off, and the voltage setting switch PSW is turned off. Then, the operational amplifier circuit block _OPC 1 _{~OPC N} supplies a gradation voltage corresponding to the grayscale data to the source line _S 1 to S _N.

  The third and fourth control methods are control methods in which a part of the second control method is omitted. Therefore, as described in detail for the first or second control method as shown in FIG. 18 or FIG. 20, those skilled in the art realize the third and fourth control methods with reference to FIG. 18 or FIG. it can.

  As described above, the display driver 60 according to the present embodiment has the configuration illustrated in FIG. 14, and therefore, when reusing charges, priority is given to low power consumption or low cost with a simple configuration. I can do it. Further, the display driver 60 writes a desired gradation voltage to the source line or the pixel electrode electrically connected to the source line at a high speed by the precharge function even when the charge is reused. Can do.

5. In the present embodiment, the power supply circuit 50 realizes the function of the panel load measuring device by considering the load on the display panel 12 based on the load of the counter electrode CE. However, the present invention is not limited to this. In a variation of this embodiment, even if the function of the panel load measuring device considers load of the display panel 12 by the load of one source line S _L of the source lines S ₁ to S _N to achieve the source driver 20 Good.

  FIG. 23 shows a main configuration part for measuring the load on the display panel 12 in a modification of the present embodiment. In FIG. 23, the same parts as those in FIG. 1 or FIG.

  In FIG. 23, the source driver 20 includes a source line driving unit 180 and a panel load measuring unit 190.

The source line driver 180 includes the shift register 22, the line latches 24 and 26, the reference voltage generation circuit 27, the DAC 28, the output buffer 29, the charge reuse controller 150 and the precharge controller 160 shown in FIG. At this time, the source line driver 180, via a source line connecting points SEP of the display panel 12, supplies a voltage (measurement voltage or gradation voltage) to the source line S _L.

  The panel load measuring unit 190 receives the measurement signal FBS from the display panel 12 and obtains the load on the display panel 12 based on the delay time of the measurement signal FBS.

  FIG. 24 is an explanatory diagram of the delay time of the measurement signal FBS of FIG.

Panel load measuring unit 190, based on the timing of starting the supply of the voltage to the source line S _L, 2 minutes of the first voltage amplitude of the measuring signal FBS voltage given threshold voltage Vths (eg measurement signal FBS ) Is obtained as a delay time Δt2.

  The panel load measurement unit 190 stores in advance a control signal tEQ that defines a charge recycle period and a control signal tPR that defines a precharge period corresponding to the delay time, and delay time Δt2 as in FIG. The control signals tEQ and tPR corresponding to are output. The charge reuse controller 150 and the precharge controller 160 of the source line driver 180 perform charge reuse control and precharge control only for a period corresponding to the control signals tEQ and tPR.

  In FIG. 24, the rising timing of the source voltage has been described as an example, but the same applies to the falling timing of the source voltage.

  FIG. 25 is a block diagram showing a configuration example of the panel load measuring unit 190 shown in FIG.

  The panel load measuring unit 190 can include a comparator 192, a counter 194, and a period table 196. The comparator 192 compares the voltage of the measurement signal FBS with the threshold voltage VTHs, and outputs a pulse when the voltage of the measurement signal FBS reaches the threshold voltage VTHs, for example. The counter 194 counts up the count value in synchronization with the reference clock. The counter 194 initializes the count value at the source output change timing. In addition, the counter 194 latches the count value with the pulse from the comparator 192 and outputs it to the period table 196 as the count value CNT.

Similarly to the period table 116 in FIG. 7, the period table 196 stores the length of the charge reuse period and the length of the precharge period for each count value CNT from the counter 194 in advance. In response to the count value CNT, a control signal tEQ that defines a charge recycle period and a control signal tPR that defines a precharge period are output. Thus, the period table 196, considers the delay time corresponding to the load of the source line S _L as the count value of the counter 194, the drive control of the source line in the charge recycle period corresponding to the count value and the precharge period You can contribute.

In the period table 196, the precharge voltage PV supplied to the source line during the precharge period is stored in advance for each count value CNT from the counter 114 as in FIG. A control signal designating a precharge voltage can be output in accordance with the value CNT. Therefore, the period table 196, considers the delay time corresponding to the load of the source line S _L as the count value of the counter 194, which is to change the precharge voltage corresponding to the count value.

As described above, the panel load measuring unit 190 displays the load corresponding to the time required for the measurement signal FBS to reach the predetermined threshold voltage VTHs (threshold) with reference to the change timing of the source output. It can be obtained as a load. Therefore, the source load measuring connection point SZP is, that the load of the source line S _L as viewed from the source line connection points SEP is provided so as to maximize, it can be obtained easily and reliably delay time Δt2 As a result, the load on the display panel 12 can be obtained with higher accuracy.

6). Electronic Device FIG. 26 shows a block diagram of a configuration example of the electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera, and supplies image data captured by the CCD camera to the display controller 540 in the YUV format. The display controller 540 has the function of the display controller 40 of FIG. 1 or FIG.

  The mobile phone 900 includes a display panel 512. The display panel 512 is driven by the source driver 520 and the gate driver 530. The display panel 512 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels. The display panel 512 has the function of the display panel 12 shown in FIG.

  The display controller 540 is connected to the source driver 520 and the gate driver 530 and supplies gradation data in RGB format to the source driver 520.

  The power supply circuit 542 is connected to the source driver 520 and the gate driver 530, and supplies a driving power supply voltage to each driver. The power supply circuit 542 has the function of the power supply circuit 50 of FIG. 1 or FIG. The display driver 544 includes a source driver 520, a gate driver 530, and a power supply circuit 542, and the display driver 544 can drive the display panel 512.

  The host 940 is connected to the display controller 540. The host 940 controls the display controller 540. In addition, the host 940 can supply the gradation data received via the antenna 960 to the display controller 540 after demodulating by the modem 950. The display controller 540 causes the display panel 512 to display the source driver 520 and the gate driver 530 based on the gradation data. The source driver 520 has the function of the source driver 20 shown in FIG. The gate driver 530 has the function of the gate driver 30 shown in FIG.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the display panel 512 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the present embodiment, the source lines are all short-circuited to the shared line COL. However, the present invention is not limited to this. One source line may be short-circuited with the common line COL, but it is desirable that there are a plurality of source lines short-circuited with the common line COL.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention may be made dependent on another independent claim.

1 is a block diagram of a configuration example of a liquid crystal device according to an embodiment. Explanatory drawing of the example of a drive control of the source line in 1 horizontal scanning period in this embodiment. The block diagram of the other structural example of the liquid crystal device of this embodiment. The figure which shows the structure principal part for measuring the load of the display panel in this embodiment. Explanatory drawing of the delay time of the signal for a measurement of FIG. The block diagram of the structural example of the panel load measurement part of FIG. The figure which shows the outline | summary of a structure of the period table of FIG. FIG. 4 is a block diagram of a configuration example of the source driver in FIG. 1 or FIG. 3. FIG. 4 is a block diagram of a configuration example of the source driver in FIG. 1 or FIG. 3. The figure which shows the structural example of the gate driver of FIG. 1 or FIG. The figure which shows the structural example of the power supply circuit of FIG. 1 or FIG. FIG. 4 is a diagram illustrating an example of a driving waveform of the display panel of FIG. 1 or FIG. 3. Explanatory drawing of polarity inversion drive. The figure which shows the structure principal part of the display driver of this embodiment. The relationship between the power supply voltages VDD and VDDHS is shown. Explanatory drawing of the example of control of the display driver of this embodiment. The figure which shows an example of the control timing of the 1st control system of FIG. The wave form diagram of the operation example of the liquid crystal device controlled by a 1st control system. The figure which shows an example of the control timing of the 2nd control system of FIG. The wave form diagram of the operation example of the liquid crystal device controlled by a 2nd control system. The figure which shows an example of the control timing of the 3rd control system of FIG. The figure which shows an example of the control timing of the 4th control system of FIG. The figure which shows the structure principal part for measuring the load of the display panel in the modification of this embodiment. FIG. 24 is an explanatory diagram of a delay time of the measurement signal in FIG. The block diagram of the structural example of the panel load measurement part of FIG. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal device, 12 display panel, 20 source driver,
30 gate driver, 40 display controller, 50 power supply circuit,
58, 110, 190 Panel load measuring unit, 60 Display driver,
70 source voltage setting circuit, 100 counter electrode drive unit, CCS second capacitor element,
CCV first capacitive element, CE counter electrode, CEP counter electrode connection point,
COL common line, CSW source charge storage switch,
Connection point for CZP counter electrode load connection, FBC, FBS measurement signal,
G ₁ ~G _M gate lines, HSW node shorting switches, _S 1 to S _N source line,
SEP source line connection point, SSW _{1 to} SSW _N source output switching circuit,
SZP source load measurement connection point, tEQ, tPR control signal,
TL1 first capacitor element connection terminal, TL2 second capacitor element connection terminal,
VCOM Counter electrode voltage, VSW Counter electrode charge storage switch

Claims (19)

A plurality of source lines, a plurality of gate lines, a plurality of switch elements each of which is specified by each source line and each gate line, a plurality of pixel electrodes each of which is connected to each of the switch elements, A load measuring device for measuring a load of a display panel including a counter electrode provided facing the plurality of pixel electrodes,
A counter electrode driver for supplying a counter electrode voltage to the counter electrode electrically connected to the counter electrode connection point via the counter electrode connection point provided on the display panel;
A panel load measurement unit that receives a measurement signal through a counter electrode load measurement connection point that is provided in the display panel and is electrically connected to the counter electrode, and obtains the load of the display panel using the measurement signal And a load measuring device. In claim 1,
The panel load measuring unit is
A load measuring apparatus, wherein a load corresponding to a time required for the level of the measurement signal to reach a predetermined threshold is obtained as a load of the display panel based on a change timing of the counter electrode voltage. In claim 1 or 2,
A load measuring apparatus using the measurement signal from the counter electrode load measuring connection point provided on the display panel so that the load on the counter electrode is maximized with reference to the counter electrode connection point. . A load measuring device for measuring a load of a display panel including a plurality of source lines, a plurality of gate lines, and a plurality of pixels each pixel being specified by each source line and each gate line,
A source line driver for supplying a source voltage to a source line electrically connected to the source line connection point via a source line connection point provided on the display panel;
A panel load measuring unit which receives a measurement signal via a connection point for measuring a source load provided in the display panel and electrically connected to the source line, and obtains a load of the display panel using the measurement signal; A load measuring device comprising: In claim 4,
The panel load measuring unit is
A load measuring apparatus, wherein a load corresponding to a time required for the level of the measurement signal to reach a predetermined threshold is obtained as a load of the display panel based on a change timing of the source voltage. In claim 4 or 5,
The load measurement apparatus using the measurement signal from the source load measurement connection point provided on the display panel so that the load on the source line is maximized with reference to the source line connection point. A plurality of source lines, a plurality of gate lines, a plurality of switch elements each of which is specified by each source line and each gate line, a plurality of pixel electrodes each of which is connected to each of the switch elements, A drive circuit for driving a display panel including the plurality of pixel electrodes and a counter electrode provided to face the pixel electrode;
The load measuring device according to any one of claims 1 to 3, wherein a load of the display panel is obtained;
A source line driving unit that drives the plurality of source lines based on a gradation voltage corresponding to gradation data,
The source line driver is
A drive circuit that drives the plurality of source lines based on the load of the display panel obtained by the load measuring device. A display including a plurality of source lines, a plurality of gate lines, a plurality of switch elements in which each switch element is specified by each source line and each gate line, and a plurality of pixels in which each pixel is connected to each switch element A driving circuit for driving a panel,
The load measuring device according to any one of claims 4 to 6, wherein a load of the display panel is obtained;
A source line driving unit that drives the plurality of source lines based on a gradation voltage corresponding to gradation data,
The source line driver is
A drive circuit that drives the plurality of source lines based on the load of the display panel obtained by the load measuring device. In claim 7 or 8,
The source line driver is
After short-circuiting the counter electrode and at least one of the plurality of source lines for a charge recycling period corresponding to the load, the plurality of source lines are connected based on a gradation voltage corresponding to gradation data of each source line. A driving circuit characterized by driving. In claim 7 or 8,
The source line driver is
After at least one of the plurality of source lines is short-circuited with one end of a capacitor only during a charge recycling period corresponding to the load, the gray scale data of each source line is handled in a state of being electrically disconnected from the capacitor. A driving circuit which drives the plurality of source lines based on a gradation voltage. In claim 7 or 8,
The source line driver is
The plurality of source lines are driven based on the gradation voltage corresponding to the gradation data of each source line after the plurality of source lines are precharged for a precharge period corresponding to the load. Drive circuit. In claim 7 or 8,
The source line driver is
After short-circuiting the counter electrode and at least one of the plurality of source lines only during a charge recycling period corresponding to the load, precharging the plurality of source lines only during a precharge period corresponding to the load, A driving circuit for driving the plurality of source lines based on a gradation voltage corresponding to gradation data of each source line. In claim 7 or 8,
The source line driver is
After short-circuiting at least one of the plurality of source lines with one end of a capacitor for a charge recycle period corresponding to the load, precharging the plurality of source lines for a precharge period corresponding to the load, A drive circuit, wherein the plurality of source lines are driven based on a grayscale voltage corresponding to grayscale data of each source line while being electrically disconnected from the capacitor. Multiple source lines,
Multiple gate lines,
A plurality of switch elements, each switch element being specified by each source line and each gate line;
A plurality of pixel electrodes, each pixel electrode being connected to each switch element;
A counter electrode provided to face the plurality of pixel electrodes;
A gate driver that scans the plurality of gate lines;
A source driver for driving the plurality of source lines based on gradation data;
An electro-optical device comprising the load measuring device according to claim 1. Multiple source lines,
Multiple gate lines,
A plurality of switch elements, each switch element being specified by each source line and each gate line;
A plurality of pixels, each pixel connected to each switch element;
A gate driver that scans the plurality of gate lines;
A source driver for driving the plurality of source lines based on gradation data;
An electro-optical device comprising the load measuring device according to claim 4. Multiple source lines,
Multiple gate lines,
A plurality of switch elements, each switch element being specified by each source line and each gate line;
A plurality of pixel electrodes, each pixel electrode being connected to each switch element;
A gate driver that scans the plurality of gate lines;
14. An electro-optical device comprising: the drive circuit according to claim 7 that drives the plurality of source lines.   An electronic apparatus comprising the load measuring device according to claim 1.   An electronic device comprising the drive circuit according to claim 7.   An electronic apparatus comprising the electro-optical device according to claim 15.

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