JP4487883B2 - 電子部品内蔵モジュールの製造方法 - Google Patents
電子部品内蔵モジュールの製造方法 Download PDFInfo
- Publication number
- JP4487883B2 JP4487883B2 JP2005224865A JP2005224865A JP4487883B2 JP 4487883 B2 JP4487883 B2 JP 4487883B2 JP 2005224865 A JP2005224865 A JP 2005224865A JP 2005224865 A JP2005224865 A JP 2005224865A JP 4487883 B2 JP4487883 B2 JP 4487883B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- component built
- adhesive layer
- electrode
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83874—Ultraviolet [UV] curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
図1は、本発明の第1の実施の形態における電子部品内蔵モジュールの構成を示す概略断面図である。
図3は、本発明の第2の実施の形態における電子部品内蔵基板の構成を示す概略断面図である。図3において、図1と同じ構成要素については同じ符号を用い説明を省略する。
以下に、本発明の第3の実施の形態における電子部品内蔵モジュールおよび電子部品内蔵基板の製造方法について、図5を用いて説明する。
20 接着層
30 能動素子
40 受動素子
50 突起電極
60 電極端子
70 絶縁層
80 配線パターン
100 注入用治具
110 封止樹脂
120 注入装置
Claims (3)
- 樹脂フィルム基材の少なくとも一方の面全面に接着層を形成する工程と、
一方の面に少なくとも電極を有する複数の電子部品の他方の面を前記接着層を介して前記フィルム基材の所定の位置に固着する工程と、
シート状の封止樹脂を前記複数の電子部品の電極が露出するように圧入して埋設する工程と、
を含むことを特徴とする電子部品内蔵モジュールの製造方法。 - 前記接着層が接着フィルムである請求項1記載の電子部品内蔵モジュールの製造方法。
- 前記複数の電子部品は、受動素子である請求項1または2に記載の電子部品内蔵モジュールの製造方法。
ある。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005224865A JP4487883B2 (ja) | 2005-08-03 | 2005-08-03 | 電子部品内蔵モジュールの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005224865A JP4487883B2 (ja) | 2005-08-03 | 2005-08-03 | 電子部品内蔵モジュールの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007042829A JP2007042829A (ja) | 2007-02-15 |
JP4487883B2 true JP4487883B2 (ja) | 2010-06-23 |
Family
ID=37800542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005224865A Expired - Fee Related JP4487883B2 (ja) | 2005-08-03 | 2005-08-03 | 電子部品内蔵モジュールの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4487883B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5235312B2 (ja) * | 2007-02-22 | 2013-07-10 | サンデン株式会社 | インバータ一体型電動圧縮機の製造方法 |
TWI452083B (zh) | 2008-10-21 | 2014-09-11 | Ajinomoto Kk | Thermosetting resin composition |
JP5892388B2 (ja) | 2011-01-12 | 2016-03-23 | 株式会社村田製作所 | 樹脂封止型モジュール |
CA2935372C (en) * | 2014-01-06 | 2023-08-08 | Mc10, Inc. | Encapsulated conformal electronic systems and devices, and methods of making and using the same |
CN107530004A (zh) | 2015-02-20 | 2018-01-02 | Mc10股份有限公司 | 基于贴身状况、位置和/或取向的可穿戴式设备的自动检测和构造 |
EP3420732B8 (en) | 2016-02-22 | 2020-12-30 | Medidata Solutions, Inc. | System, devices, and method for on-body data and power transmission |
JP6691816B2 (ja) * | 2016-05-18 | 2020-05-13 | 東京応化工業株式会社 | 封止体の製造方法 |
US10447347B2 (en) | 2016-08-12 | 2019-10-15 | Mc10, Inc. | Wireless charger and high speed data off-loader |
-
2005
- 2005-08-03 JP JP2005224865A patent/JP4487883B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2007042829A (ja) | 2007-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4487883B2 (ja) | 電子部品内蔵モジュールの製造方法 | |
KR100987688B1 (ko) | 프린트 배선 기판 및 프린트 배선 기판의 제조 방법 | |
US8336201B2 (en) | Method of manufacturing printed circuit board having flow preventing dam | |
US9773766B2 (en) | Semiconductor device including independent film layer for embedding and/or spacing semiconductor die | |
US20080093115A1 (en) | Interposer, electrical package, and contact structure and fabricating method thereof | |
US8294253B2 (en) | Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure | |
US20100163168A1 (en) | Method for manufacturing wiring board with built-in component | |
TWI454199B (zh) | 印刷電路板之製造方法 | |
US20100163172A1 (en) | Method for manufacturing wiring board with built-in component | |
US20080264899A1 (en) | Interconnect structure with stress buffering ability and the manufacturing method thereof | |
US20180177045A1 (en) | Embedding Component in Component Carrier by Component Fixation Structure | |
KR101065935B1 (ko) | 전자 부품 실장 장치 및 그 제조 방법 | |
US9293438B2 (en) | Method for making electronic device with cover layer with openings and related devices | |
JPWO2006109383A1 (ja) | 配線基板を有する電子デバイス、その製造方法、および前記電子デバイスに用いられる配線基板 | |
US9105616B2 (en) | External connection terminal, semiconductor package having external connection terminal, and methods for manufacturing the same | |
JP2005191156A (ja) | 電気部品内蔵配線板およびその製造方法 | |
US20100059876A1 (en) | Electronic component package and method of manufacturing the same | |
KR19980063532A (ko) | 반도체 장치와 그의 제조방법 및 필름 캐리어 테이프와 그의 제조방법 | |
JP4158714B2 (ja) | 電子部品実装済基板の製造方法 | |
JPWO2011030542A1 (ja) | 電子部品モジュールおよびその製造方法 | |
JP2008218758A (ja) | 電子回路実装構造体 | |
JP4870501B2 (ja) | 電子部品内蔵基板の製造方法 | |
JP2004363566A (ja) | 電子部品実装体及びその製造方法 | |
KR20030019439A (ko) | 반도체장치 | |
US6492715B1 (en) | Integrated semiconductor package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070829 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080205 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091020 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20091126 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091218 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100119 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100209 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100309 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100322 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130409 Year of fee payment: 3 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4487883 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130409 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130409 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140409 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |