JP4481561B2 - Mask for semiconductor devices - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a mass for manufacturing a semiconductor device having a multi-chip configuration.ToRelated.
[0002]
[Prior art]
Conventionally, a step-and-repeat method and a step-and-scan method are widely used to expose a wafer with a fine pattern of a mask using an exposure apparatus. In the step-and-repeat method, a circular wafer is placed on a two-dimensionally movable wafer stage, and the wafer stage is sequentially stepped in the X and Y directions while irradiating the wafer with light through a mask on which a device pattern is drawn. The device pattern is transferred to the wafer, and a large number of device patterns are drawn vertically and horizontally. Similarly, in the step-and-scan method, the wafer stage is sequentially stepped in the X and Y directions, and the wafer stage is synchronized with the mask stage that holds the mask on which the device pattern is drawn while irradiating light only in the slit-shaped exposure area. By scanning, the device pattern drawn on the mask is transferred onto the wafer, and a large number of device patterns are drawn vertically and horizontally.
[0003]
However, regardless of whether the step-and-repeat method or the step-and-scan method is used, the wafer to which the device pattern is transferred is circular, whereas the shot area to be exposed is rectangular. In the peripheral part, a part of the shot area is chipped, and a chip that does not transfer a part of the device pattern is generated.
[0004]
Also, in this chipped shot area, the focus (wafer stage height) performed during the exposure process and the wafer surface height detection position necessary for leveling (stage tilt) adjustment protrude outside the wafer, so that accurate adjustment cannot be performed. There is a problem.
[0005]
To solve this problem, there is a method in which the information on the wafer surface height acquired in the adjacent shot area is applied as it is before the stepping to the shot area to be exposed, and the adjustment is made for convenience.
[0006]
However, the peripheral portion of the wafer is warped due to heat treatment applied in the manufacturing process, or the uneven state is different from the central portion of the wafer due to variations in the surface of a polishing process such as CMP (Chemical Mechanical Polishing). There is a big difference in inclination. For this reason, the method of applying the information of adjacent shot areas as they are is not necessarily an effective method.
[0007]
FIG. 1 is a diagram showing a semiconductor device mask that has been generally used.
[0008]
As shown in FIG. 1, a plurality of device patterns 2 are usually drawn on a semiconductor device mask 1, and a plurality of chips are simultaneously formed by exposing the plurality of device patterns 2 to a wafer at once. It is configured to be.
[0009]
FIG. 2 is a diagram illustrating an example of a wafer onto which a plurality of device patterns drawn on a mask are transferred.
[0010]
In FIG. 2, the circular wafer 10 has a boundary (referred to as “wafer edge”) between an invalid area 11 b that is not used for manufacturing product chips and an effective area 11 a that is used. The width of the invalid area 11b is, for example, 4 mm. On the circular wafer 10, 58 shot areas (areas exposed by one stepping operation) 12 of 24 mm × 24 mm indicated by a solid line formed by exposing the device pattern of the mask are formed. Of these, 16 chip regions (indicated by dotted lines) to which one device pattern is exposed are formed in the shot region 12a that does not cover the invalid region 11b.
[0011]
However, in the shot region 12b formed in the peripheral portion of the wafer where a part of the shot region protrudes from the wafer edge 11, a chip chip indicated by x is generated. In the peripheral shot area 12b, focus and leveling are not adjusted over the entire shot area, and therefore defocusing easily occurs. In particular, the chip 13 indicated by Δ is easily defocused.
[0012]
Therefore, in a step-and-repeat type exposure apparatus, when a forbidden band having a certain width is provided around the wafer, and a part of the forbidden band exists and the remaining part is exposed outside the wafer, In some cases, the stage is shifted to the boundary position of the forbidden band, focus adjustment is performed, and the exposure is returned to the original position again (see Patent Document 1).
[0013]
Further, in a step-and-scan type exposure apparatus, the main purpose of improving throughput is to expose only the chip that can be taken (the whole is within the wafer edge) instead of performing exposure around the wafer for one shot. . As a result, the measurement of the focus around the wafer also reduces the measurement error because there is no exposure area outside the wafer (see Patent Document 2).
[0014]
[Patent Document 1]
JP-A-6-29186 (paragraph numbers 0029 to 0039, FIGS. 7 and 8)
[Patent Document 2]
Japanese Patent Laid-Open No. 9-22863 (paragraph numbers 0007 to 0019, 0034 to 0038, FIGS. 3, 5, 6 and 11)
[0015]
[Problems to be solved by the invention]
However, even the method disclosed in Patent Document 1 cannot prevent the occurrence of chipped chips. The fine pattern formed on the chip chip is peeled off during the subsequent manufacturing process and becomes a generation source of particles. As a result, the yield decreases. Further, this method requires complicated stage control, and there is a possibility that a focus shift occurs when returning to the exposure position after performing the focus control.
[0016]
Although the method disclosed in Patent Document 2 can be applied satisfactorily when exposing a mask in which a plurality of device patterns are arranged only in the scan direction as shown in the embodiment of this document. When a plurality of device patterns are arranged in a direction perpendicular to the scan direction, it is difficult to apply. That is, if the wafer is used without waste, the generation of chipped chips cannot be prevented.
[0017]
Furthermore, even when the device patterns are arranged only in one line in the direction perpendicular to the scanning direction, as described in paragraph 0038 of this document, it is possible to completely prevent the occurrence of chipped chips. Can not.
[0018]
Further, the method of Patent Document 2 cannot completely prevent the occurrence of defocus. For example, in FIG. 2 of the present specification, if scanning is performed in the vertical direction of the drawing, even if the method of Patent Document 2 is applied, defocusing is likely to occur in the chip 13 marked Δ. This is because a part of the wafer surface height detection position (for example, CR1 and CR3 in FIG. 6 of Patent Document 2) placed at a position close to both ends of the slit-shaped exposure region protrudes from the wafer edge.
[0019]
  In view of the above circumstances, the present invention avoids the generation of chipped chips that are particles generation sources. Also, together with particles, a mass for semiconductor devices that can reduce defocus, which causes a decrease in yield, as much as possible.TheThe purpose is to provide.
[0020]
[Means for Solving the Problems]
  The semiconductor device mask of the present invention that achieves the above object has a plurality of identical device patterns, and exposes the wafer by projecting the device pattern onto a wafer placed on a wafer stage of a projection exposure apparatus. A mask for a semiconductor device
  One central area where two device patterns are arranged vertically and horizontally,
  In the central areaTwo opposite sidesPlaced outside,Two first peripheral regions in which two device patterns are arranged horizontally;
  Two second peripheral regions arranged outside the two sides excluding the two opposite sides of the central region, and two device patterns arranged vertically;
  Four third peripheral regions arranged outside the two opposite sides of the central region and outside the two sides excluding the two opposite sides of the central region, wherein one device pattern is arranged ,
  The central region andThe first, second and thirdBetween surrounding areasAs well asAdjacentThe first, second and thirdLocated between the surrounding areas, the areas are separated from each other by blocking the irradiated light.And a width wider than the width of the scribe area between the device patterns in the central area.It has a shading zone.
[0021]
As described above, the semiconductor device mask is divided into a plurality of regions, and a light-shielding band is provided at the boundary between the regions, so that the light can be shielded blindly except for the required region. Using this mask, device patterns provided in appropriate areas in the central and peripheral parts of the wafer can be projected and exposed to the inside of the wafer edge to prevent chipping. is there. Furthermore, by optimizing the shading band, it is possible to appropriately operate the adjustment function of the exposure apparatus regardless of the size of each region and prevent the occurrence of defocusing.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0027]
FIG. 3 is a schematic block diagram showing the main part of the exposure apparatus used in the embodiment of the exposure method of the present invention.
[0028]
The exposure apparatus 50 is used as an embodiment of the exposure method of the present invention, and the semiconductor device mask used in the exposure apparatus corresponds to the embodiment of the semiconductor device mask of the present invention.
[0029]
The main part of the exposure apparatus 50 shown in FIG. 3 is an illumination system 20 composed of a light source and a lens, a mask blind 21, and a semiconductor device mask in which a plurality of identical device patterns are arranged (hereinafter referred to as “mask”). 22, a mask holder 23 that holds 22, a projection optical system 24 that forms a reduced image of a device pattern drawn on the mask on the wafer, an XYZ stage device 25, and a holder 26 that holds the wafer 30 on the XYZ stage device 25. And a wafer surface height detection system 27 that includes a plurality of light emitting units 27a and a plurality of light receiving sensors 27b and detects the height of the position of the wafer surface.
[0030]
The mask blind 21 is composed of two sets of blades, and regulates a rectangular illumination area that illuminates the mask 22 from the illumination system to a predetermined size. The reduction ratio of the projection optical system is 1/4, for example. The XYZ stage device 25 is mounted on the XY stage that reciprocates in the X-axis direction and the Y-axis direction perpendicular to the optical axis, and is reciprocated in the Z-axis direction parallel to the optical axis, and has an inclination. It consists of a Z stage that can be controlled. By placing the wafer 30 on the wafer holder 26 on the XYZ stage device 25, the wafer 30 can be freely moved in the XY plane and in the Z-axis direction, and the inclination with respect to the optical axis can be adjusted. Each of the plurality of light emitting units 27 a of the wafer surface height detection system 27 irradiates light from a diagonal direction to a predetermined position (wafer surface height detection position) on the surface of the wafer 30. Then, the light reflected in the oblique direction on the surface of the wafer 30 is received by the light receiving sensors 27b provided corresponding to the respective light emitting portions 27a. The light receiving sensor 27b has a position detection function, and detects the height of the irradiated position on the wafer surface based on the position where the reflected light is detected. That is, the height of a plurality of detection positions on the wafer surface is detected using a plurality of sets of light emitting units 27a and light receiving sensors 27b.
[0031]
Prior to the actual exposure of the wafer 30, shot area assignment is performed to determine how the shot area to be exposed on which device pattern provided on the mask 22 is arranged on the wafer 30. Then, the wafer 30 is placed on a wafer holder 26 on the XYZ stage device 25 (hereinafter, the XYZ stage device and the wafer holder are collectively referred to as a “wafer stage”), and a predetermined position is determined according to a predetermined shot area allocation. And exposure of each shot area is performed. At this time, as will be described later, the mask blind 21 is adjusted, and only necessary ones of a plurality of device patterns arranged on the mask are projected onto the wafer. Further, for each shot area, the wafer surface height detection system 27 detects the height of the wafer surface, and based on the result, controls at least one of the height and tilt of the wafer stage, so Adjustment is performed so that the projection optical system is focused on the wafer surface (hereinafter, stage height adjustment and tilt adjustment are collectively referred to as “focus adjustment”).
[0032]
Hereinafter, the exposure procedure will be described more specifically by dividing it into a step-and-repeat method and a step-and-scan method.
[0033]
In the case of a step-and-repeat type exposure apparatus, at the time of exposure, the mask holder 23 is fixed at a predetermined position, and the portion of the mask 22 within the illumination area restricted by the mask blind 21 is illuminated. A pattern obtained by reducing the pattern on the mask provided in the illumination area with the reduction ratio of the projection optical system 24 is reduced, and the illumination area on the surface of the wafer 30 positioned under the projection optical system 24 is reduced with the reduction ratio. Project to the area of the specified size. At the same time, the wafer stage on which the wafer 30 is placed is moved to a predetermined position according to the shot area assignment. As a result, a predetermined pattern is projected onto a predetermined shot area, and the wafer is exposed. Then, the wafer stage is moved stepwise within the XY plane, and exposure is performed in the same manner each time, thereby exposing the entire surface of the wafer 30.
[0034]
Prior to exposure of each shot area at the position where the wafer stage is moved according to the shot area allocation, the wafer surface height detection system 27 detects the height of a plurality of locations on the wafer surface. Then, using the data, at least one of the height or inclination of the wafer stage in the Z direction, preferably both, is controlled so that the entire shot area is in focus.
[0035]
In the step-and-repeat type exposure apparatus, a maximum exposure area (exposure possible area) in which exposure can be performed within a required dimensional error range is determined. The wafer surface height detection positions are provided at a total of five points, for example, the center of the exposure possible area and the position slightly inside from the four corners. All of these five points are inside the wafer edge of the wafer 30, and when the wafer surface height data is obtained at all detection positions, focusing can be performed with a predetermined accuracy.
[0036]
In the case of a step-and-scan exposure apparatus, a second mask blind (not shown) is provided in addition to the mask blind 21 shown in FIG. The mask 22 is illuminated by the illumination light shaped like a slit by the second mask blind. A pattern obtained by reducing the pattern provided in the slit-like illumination area with the reduction ratio of the projection optical system 24 is used to reduce the illumination area on the surface of the wafer 30 positioned under the projection optical system 24 with the reduction ratio. Project to the slit exposure area.
[0037]
Then, while the second mask blind is fixed, the mask holder 23 and the wafer stage are moved synchronously in the direction intersecting the longitudinal direction of the slit-shaped exposure region (usually the direction intersecting perpendicularly), and the mask 23 and The wafer 30 is moved (scanned). As a result, the pattern in the illumination area restricted by the mask blind 21 of the mask 22 is projected onto the shot area on the wafer 30 to expose the wafer. At this time, the mask blind 21 is also moved in synchronization with the mask 22. Actually, exposure is performed by moving the wafer while the position of the slit-shaped exposure area remains fixed, but effectively, the shot is performed by moving (scanning) the slit-shaped exposure area onto the wafer. It can be considered that the exposure in the region is performed.
[0038]
Further, exposing the entire surface of the wafer 30 by stepping is the same as the step-and-repeat method.
[0039]
In the case of the step-and-scan method, a plurality of wafer surface height detection positions are provided on the moving direction side in or close to the slit-shaped exposure region, and the height of the wafer surface is detected. Using this result, the height or tilt of the stage is controlled so that the portion of the wafer surface where the slit-shaped exposure area is currently focused is in focus. The wafer surface height detection position is one or more rows in the longitudinal direction of the slit-shaped exposure area (usually the direction perpendicular to the scanning direction), in a slightly shorter range than the longitudinal dimension of the slit-shaped exposure area. Are arranged side by side and move in synchronization with scanning of the slit-shaped exposure region. When all the detection positions are inside the wafer edge of the wafer 30 while detecting the surface height in the shot area, focus adjustment can be performed with a predetermined accuracy.
[0040]
In both the step-and-repeat method and the step-and-scan method, as described above, the wafer stage height is detected in accordance with the shot area assignment in order to detect the wafer surface height of each shot area. It is also possible to perform exposure at the position where the lens is moved to adjust the focus.
[0041]
In this case, as shown in FIG. A wafer surface height detection system 27 is provided at a position where exposure is performed. It is also possible to provide a wafer surface height detection system 27 at a position different from the position where exposure is performed. In this case, prior to exposure, at the position where the surface height detection system 27 is provided, the wafer stage is moved according to the shot area assignment, the wafer surface height is detected for each shot area, and the result is stored. . When each shot area is exposed, the stored measurement result is used to perform focus adjustment.
[0042]
Next, the semiconductor device mask of the present invention will be described in detail. FIG. 4 is a diagram showing an embodiment of the semiconductor device mask 22 of the present invention.
[0043]
In the semiconductor device mask 22 shown in FIG. 4, a plurality of identical device patterns 2 for exposing a wafer are arranged. One central region (first region) 101 in which two device patterns 2 are arranged vertically and horizontally, and peripheral regions (second region 2 to ninth region) 102 to 109 disposed outside the central region. is there. The peripheral regions are two peripheral regions (third region and eighth region) 103 and 108 in which two device patterns are arranged horizontally, and two peripheral regions (fifth region, (Sixth region) 105, 106 and four peripheral regions (second region, fourth region, seventh region, ninth region) 102, 104, 107, 109 where one device pattern is arranged. Also, the peripheral regions adjacent to each other between the central region (first region) 101 and the peripheral regions (third, sixth, eighth, and fifth regions) 103, 105, 108, 105 adjacent to the central region. Between each other, a light-shielding band 100 is disposed that blocks areas by blocking light.
[0044]
The width of the light shielding band 100 is, for example, 300 μm. On the other hand, between the plurality of device patterns 2 arranged in the same region, a scribe region having a width smaller than the width of the light shielding band, for example, 100 μm or less is provided. As described above, the exposure apparatus 50 used in the exposure method of the present invention has the mask blind 21 that regulates the illumination area. The set position of the mask blind 21 has an error of 100 μm or more. The width of the light shielding band 100 is larger than the position setting error of the mask blind 21.
[0045]
These dimensions are the dimensions when projected onto the wafer 30. That is, the actual dimensions are obtained by multiplying these dimensions by the reciprocal of the reduction ratio. Hereinafter, unless otherwise noted, dimensions on the mask are also expressed by dimensions projected onto the wafer.
[0046]
As described above, the semiconductor device mask 22 is divided into a plurality of regions, the central portion has one first region 101 in which the most device patterns 2 are arranged, and the outer side has a smaller number of device patterns than the central portion. 2 to 9 regions 102 to 109 in which 2 are arranged are provided. In particular, in the example of FIG. 4, a plurality of peripheral regions 102 to 109 are arranged so as to surround the center region 101. A light shielding band 100 having a width wider than the space between the device patterns and wider than the position setting error of the mask blind 21 that restricts the illumination area of the exposure apparatus 50 is provided at the boundary between the areas. . Accordingly, since the illumination light can be completely blocked by the blind in areas other than the required area, exposure can be performed only in any area.
[0047]
Although an example of the semiconductor device mask 22 in which 16 identical device patterns 2 are arranged has been described here, the device pattern 2 is not limited to 16 pieces. The number of device patterns arranged in the central area and the peripheral area is not limited to this example.
[0048]
FIG. 5 is a view showing an embodiment of the exposure method of the present invention.
[0049]
In FIG. 5, the boundary between shot areas is represented by a solid line, and the boundary between chips is represented by a thin broken line. The same applies to FIGS. 6, 8, and 10 shown later.
[0050]
As shown in FIG. 5, on the inner side (center portion) of the wafer 30 excluding the portion adjacent to the wafer edge 31, a first shot region of the mask 22 is projected and four device patterns 2 are transferred. 201 are assigned at a fixed pitch to each of a plurality of vertical and horizontal lines. However, when the central shot area 201 is assigned, a chip chip in which only a part of the device pattern is transferred is generated. One device pattern 2 of the mask 22 is arranged so that the chip chip is not formed in the peripheral portion of the wafer. Peripheral shot regions 202a to 202c to which one of the second to ninth regions arranged or two device patterns 2 arranged vertically or horizontally are projected are allocated.
[0051]
The mask 22 and the wafer 30 shown in FIG. 4 are placed on the exposure apparatus 50 shown in FIG. 3 at the center of the wafer where the central shot area 201 is assigned, and according to the shot area assignment assigned in advance. The mask blind 21 covers the peripheral areas 2 to 9 of the mask 22, and the central area 101 is projected to perform exposure.
[0052]
In the peripheral portion of the wafer, for example, when the peripheral shot area 202a indicated by hatching in FIG. 5 is exposed, the third area of the mask 22 is projected onto the peripheral shot area 202a, that is, the first position of the mask 22 is exposed. When the mask blind 21 is extended to the position of the shading band 10 that surrounds the outside of the first to ninth regions, and the illumination region restriction by the mask blind 21 is not performed, the center of the mask 22 is within the range indicated by 210a in FIG. The wafer stage is moved so that the wafer 30 is positioned at a position where the entire area and peripheral areas (first to ninth areas) are projected. Then, the area other than the third area of the mask 22 is covered with the mask blind 21, and the third area is projected to expose the wafer. As a result, two device patterns arranged side by side arranged in the third region of the mask 22 are transferred to the peripheral shot region 202a indicated by diagonal lines.
[0053]
Similarly, for example, when the peripheral shot area 202b shown by hatching in FIG. 5 is exposed, the central area and the peripheral area of the mask 22 are projected to the area 210b when the illumination area restriction by the mask blind 21 is not performed. After moving the wafer stage to the position, the area other than the second area of the mask 22 is covered with the mask blind 21, and the second area is projected to expose the wafer. As a result, one device pattern arranged in the second area is transferred to the peripheral shot area 202b indicated by hatching. Further, when the peripheral shot area 202c is exposed, the wafer stage is moved to a position where the central area and the peripheral area of the mask 22 are projected to the range of 201c when the proof area restriction by the mask blind is not performed. The fifth region is projected, and two device patterns arranged in the fifth region and arranged vertically are transferred.
[0054]
As described above, the mask 22 is divided into the plurality of regions 101 to 109 by the light shielding band having a width equal to or larger than the position setting error of the mask blind 21 of the exposure apparatus 50, and the wafer peripheral portion where a chip chip may occur is masked. An area that does not generate a chip chip is selected from the 22 peripheral areas, and the area other than the selected area is shielded by a mask blind, and the wafer is exposed by the selected area. Thereby, generation | occurrence | production of a chip | tip is prevented and generation | occurrence | production of the particle by film peeling can be prevented.
[0055]
In the embodiment of the exposure method of the present invention described above, as shown in FIG. 4, the mask 22 in which the peripheral regions 102 to 109 are arranged outside the four sides and the four vertices of the rectangular central region 101 is provided. used. That is, the mask 22 shown in FIG. 4 has two peripheral regions 103 and 108 in which a plurality of device patterns 2 are arranged in the horizontal direction and a peripheral region in which two device patterns 2 are arranged in the vertical direction. Two peripheral regions 105, 106 are formed, and four peripheral regions 102, 104, 107, 109 where one device pattern is arranged are formed. However, it is not essential to use all of the peripheral regions 102 to 109 in order to prevent the occurrence of chipped chips. For example, a peripheral region in which a plurality of device patterns are arranged in the horizontal direction, a peripheral region in which a plurality of device patterns are arranged in the vertical direction, and a peripheral region in which one device pattern is arranged are each one central region Even if a mask arranged outside the two sides and one vertex of 101 is used, the occurrence of chipped chips can be prevented.
[0056]
However, as will be described later, in order to prevent the occurrence of defocusing, it is preferable to use a mask in which peripheral regions are arranged outside all sides and vertices of the central region 101 as shown in FIG.
[0057]
Further, in the mask 22 shown in FIG. 4, the central region 101 and all the peripheral regions 102 to 109 are arranged on the same substrate. As described above, by using a mask in which both the central region and the plurality of peripheral regions are arranged on the same substrate, one wafer 30 or a plurality of (for example, 25) wafers including the wafer 30 can be used. The exposure time can be shortened by eliminating the need to replace the mask in the course of one lot of exposure processing.
[0058]
However, the exposure method of the present invention is performed by exchanging the central area mask in which the central area is arranged and the peripheral area mask in which all or a part of the peripheral area is respectively arranged as necessary. You can also.
[0059]
In this case, for example, if the central area mask is provided with a central area in which four device patterns 2 are arranged in the vertical and horizontal directions, a total of 16 device areas, the central area of the wafer 30 is exposed at each step. Sixteen device patterns can be transferred. As a result, the number of steps and the exposure time required to expose one wafer can be reduced.
[0060]
In addition to such a central area mask, a mask as shown in FIG. 4 can be used as a peripheral area mask. The center region 101 of the mask 22 in FIG. 4 is used as an intermediate region in which a plurality of device patterns are arranged vertically and horizontally, although the number is smaller than the center region mask in which 16 device patterns are arranged. be able to. That is, the outermost peripheral portion of the peripheral portion excluding the central portion exposed using the central region mask is exposed using any one of the second to ninth peripheral regions, and the outermost peripheral portion is exposed. An intermediate portion between the portion and the central portion can be exposed using the intermediate region.
[0061]
In this case, when focusing attention on the exposure processing of the outermost peripheral portion and the intermediate portion, as in the embodiment described with reference to FIG. 5, an appropriate one in the central region and the peripheral region arranged on one mask. This corresponds to an embodiment in which the central portion and the peripheral portion of the wafer are exposed using the above. In other words, the intermediate portion and the outermost peripheral portion in this case correspond to the central portion and the peripheral portion in the embodiment described with reference to FIG.
[0062]
FIG. 6 is a schematic block diagram showing an example of a processed wafer exposed by the embodiment of the exposure method of the present invention.
[0063]
The processed wafer 40 shown in FIG. 6 has a circular shape, and a wafer edge 41 is formed on the inner side by several mm from the peripheral edge.
[0064]
In the central portion of the processed wafer 40, 173 central shot regions 201 constituting four chips, each of which is exposed by projecting the first region of the mask 22, are formed.
[0065]
On the other hand, in the peripheral part of the wafer, five peripheral shot areas 202 exposed by projecting the second area of the mask 22 so as not to cause chipped chips, five peripheral shot areas 203 exposed by the third area, Five peripheral shot regions 204 exposed in the fourth region, two peripheral shot regions 205 exposed in the fifth region, two peripheral shot regions 206 exposed in the sixth region, and five exposed in the seventh region One peripheral shot region 207, four peripheral shot regions 208 exposed to the eighth region, and five peripheral shot regions 209 exposed to the ninth region are formed.
[0066]
As described above, the processed wafer exposed by the exposure method of the present embodiment does not generate chipped chips and does not generate particles due to film peeling.
[0067]
However, even when no chip is generated, defocusing cannot always be prevented. In order to completely prevent the occurrence of defocus, it is necessary to appropriately allocate shot areas in consideration of the type of exposure apparatus to be used and the arrangement of the wafer surface height detection position. For this purpose, it may be necessary to optimize the arrangement of the mask to be used.
[0068]
First, the case of the step and repeat method will be described.
[0069]
FIG. 7 schematically shows the relationship between the wafer surface height detection positions 5a to 5e placed at the center and at the four corners in the exposure possible area and the position at which the mask 22 is projected in the step-and-repeat type exposure apparatus. It was. In the case shown in FIG. 7B, the wafer surface is provided at the center and the four corners of the range in which the central region 101 and the peripheral regions 102 to 109 of the mask 22 are projected when the illumination region restriction by the mask blind 21 is not performed. Height detection positions 5a to 5e are located. Therefore, if the range 210 where the central area and the entire peripheral area are projected is within the wafer edge, all the wafer surface height detection positions are located inside the wafer edge 31, and all wafer surface height detection positions are within the wafer edge. The wafer surface height can be measured. Then, using the measurement result, the height and inclination of the wafer stage can be adjusted to perform accurate focusing.
[0070]
When shot area allocation is performed as shown in FIG. 5, this condition is satisfied in a portion near the center of the wafer 30, and defocusing does not occur. However, in the portion close to the wafer edge 31, even in the shot assigned to expose the central region of the mask 22 in FIG. 5, some of the wafer surface height detection positions are outside the wafer edge 31 and defocused. May occur.
[0071]
For example, FIG. 8A shows an example where defocusing occurs in this way. In FIG. 8A, when the central region 101 of the mask 22 is exposed at a position P1 indicated by oblique lines, a range 210 in which the central region and the entire peripheral region are projected when the illumination region is not restricted by the mask blind 21 is shown. Indicated by a thick broken line. As shown in FIG. 8A, a part of a range 210 in which the entire central region and the entire peripheral region are projected protrudes outside the wafer edge 31, and the first to fifth detections of the wafer surface height placed at the four corners. Of the positions 5 a to 5 e, the first detection position 5 a goes outside the wafer edge 31. Therefore, defocus may occur in this shot area.
[0072]
On the other hand, FIG. 8B shows an example in which the shot area allocation is changed so that defocus does not occur.
[0073]
In FIG. 8 (a), the position P1 indicated by hatching where the shot area allocation is performed so as to expose the central area 101 of the mask is changed to an allocation so that the exposure is divided into three in FIG. 8 (b). Made.
[0074]
In other words, the position P2 indicated by the left-upward oblique line in the lower half is exposed in the third region 103 of the mask 22. In this case, a range 210 in which the entire central region and the peripheral region are projected is indicated by a thick broken line. That is, in order to perform exposure in the third region 103 at the position P2 indicated by the left-upward oblique line, the wafer stage is set such that the range 210 where the central region and the entire peripheral region of the mask 22 are projected is the position indicated by the thick broken line. Move. As can be seen from the figure, in this case, a range 210 in which the central region and the entire peripheral region are projected falls within the wafer edge 31. Therefore, all of the wafer surface height detection positions 5a to 5e are arranged inside the wafer edge 31, and defocusing can be prevented. In addition, the upper half of the position P3 indicated by the upper right diagonal line is further divided into two parts on the left and right sides, and by assigning each to be exposed in the second region 102 of the mask 22, defocusing is also performed in this part. Can be prevented.
[0075]
Further, in FIG. 8B, the allocation is changed so that defocus does not occur in other shot areas. For example, the position P <b> 4 indicated by the oblique line of the cross is changed so that the exposure is performed in the fifth region 105 of the mask 22.
[0076]
Depending on the number of wafer surface height detection positions of the exposure apparatus and their respective roles, it is not always necessary to perform shot area allocation so that all of them are located within the wafer edge 31. For example, the number of wafer surface height detection positions necessary for guaranteeing a predetermined focus accuracy is provided relatively inside the exposure-possible area, and an additional wafer surface height detection position is further provided outside the position. In the case where measurement data is obtained there, it is also assumed that an exposure apparatus having a focus control function that further increases accuracy is used.
[0077]
In this case, since the wafer surface position detection position necessary for assuring a predetermined accuracy is only the one provided on the inner side, all of the necessary wafer surface height detection positions are located inside the wafer edge 31. The shot area may be allocated so as to be located at The same applies to the case of using a step-and-scan type exposure apparatus.
[0078]
In the above description, as shown in FIG. 7B, it is assumed that the wafer surface height detection positions 5a to 5e are all within the range 210 where the central region and the peripheral region of the mask 22 are projected. did. However, depending on the dimensions of the device pattern 2 and the arrangement of the wafer surface height detection position, as shown in FIG. 7A, the width of the light shielding bands 100a to 100d of the mask 22 is set to the mask blind 21 of the exposure apparatus. Even when the size is sufficient to absorb the set position error, the wafer surface height detection positions 5a, 5b, 5d, and 5e at the four corners of the exposure possible area are projected on the entire central area and the peripheral area. It may be outside the range 210. In such a case, in the portion close to the wafer edge 31, it may not be possible to put all of the wafer surface height detection positions 5a to 5e into the wafer edge 31 even if exposure is performed using any peripheral region.
[0079]
As a countermeasure, as shown in FIG. 7B, the width of the light shielding bands 100a to 100d is widened, and all the wafer surface height detection positions 5a to 5e are projected in the central area and the entire peripheral area. It is possible to optimize the arrangement of the peripheral areas in the mask 22 so as to be within 210.
[0080]
Next, the case of the step and scan method will be described.
[0081]
In FIG. 9, the slit-shaped exposure region 15 and the wafer surface height detection positions 5a to 5e, and the central region and the peripheral region (second to ninth regions) of the mask 22 are projected in the step-and-scan type exposure apparatus. The relationship with the position is shown schematically.
[0082]
In the figure, a state where the illumination area is not restricted by the mask blind 21 is shown. In this example, the detection points 5 are arranged in a line in the direction intersecting (orthogonal to) the scanning direction A in which the slit exposure region 15 moves, that is, in the longitudinal direction of the slit exposure region 15. It moves in the scanning direction A in synchronization with the movement. Then, the height of the surface of the wafer at each detection point 5 is measured at a predetermined timing. For example, the wafer surface height detection position 5 is provided at the tip of the slit-shaped exposure region 15 on the moving direction A side or a slightly preceding position. Then, the measurement of the wafer surface height at each detection position is repeatedly performed within the period during which the slit-shaped exposure area 15 is scanned, and the height and inclination of the XYZ stage apparatus 25 are adjusted based on the result. Do it continuously. As a result, the focused state is maintained with respect to the part of the surface of the wafer 30 that is in the slit-shaped exposure area and that is actually being exposed.
[0083]
Actually, the slit-shaped exposure region 15 and the wafer surface height detection position 5 are fixed, and the wafer 30 and the mask 22 move in synchronization. For convenience, the slit-shaped exposure region 15 and the wafer surface height are moved. The description will be made assuming that the detection position 5 moves.
[0084]
Here, in order to perform accurate focus adjustment, it is necessary that all of the wafer surface height detection positions 5a to 5e are inside the wafer edge 31 of the wafer 30 and the height of the wafer surface can be accurately measured. However, unlike the case of the step-and-repeat method, the center of the mask 22 is formed over the entire range in which the wafer surface height detection positions 5a to 5e move, that is, when the illumination area restriction by the mask blind 21 is not performed. It is not essential that all the detection positions 5 a to 5 e are always inside the wafer edge 31 in the entire region onto which the region and the peripheral region are projected.
[0085]
For example, in the example shown in FIG. 9B, the exposure is performed on the shot area that projects either the central area of the mask 22 or the fifth and sixth peripheral areas arranged on the left and right of the central area. think of. In this case, in order to perform accurate focus adjustment, while the wafer surface height detection position is moving within the center area to be exposed or the area in which the fifth and sixth peripheral areas are projected, there are five points. All of the detection positions must be inside the wafer edge 31. However, for example, the wafer surface height detection position 5 is within the range in which the second, third, and fourth peripheral regions arranged above the exposed region are projected (when the illumination region is not restricted by the mask blind 21). There is no problem even if a part or all of the detection positions are outside the wafer edge 31 during the movement. That is, even if an abnormal measurement result is obtained at a detection position located outside the wafer edge 31 within a period in which the detection position is outside the area to be exposed, within a period in which the detection position is in the area to be exposed. If the focus adjustment is performed using only the measurement results obtained in the above, it is possible to prevent the occurrence of defocusing.
[0086]
FIG. 10A shows an example in which defocus occurs when exposure is performed by scanning the slit-shaped exposure region in the vertical direction by the step-and-scan method in the shot region allocation described with reference to FIG. In FIG. 10A, when the central region 101 of the mask 22 is exposed at the position P1 indicated by the oblique lines in the drawing, the central region 101 and the left and right sides thereof are arranged when the illumination region is not restricted by the mask blind 21. A range 220 in which the fifth and sixth peripheral regions 105 and 106 are projected is indicated by a thick broken line. As shown in FIG. 10A, the leftmost wafer surface height detection position 5 a protrudes outside the wafer edge 31 when measuring the wafer surface height in the region surrounded by the broken line. Therefore, defocus may occur in this shot area.
[0087]
On the other hand, an example in which the shot area allocation is changed so that defocusing does not occur is shown in FIG. In FIG. 10 (a), the position P1 indicated by hatching where the shot area is assigned so as to expose the central area 101 of the mask is divided into two parts on the left and right in FIG. 10 (b). A change has been made.
[0088]
First, shot area allocation is performed so that exposure is performed in the fifth area 105 of the mask 22 at the position P4 indicated by the cross hatching in the left half. In order to expose the position P4 in the fifth area, the wafer stage is moved so that the area 230 on which the central area 101, the fifth area 105, and the sixth area 106 of the mask 22 are projected is a position indicated by a thick broken line. . As can be seen from the figure, in this case, all of the wafer surface height detection positions 5a to 5e are accommodated in the wafer edge 31, and the occurrence of defocusing can be prevented.
[0089]
Then, the position P5 indicated by the oblique line of the cross in the right half is also assigned as another shot area for projecting the fifth area 105. Further, in FIG. 10B, the shot area allocation is changed so that defocus does not occur for other shot areas. That is, a shot area for projecting the fifth area 105 is assigned to the position indicated by the cross hatched line, and a shot area for projecting the second area 102 is assigned to the position P3 indicated by the oblique line rising to the right.
[0090]
As described above, in both the step-and-repeat method and the step-and-scan method, shot area allocation as shown in FIGS. 8B and 10B is performed in consideration of the arrangement of the wafer surface height detection position. Also, it is possible to prevent the occurrence of defocus even in the peripheral shot area. That is, by performing shot area allocation as shown in FIGS. 8B and 10B, even in the peripheral shot areas, the wafer edge is detected at all the wafer surface height detection positions necessary to guarantee high focus accuracy. The height and tilt of the stage can be adjusted by detecting the height of the inner surface and using the detection result.
[0091]
However, even when shot area allocation as shown in FIG. 5 is performed, the amount of occurrence of defocus can be reduced. That is, at the stage where the shot area is assigned, it is possible to determine which of the plurality of wafer surface height detection positions is outside the wafer edge 31, and therefore, at other positions excluding measurement data at the detection positions. It is possible to control the stage using only the measurement data. Since there are few data points that can be used, the focus accuracy is reduced as compared with the case where data of all detection points can be used. In some cases, only one of the height and tilt of the stage can be controlled. However, it is possible to prevent a large defocus from occurring.
[0092]
In the case of the step-and-scan method, it may be preferable to optimize the mask as in the case of the step-and-repeat method. For example, as shown in FIG. 9A, even when the width of the light shielding bands 100a to 100d of the mask 22 is set to a dimension sufficient to absorb the set position error of the mask blind 21 of the exposure apparatus, Wafer surface height detection positions 5a and 5e placed at both ends are further outward in the longitudinal direction (lateral direction in the drawing) of the slit-shaped exposure region 15 than the range in which the central region and the peripheral region of the mask 22 are projected. There is a case. In such a case, in a portion close to the wafer edge 31, even if shot area allocation is performed so that exposure is performed using any peripheral area, it cannot be included in all the wafer edges 31 at the wafer surface height detection position. Sometimes.
[0093]
As a countermeasure against this, as shown in FIG. 9B, the widths of the light shielding bands 100a and 100b that define the longitudinal direction of the slit-shaped exposure area 15 (the vertical light shielding bands in the figure) are increased. It is possible to optimize the mask 22 so that the wafer surface height detection position is within the range in which the central region and the peripheral region are projected.
[0094]
In FIG. 9B, the wafer surface height detection position 5 is drawn so as to be located further above the upper end of the wafer 22. However, this detection position moves downward in the figure as the slit-shaped exposure region 15 moves, and when it reaches an appropriate position, the wafer surface height at a necessary position is measured. That is, in the case of the step-and-scan method, even in the case of optimizing the light shielding band width in the longitudinal direction (left and right direction in the figure) of the slit-shaped exposure region 15, light shielding in the scanning direction (up and down direction in the figure). There is no need to optimize the bandwidth.
[0095]
【The invention's effect】
As described above, according to the mask for a semiconductor device of the present invention, the mask is divided into a plurality of regions that can be individually projected by the light shielding band. Further, according to the exposure method of the present invention, the exposure is performed by assigning shot areas for projecting appropriate areas of the mask to the central part and the peripheral part of the wafer, respectively. For this reason, chipped chips that are likely to occur in the periphery of the wafer can be prevented, and the yield of semiconductor chips can be improved. In addition, it is possible to prevent the occurrence of defocus that tends to occur in the peripheral portion of the wafer and further improve the yield of the semiconductor chips.
[Brief description of the drawings]
FIG. 1 is a view showing a mask for a semiconductor device generally used conventionally.
FIG. 2 is a diagram illustrating an example of a device formed by exposing a wafer.
FIG. 3 is a schematic block diagram showing a main part of an exposure apparatus used in an embodiment of the exposure method of the present invention.
FIG. 4 is a diagram showing an embodiment of a semiconductor device mask of the present invention.
FIG. 5 is a view showing an embodiment of the exposure method of the present invention.
FIG. 6 is a schematic configuration diagram showing an embodiment of a processed wafer according to the present invention.
FIG. 7 is a diagram showing a relationship between a position at which the semiconductor device mask of the present embodiment is projected and a wafer surface height detection position;
FIG. 8 is a diagram showing shot area allocation for preventing the occurrence of defocus when exposure is performed by the step-and-repeat method.
FIG. 9 is a diagram showing a relationship between a position at which the semiconductor device mask of the present embodiment is projected, a slit exposure region, and a wafer surface height detection position;
FIG. 10 is a diagram showing shot area allocation that prevents the occurrence of defocusing when exposure is performed in a step-and-scan manner.
[Explanation of symbols]
1,22 Mask for semiconductor devices
2 Device pattern
5 Wafer surface height detection position
5a First detection position
5b Second detection position
5c Third detection position
5d 4th detection position
5e 5th detection position
10, 30, 40 wafers
11, 31, 41 Wafer edge
11a Effective area
11b Invalid area
12 shot area
12a Shot area not over the invalid area
12b Shot region formed in wafer peripheral portion
13 chips
15 Slit exposure area
20 Lighting system
21 Mask Blind
22 Mask
22a frame
23 Mask holder
24 Projection optical system
25 XYZ stage device
26 Holder
27 Wafer surface height detection system
27a Light emitting part
27b Light receiving sensor
50 exposure equipment
100 shading zone
101 1st area
102 2nd area
103 3rd area
104 4th area
105 5th area
106 6th area
107 7th area
108 8th area
109 9th region
201 Central shot area
202 Peripheral shot area where second area is exposed
202a, 202b, 202c Shot areas indicated by diagonal lines
203 Peripheral shot area where third area is exposed
204 A peripheral shot area in which the fourth area is exposed
205 Peripheral shot area where fifth area is exposed
206 Peripheral shot area where the sixth area is exposed
207 Peripheral shot area where the seventh area is exposed
208 Peripheral shot area where the eighth area is exposed
209 Peripheral shot area in which the ninth area is exposed
210 Area in which the central area and the entire peripheral area are projected
210a Position where the third region is projected and exposed
210b The position where the second region is projected and exposed
210c Position where the fifth region is projected and exposed
220 Area in which the central area, the fifth area, and the sixth area are projected

Claims (1)

A mask for a semiconductor device having a plurality of identical device patterns, and exposing the wafer by projecting the device pattern onto a wafer placed on a wafer stage of a projection exposure apparatus,
One central region in which two device patterns are arranged vertically and horizontally;
Two first peripheral regions disposed outside two opposite sides of the central region, and two device patterns disposed laterally;
Two second peripheral regions arranged outside two sides excluding the two opposite sides of the central region, wherein the two device patterns are arranged vertically;
Four third peripheral regions arranged outside the two opposite sides of the central region and outside the two sides excluding the two opposite sides of the central region, wherein one device pattern is arranged ,
It is arranged between the central region and the first, second and third peripheral regions and between the adjacent first, second and third peripheral regions, and blocks the irradiated light. fractionated regions each other by a mask for a semiconductor device characterized by having a light-shielding band having a width greater than the width of the scribe area between the device pattern of the central region.

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