JP5204127B2 - Scan exposure apparatus and method for manufacturing semiconductor device - Google Patents

Description

  The present invention is suitable for, for example, EUV (Extreme Ultra Violet) lithography and the like, and relates to a scan exposure apparatus and a semiconductor device manufacturing method for performing scan exposure using a mask.

  In the process of manufacturing a semiconductor device such as a semiconductor integrated circuit, a lithography technique is used as a method for transferring a fine pattern onto a substrate. In this lithography technique, a projection exposure apparatus is mainly used, and pattern transfer is performed by irradiating the resist on the substrate with exposure light transmitted through a photomask mounted on the projection exposure apparatus.

  In recent years, higher integration of devices and higher device operating speeds have been demanded, and pattern miniaturization has been promoted to meet these demands. In order to meet this demand for miniaturization, efforts have been made to improve the resolution of projected images by shortening the exposure wavelength. Recently, EUV light having a wavelength of 13.5 nm, which is one digit or more shorter than conventional ultraviolet rays, has been recently used. The exposure method used is also being studied.

  From the viewpoint of the aberration and angle of view of the projection optical system, as a state-of-the-art exposure method including the EUV exposure method, a scanner method that performs exposure by scanning an arc-shaped exposure region instead of the stepper method is the mainstream. It is used as.

JP 2005-86148 A

  Although the resolution of the projected image is improved with the shortening of the exposure light wavelength, the problem of flare is emerging. This flare is a major problem in the EUV exposure method in which a reflective mask made of a multilayer film and a reflective projection optical system made of a multilayer film are indispensable, helping to shorten the exposure wavelength.

  Flares are classified into several types, and what is particularly a major problem centering on EUV lithography is what is called local flare. The local flare has a slight roughness on the surface of the reflecting mirror, so that the exposure light is irregularly reflected on the reflecting surface, which causes stray light in a direction other than the regular reflection direction.

  Patent Document 1 proposes an extreme ultraviolet optical system for the purpose of preventing image quality deterioration and resolution reduction due to stray light by incorporating a large number of stray light apertures inside the reflection projection optical system. Yes.

  FIG. 6 is a plan view showing a state in which exposure light is irradiated on the reflective mask. In the scanner device using the reflection mask, the exposure area 11 of one shot has an arc shape divided by the exposure boundary 10. Focusing on the exposure point 12a in the exposure region 11, when flare due to irregular reflection occurs at the exposure point 12a, a substantially circular light spread 13a occurs around the exposure point 12a. When irregular reflection occurs at other exposure points 12b, 12c, etc., similarly, substantially circular light spreads 13b, 13c occur around the exposure points 12b, 12c. Such light spread can be defined as the angular distribution of scattered light.

  FIG. 7 is a graph showing how light spreads on the wafer due to flare. The horizontal axis indicates the position in the in-plane direction with the exposure point as the origin 0, and the vertical axis indicates the amount of light. From this graph, it can be seen that the peak of the light amount is located at the exposure point, and the light amount decreases as the distance from the exposure point increases.

  Although depending on the roughness characteristic of the multilayer film of the mask and the roughness characteristic of the substrate, the light quantity distribution is a characteristic of the axis target in a first order approximation. As described above, this irregular reflection characteristic is caused by the roughness of the reflecting surface. In particular, in EUV lithography having a short exposure wavelength of 13.5 nm and a short nanometer level, a roughness with a spatial period of 0.1 nm exists. However, the scattered light is taken into the optical system and causes a resolution failure.

  Due to the flare, a light flare 15 is also generated outside the arcuate exposure region 11 and the exposure boundary 10 as shown in FIG. Due to this flare, exposure coverage occurs in the chip area adjacent to the chip area to be exposed, and pattern dimension abnormality and resolution reduction occur in the adjacent area.

  In the case of EUV lithography, there is a margin in resolution, so the problem of whether or not to resolve is relatively small, but pattern dimension abnormality is a big problem.

  In order to solve this problem, conventionally, correction has been performed by applying a dimensional bias to the mask pattern where the exposure coverage occurs. Unlike electron beam lithography (EB lithography) that can correct the beam diameter and dose for each pattern, it is dimensional correction on the mask pattern. Can not.

  FIG. 9 is a plan view showing an exposure shot map on the wafer. The effective chip area 20 located inside the wafer is affected by a shot to the adjacent effective chip area around the periphery, and a uniform exposure environment is maintained.

  On the other hand, in order to maintain the same exposure environment as the inside for the effective chip area located in the periphery of the wafer, the ineffective chip area that is located outside the effective chip shot area 22 and intersects the wafer outer periphery 21 or a further outside area. It is necessary to irradiate dummy shots 24 and 25.

  Here, the dummy shot 24 along the exposure scan direction 23 needs to be a full chip size dummy shot. On the other hand, since the dummy shot 25 in the vertical direction scans the arc-shaped exposure region, it does not have to be a full chip size but a shot size up to a size at which exposure covering occurs. This size depends on the length of the arcuate exposure area and the extent of the cover area, but in many cases is about 1/4 of the full chip size.

  Such dummy shots cause a problem that the number of shots per wafer increases and the exposure throughput decreases. Usually, the exposure field size of a full field scanner is around 26 mm × 33 mm on the wafer. At this time, when the chip size is 24.9 mm × 32.9 mm and the shot pitch is 25 mm × 33 mm, the number of effective acquisition chips is 74 chips, and the number of invalid chips of the dummy shot 24 of the full chip size parallel to the scan direction is 18, vertical. The number of invalid chips in the dummy shot 25 of the partial chip size in any direction is 24.

  In terms of exposure time, T is the time required for exposure of one full chip size, 74 T is the exposure time required to acquire an effective chip, 18 T is the exposure time required for dummy shot 24, and 25 is required for dummy shot 25. The exposure time is calculated as 24/4 = 6T. Therefore, the total exposure time of the wafer is 98T, and 32% (= (98−74) / 74) of the effective exposure time is redundant due to the dummy shot for maintaining the exposure environment.

  In particular, in EUV lithography, since the amount of light from the EUV light source is low, the exposure time tends to be long and the throughput tends to be low. However, the dummy shot as described above promotes a decrease in the throughput.

  An object of the present invention is to provide a scan exposure apparatus and a semiconductor device manufacturing method capable of reducing dummy shots for maintaining an exposure environment, shortening exposure time, and improving throughput.

According to one embodiment of the present invention, a light shielding member for defining an exposure width along a direction perpendicular to a scanning direction when performing exposure on a wafer by projecting exposure light from an exposure mask. Are arranged close to the wafer surface to block flare toward the chip area adjacent to the chip area to be exposed. Scan exposure on a wafer is performed using an exposure region that is elongated in a direction perpendicular to the scan direction. The light shielding member limits flare generated inside the projection optical system by setting the exposure width to be smaller than the length of the exposure region.

  At this time, the exposure width defined by the light shielding member is preferably changed in accordance with the size of the chip area to be exposed and / or the interval between the chip area to be exposed and the adjacent chip area.

  The gap between the light shielding member and the wafer surface is preferably set to 500 μm or less.

  According to this embodiment, the light shielding member is disposed close to the wafer surface to block flare toward the chip area adjacent to the chip area to be exposed, thereby reducing dummy shots for maintaining the exposure environment. can do. As a result, the exposure time can be shortened and the throughput can be improved.

It is a block diagram which shows an example of the scanning exposure apparatus which concerns on this invention. It is a top view which shows the mode of the opening part vicinity of a housing. It is explanatory drawing which shows a mode that the exposure width of a X direction is restrict | limited with the light-shielding blade. It is a top view which shows the exposure shot map in the wafer at the time of using the scanning exposure apparatus shown in FIG. 5A to 5D are plan views showing various examples of chip shot maps having various chip intervals. It is a top view which shows a mode that exposure light is irradiated to the reflective mask. It is a graph which shows the mode of the expansion of the light on the wafer by a flare. It is a top view which shows the mode of the flare of the light which appears around the exposure area | region. It is a top view which shows the exposure shot map in a wafer.

Explanation of symbols

100 light source, 101 exposure light, 102 reflective optical system, 103 exposure mask,
103a mask stage, 104 housing, 105 reflective projection optical system,
106 wafer, 106a wafer stage, 110 shading blade,
111 Drive mechanism, 112 opening.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an example of a scanning exposure apparatus according to the present invention. The scanning exposure apparatus includes a light source 100 that supplies exposure light 101, a reflection optical system 102, a mask stage 103a for mounting an exposure mask 103, a reflection projection optical system 105, a housing 104 that houses the optical system, A wafer stage 106a for mounting the wafer 106, a pair of light shielding blades 110, a drive mechanism 111 for variably setting the exposure width of the light shielding blades 110, and the like. Hereinafter, for easy understanding, the exposure mask 103 and the wafer 106 are set parallel to the XY plane, and the direction perpendicular to the XY plane is defined as the Z direction.

  The light source 100 supplies, for example, EUV light having a wavelength range of 10 nm to 15 nm, in particular, a wavelength of 13.5 nm as the exposure light 101. In this embodiment, the case where EUV exposure light is used is exemplified, but the present invention uses other wavelengths, for example, wavelength regions such as soft X-rays, DUV (deep ultraviolet), ultraviolet, and visible light. It is also applicable to cases.

  The optical path from the light source 100 to the wafer 106 is maintained in an appropriate atmosphere according to the wavelength used so that the absorption of exposure light is as low as possible. In the case of EUV light, it is generally maintained in a vacuum. Yes. In particular, the inside of the housing 104 that accommodates the reflective optical system 102, the exposure mask 103, and the reflective projection optical system 105 is evacuated so as to have a particularly high degree of vacuum compared to the surroundings, thereby contaminating the optical system. Protect from.

  The mask stage 103a is supported so as to be displaceable in the XY plane, and is connected to a stage drive mechanism (not shown). The wafer stage 106a is also supported so as to be displaceable in the XY plane, and is connected to another stage driving mechanism (not shown). In particular, when performing scanning exposure, the mask stage 103a and the wafer stage 106a move the exposure mask 103 and the wafer 106 at a constant speed in the Y direction in synchronization with each other.

  The scanning speed Vm of the mask stage 103a and the scanning speed Vw of the wafer stage 106a are determined according to the imaging magnification M of the reflection projection optical system 105. For example, when M = 1/4, Vw is four times Vm. In general, Vm = M × Vw.

  In the case of EUV light, the reflective optical system 102 is configured by a multilayer mirror in which a multilayer film in which, for example, Mo / Si is alternately laminated is coated on the surface of a substrate such as low thermal expansion glass. The reflection projection optical system 105 is also composed of a plurality of multilayer mirrors having such a configuration. By forming the reflective surface of the multilayer mirror as a concave surface, a positive optical power can be applied, and conversely, if it is formed as a convex surface, a negative optical power can be applied. The magnitude of the optical power can be determined according to the radius of curvature of the reflecting surface.

  The exposure mask 103 includes a mask substrate, a multilayer reflective film formed on the entire surface of the mask, an absorber film having an exposure pattern shape, and the like. The mask base is formed of quartz glass, low thermal expansion glass LTEM, or the like. The multilayer reflective film is formed of a MoSi multilayer film having a sufficient reflectance with respect to EUV light. The absorber film is formed of a material that can absorb or block EUV light, such as Ta or TaBN.

  Next, the exposure operation will be described. The exposure light 101 supplied from the light source 100 is reflected by the reflection optical system 102 and enters the exposure mask 103 obliquely. The exposure light reflected from the exposure mask 103 is spatially modulated in accordance with the pattern shape of the absorber film, and subsequently imaged on the wafer 106 via the reflective projection optical system 105. In this state, the exposure pattern of the exposure mask 103 can be projected onto the wafer 106 by performing synchronous scanning of the mask stage 103a and the wafer stage 106a.

  In the present embodiment, an opening 112 through which light emitted from the reflective projection optical system 105 passes is provided on the lower surface of the housing 104. Further, a pair of light shielding blades 110 are arranged between the opening 112 and the wafer 106 so as to be close to the wafer surface. The gap between the blade tips defines the exposure width along the direction (X direction) perpendicular to the scanning direction (Y direction). Each light shielding blade 110 is connected to a pair of blade driving devices 111 for variably setting the exposure width of the wafer 106.

  FIG. 2 is a plan view showing a state near the opening 112 of the housing 104. As described with reference to FIG. 6, the exposure area 11 for one shot has a long and narrow circular arc shape symmetrical with respect to the Y direction, and an opening 112 is formed at a location corresponding to the exposure area 11. However, this is an opening corresponding to a full shot, and in actual chip exposure, the exposure area is limited according to the size of the chip to be formed. This limitation can be implemented by forming a light shield (absorber) on the exposure mask 103 or forming a masking blade near the exposure mask 103.

  In the present embodiment, a pair of light shielding blades 110 are arranged so as to further restrict both sides of the exposure region 11. The position and interval of each blade tip can be variably adjusted by the blade driving device 111.

  With this configuration, as shown in FIG. 3, the exposure width in the X direction of the exposure light 101 is limited by the light shielding blade 110, so that the light passing through the vicinity of the edge portion of the opening 112 toward the wafer 106, that is, flare It becomes possible to block the stray light caused by the light blocking blade 110.

  At this time, the gap s between the light shielding blade 110 and the wafer surface is preferably set to 500 μm or less, so that the light spreading distance d at the edge portion is set to 50 μm or less. As a result, the spread of light is confined to the gap between the acquisition chips and the chip scribe region, so that it is possible to prevent the adjacent chips from being exposed to light.

  FIG. 4 is a plan view showing an exposure shot map on the wafer when the scan exposure apparatus shown in FIG. 1 is used. In the present embodiment, in particular, by limiting the spread of flare light in the X direction, dummy shots in the X direction of the full chip size can be omitted with respect to the dummy shots for maintaining the exposure environment. Only the dummy shot 25 in the narrow portion of the exposure area in the direction is required.

  Here, similarly to the description in FIG. 9, when the exposure throughput is estimated, when the chip size is 24.9 mm × 32.9 mm and the shot pitch is 25 mm × 33 mm, the number of effective acquisition chips is 74 chips in the scan direction. The number of invalid chips in the parallel full chip size dummy shot is zero, and the number of invalid chips in the partial shot size dummy shot 25 in the vertical direction is 20.

  In terms of exposure time, the time required for exposure of one full chip size is T, and the exposure time required to acquire an effective chip is calculated as 74T, and the exposure time required for the dummy shot 25 is calculated as 20/4 = 5T. The Therefore, the total exposure time of the wafer is 79T, and it can be seen that the exposure time can be reduced by 20% compared to the conventional exposure time 98T described in FIG.

  In particular, in EUV lithography, since the amount of light of the EUV light source is low, the exposure time tends to be long and the throughput tends to be low. However, by arranging the flare light shielding blade 110 as described above, the exposure throughput is greatly increased. Can improve.

  Here, the movable shading blade 110 is arranged just above the wafer only in the X direction perpendicular to the scanning direction. On the other hand, there is an opening of a certain width directly above the wafer in the Y direction which is the scanning direction. Just do it.

  This is because in EUV lithography, it is necessary to install a reflective optical system near the wafer, and there is a gap for installing the two movable light-shielding blades 110 in both the X and Y directions including the driving device 111. That is, there is no room for securing the clearance. Even if a dummy shot is required in the Y direction, it is not necessary to use a full chip size dummy shot, so that the present method in which the flare light in the X direction is limited has a higher effect of improving the throughput.

  As described above, in the present embodiment, the dummy shot for maintaining the exposure environment can be omitted in the X-direction dummy shot of the full chip size, and only a partial dummy shot with a narrow exposure area in the Y-direction in the scanning direction can be used. become. As a result, the exposure time can be reduced by 20%, and the exposure throughput can be greatly improved.

Embodiment 2. FIG.
In the present embodiment, a case where chip exposure with various shot intervals is performed using the above-described scan exposure apparatus will be described.

  5A to 5D are plan views showing various examples of chip shot maps having various chip intervals. With respect to the X direction perpendicular to the scanning direction (Y direction), exposure is performed by changing the shot gap from s1 to s4. The shot interval can be arbitrarily changed. Here, a case where s1 = 50 μm, s2 = 100 μm, s3 = 150 μm, and s4 = 200 μm is illustrated. The exposure masks used are the same.

  Further, by changing the exposure width defined by the light shielding blade 110 in accordance with such a shot interval (chip interval), flare light toward the chip region adjacent in the X direction is limited.

  As a result of the exposure experiment, even if the exposure is performed by changing the shot interval from s1 to s4, adjacent chips 30a and 31a in the X direction shown in FIG. 5A, adjacent chips 30b and 31b in the X direction shown in FIG. 5B, and shown in FIG. In the adjacent chips 30c, 31c in the X direction and the adjacent chips 30d, 31d in the X direction shown in FIG. 5D, there is no change in the in-plane dimension distribution, particularly the dimension distribution near the outer periphery of the chip area, and a dimensionally stable chip is obtained. It was. On the other hand, in the conventional method in which the light shielding blade does not exist immediately above the wafer, a dimensional distribution occurs between adjacent chips, and thus it is necessary to fix the chip interval within one wafer.

  Here, the case where the size of the chip area to be exposed is constant has been described, but when the size of the chip area changes, the exposure width defined by the light shielding blade 110 according to the size and / or the chip interval. Is preferably changed.

  Thus, in this embodiment, the degree of freedom in designing the chip shot map is increased by employing the variable light shielding blade. For example, in the case of multi-chip exposure in which a plurality of different chips are printed on a single wafer using a plurality of masks, the flexibility is increased and the facility utilization efficiency can be improved. In addition, there is an effect in improving the yield of the wafer, for example, when a part of the wafer has a defect and exposure is performed while avoiding the location in the inter-chip area.

  The present invention is extremely useful industrially in that a semiconductor device including a fine and highly accurate pattern can be manufactured with high production efficiency.

Claims (7)

A mask stage for mounting an exposure mask;
A wafer stage for mounting the wafer;
A projection optical system for projecting exposure light from the exposure mask onto the wafer,
A scan exposure apparatus that performs scan exposure on a wafer by moving a mask stage and a wafer stage in synchronization with each other,
A light shielding member provided in the vicinity of the wafer surface and for defining an exposure width along a direction perpendicular to the scanning direction;
A drive mechanism for variably setting the exposure width of the light shielding member ,
Scan exposure on a wafer is performed using an exposure area that is elongated in a direction perpendicular to the scan direction,
The scanning light exposure apparatus , wherein the light shielding member limits flare generated inside the projection optical system by setting the exposure width to be smaller than a length of the exposure region .   2. The scan exposure apparatus according to claim 1, wherein a gap between the light shielding member and the wafer surface is set to 500 [mu] m or less. The exposure mask is a reflective mask that reflects exposure light,
2. The scan exposure apparatus according to claim 1, wherein the projection optical system is a reflective optical system that reflects exposure light.   The scan exposure apparatus according to claim 1, wherein the exposure light includes EUV light. A method for manufacturing a semiconductor device in which a plurality of chip regions are two-dimensionally arranged on a wafer using the scan exposure apparatus according to claim 1 ,
Projecting exposure light from an exposure mask having an exposure pattern of a single chip area, and performing scan exposure on the wafer,
At the time of exposure, a light shielding member for defining an exposure width along a direction perpendicular to the scanning direction is arranged close to the wafer surface to block flare toward the chip area adjacent to the chip area to be exposed. A method for manufacturing a semiconductor device.   The exposure width defined by the light shielding member is changed according to a size of a chip area to be exposed and / or an interval between a chip area to be exposed and an adjacent chip area. 6. A method for producing a semiconductor device according to 5. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the exposure shot on the outer peripheral portion of the wafer is not accompanied by a dummy shot in a direction perpendicular to the scanning direction.

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