JP2004157327A - Mask for semiconductor device and exposure method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mask for a semiconductor device and an exposure method by which a defective chip or a defocus state can be prevented. <P>SOLUTION: Shot region layout is carried out so as to project mask regions where proper numbers of device patterns are arranged onto the center part and the peripheral part of a wafer, which is exposed while shielding the region not to be projected against light. A mask having a center region 101, where a plurality of device patterns 2 are arranged each in rows and columns and a plurality of peripheral regions 102 to 109 which are outside of the center region 101 and arranged as separated by light-shielding stripes, is used to layout the shot regions by projecting an appropriate region onto the center part and the peripheral part of the wafer and to expose. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a mask for manufacturing a semiconductor device having a multi-chip configuration, and an exposure method for transferring a device pattern to a wafer using the mask.
[0002]
[Prior art]
Conventionally, a step-and-repeat method and a step-and-scan method have been widely used for exposing a wafer with a fine pattern of a mask using an exposure apparatus. In the step-and-repeat method, a circular wafer is placed on a two-dimensionally movable wafer stage, and the wafer is irradiated with light through a mask on which a device pattern is drawn while sequentially stepping the wafer stage in the XY directions. The device pattern is transferred to a wafer, and a large number of device patterns are drawn vertically and horizontally. In the step-and-scan method, similarly, the wafer stage is sequentially stepped in the X and Y directions, and the mask stage holding the mask on which the device pattern is drawn is synchronized with the wafer stage while irradiating light only in the slit-shaped exposure region. By scanning, a device pattern drawn on a mask is transferred onto a wafer, and a large number of device patterns are drawn vertically and horizontally.
[0003]
However, in either case of using the step-and-repeat method or the step-and-scan method, the wafer to which the device pattern is transferred is circular, whereas the shot area to be exposed is rectangular. In the peripheral portion, a chip is generated in which a part of the shot area is missing and a part of the device pattern is not transferred.
[0004]
In addition, in the missing shot area, the focus (wafer stage height) performed during the exposure process and the wafer surface height detection position required for leveling (stage tilt) adjustment protrude outside the wafer, so that accurate adjustment cannot be performed. There is a problem.
[0005]
To address this problem, there is a method in which information on the wafer surface height acquired in an adjacent shot area is applied as it is before performing stepping on a shot area to be exposed, and adjustment is performed conveniently.
[0006]
However, the peripheral portion of the wafer is different from the central portion of the wafer due to warpage due to the heat treatment applied in the manufacturing process or due to in-plane variation of a polishing process such as CMP (Chemical Mechanical Polishing). The difference of the typical inclination is large. For this reason, the method of applying the information of the adjacent shot area as it is is not always an effective method.
[0007]
FIG. 1 is a view showing a conventional mask for a semiconductor device generally used.
[0008]
As shown in FIG. 1, a plurality of device patterns 2 are usually drawn on a semiconductor device mask 1, and a plurality of chips are simultaneously formed by simultaneously exposing the plurality of device patterns 2 to a wafer. It is configured to be.
[0009]
FIG. 2 is a diagram illustrating an example of a wafer on which a plurality of device patterns drawn on a mask are transferred.
[0010]
In FIG. 2, the circular wafer 10 has a boundary (referred to as a "wafer edge") between an invalid area 11b not used for manufacturing product chips and an effective area 11a used. The width of the invalid area 11b is, for example, 4 mm. On the circular wafer 10, 58 24 mm × 24 mm shot regions (regions exposed by one stepping operation) 12 exposed by the device pattern of the mask and indicated by solid lines are formed. Of these, in each of the shot areas 12a that do not overlap the invalid area 11b, 16 chip areas (indicated by dotted lines) to which one device pattern is exposed are formed.
[0011]
However, in the shot area 12b formed in the peripheral portion of the wafer, in which a part of the shot area protrudes from the wafer edge 11, a chip chip indicated by a cross is generated. In the peripheral shot area 12b, the focus and leveling of the entire shot area are not adjusted, so that defocus is likely to occur. In particular, the chip 13 indicated by the mark △ tends to cause defocus.
[0012]
Therefore, in a step-and-repeat type exposure apparatus, when a forbidden band having a fixed width is provided around a wafer, and a part is present in the forbidden band, and the remaining part is exposed to a shot area outside the wafer, In some cases, the stage is shifted to a boundary position of a forbidden band to perform focus adjustment, and is then returned to the original position for exposure (see Patent Document 1).
[0013]
Further, in a step-and-scan type exposure apparatus, there is a step-and-scan type exposure apparatus in which the exposure around the wafer is performed not for one shot but only for the chip that can be taken (the whole is within the wafer edge), mainly for the purpose of improving the throughput. . As a result, the measurement error of the focus around the wafer is reduced because the exposure area outside the wafer does not exist (see Patent Document 2).
[0014]
[Patent Document 1]
JP-A-6-29186 (paragraph numbers 0029 to 0039, FIGS. 7 and 8)
[Patent Document 2]
JP-A-9-22863 (paragraph numbers 0007 to 0019, 0034 to 0038, FIGS. 3, 5, 6, and 11)
[0015]
[Problems to be solved by the invention]
However, even the method disclosed in Patent Document 1 cannot prevent the generation of chipped chips. The fine pattern formed on the chip is peeled off during the subsequent manufacturing process and becomes a source of particles. As a result, the yield decreases. Further, in this method, complicated stage control is required, and when returning to the exposure position after performing the focus control, a focus shift may occur.
[0016]
Even if the method disclosed in Patent Document 2 can be favorably applied when exposing a mask in which a plurality of device patterns are arranged only in the scanning direction, as shown in the embodiment of this document, However, when a plurality of device patterns are arranged in a direction perpendicular to the scanning direction, it is difficult to apply the device pattern. That is, if the wafer is used without waste, generation of chipped chips cannot be prevented.
[0017]
Furthermore, even if the device patterns are arranged only in one row in the direction perpendicular to the scanning direction, as described in paragraph 0038 of this document, it is impossible to completely prevent the occurrence of chipped chips. Can not.
[0018]
Further, the method of Patent Document 2 cannot completely prevent occurrence of defocus. For example, in FIG. 2 of the present specification, when scanning is performed in the vertical direction of the drawing, even when the method of Patent Document 2 is applied, defocus is likely to occur in the chip 13 indicated by the triangle mark. This is because a part of the wafer surface height detection position (for example, CR1 and CR3 in FIG. 6 of Patent Document 2) placed at positions close to both ends of the slit-shaped exposure region protrudes from the wafer edge.
[0019]
In view of the above circumstances, the present invention avoids the generation of chipped chips that are sources of particles. It is another object of the present invention to provide a semiconductor device mask capable of minimizing defocus which causes a reduction in yield together with particles, and an exposure method using the mask.
[0020]
[Means for Solving the Problems]
The semiconductor device mask of the present invention that achieves the above object has the same plurality of device patterns, and exposes the wafer by projecting the device patterns onto a wafer mounted on a wafer stage of a projection exposure apparatus. Semiconductor device mask
A central region in which a plurality of device patterns are arranged vertically and horizontally, a plurality of peripheral regions arranged outside the central region, at least one of the device patterns being arranged, and a peripheral region adjacent to the central region and the central region And a light-shielding band that is arranged between the adjacent regions and between adjacent peripheral regions and blocks the irradiated light so as to separate the regions from each other.
[0021]
As described above, the semiconductor device mask is divided into a plurality of regions, and a light-shielding band is provided at the boundary of each region, and it is possible to blindly shield a region other than a required region. Using this mask, it is possible to prevent chipping from occurring by projecting and exposing device patterns provided in appropriate regions on the central portion and peripheral portion of the wafer, respectively, from the inside of the wafer edge. is there. Furthermore, by adjusting the light-shielding band, the adjustment function of the exposure apparatus can be appropriately operated irrespective of the size of each area, and the occurrence of defocus can be prevented.
[0022]
An exposure method according to the present invention for achieving the above object is a semiconductor device mask having the same plurality of device patterns, and exposing the wafer by projecting the device patterns onto the wafer, wherein each of the plurality of devices has a plurality of vertical and horizontal devices. A central region in which patterns are arranged, a plurality of peripheral regions arranged outside the central region, each having at least one of the device patterns, and a peripheral region adjacent to the central region and the central region. And a semiconductor device mask having a light-shielding band arranged between adjacent peripheral regions and interfering with each other by blocking irradiated light, and mounted on a wafer stage of a projection exposure apparatus. An exposure method for exposing a wafer, comprising:
A central shot area on which the central area is projected is allocated to a central portion of the wafer, and when the central area is projected, a part of the central area projects from a wafer edge. Performing a shot area allocation for allocating a peripheral shot area in which any one of the areas is projected inside a wafer edge in a peripheral portion of the wafer;
The central portion of the wafer, while shielding the plurality of peripheral regions, exposes by projecting the central region to the allocated central shot region,
The peripheral part of the wafer is characterized by projecting a peripheral area corresponding to the allocated peripheral shot area and exposing the peripheral area except for the central area and the corresponding peripheral area by shielding light.
[0023]
In this way, a mask having a plurality of regions that can be individually projected and exposed on the wafer, divided by the light shield, is used. Exposure is performed by allocating shots for projecting further inward, whereby occurrence of chipped chips can be prevented. Furthermore, by appropriately allocating shot areas, it is possible to prevent occurrence of defocus.
[0024]
In order to achieve the above object, the present invention provides an exposure method in which a plurality of device patterns are arrayed vertically and horizontally, a central mask pattern region surrounded by a light-shielding band, at least one device pattern is arranged, and the periphery is shielded from light. An exposure method for exposing a wafer placed on a wafer stage of an exposure apparatus using a plurality of peripheral mask pattern regions surrounded by a band,
In the center of the wafer, a central shot area where the central mask pattern area is projected is allocated, and when the central mask pattern area is projected, a part thereof protrudes from a wafer edge. Performing a shot area allocation for allocating a peripheral shot area in which any one of the plurality of peripheral mask pattern areas is projected inside a wafer edge at a peripheral portion of the wafer;
The central portion of the wafer is exposed by projecting the central mask pattern region onto the allocated central shot region,
The peripheral portion of the wafer is exposed by projecting a corresponding peripheral mask pattern region onto the allocated peripheral shot region.
[0025]
As described above, by preparing a plurality of mask pattern areas, allocating a shot area for projecting an appropriate mask pattern area to each of the central part and the peripheral part of the wafer and performing exposure, the occurrence of chipped chips is prevented. be able to.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0027]
FIG. 3 is a schematic configuration diagram showing a main part of an exposure apparatus used in an embodiment of the exposure method of the present invention.
[0028]
The present exposure apparatus 50 is used as an embodiment of the exposure method of the present invention, and a semiconductor device mask used in the present exposure apparatus corresponds to an embodiment of the semiconductor device mask of the present invention.
[0029]
A main part of the exposure apparatus 50 shown in FIG. 3 includes an illumination system 20 including a light source and a lens, a mask blind 21, and a semiconductor device mask (hereinafter, referred to as a “mask”) on which a plurality of identical device patterns are arranged. A mask holder 23 for holding the wafer 22, a projection optical system 24 for forming a reduced image of the device pattern drawn on the mask on the wafer, an XYZ stage device 25, and a holder 26 for holding the wafer 30 on the XYZ stage device 25 And a plurality of light emitting units 27a and a plurality of light receiving sensors 27b, and a wafer surface height detection system 27 for detecting the height of the position on the wafer surface.
[0030]
The mask blind 21 includes two sets of blades, and regulates a rectangular illumination area for illuminating the mask 22 from an illumination system to a predetermined size. The reduction ratio of the projection optical system is, for example, 1/4. The XYZ stage device 25 is mounted on an XY stage that reciprocates in the X-axis direction and the Y-axis direction perpendicular to the optical axis, and reciprocates in the Z-axis direction that is parallel to the optical axis. It consists of a controllable Z stage. By mounting the wafer 30 on the wafer holder 26 on the XYZ stage device 25, the wafer 30 can be freely moved in the XY plane and the Z-axis direction, and the inclination with respect to the optical axis can be adjusted. Each of the plurality of light emitting units 27a of the wafer surface height detection system 27 irradiates a predetermined position (wafer surface height detection position) on the surface of the wafer 30 with light from an oblique direction. Then, light reflected obliquely on the surface of the wafer 30 is received by light receiving sensors 27b provided corresponding to the respective light emitting units 27a. The light receiving sensor 27b has a position detecting function, and detects the height of the irradiated position on the wafer surface based on the position where the reflected light is detected. That is, the heights of a plurality of detection positions on the wafer surface are detected using the plurality of sets of the light emitting units 27a and the light receiving sensors 27b.
[0031]
Prior to the actual exposure of the wafer 30, shot area allocation is performed to determine how to arrange on the wafer 30 a shot area to be exposed to which device pattern provided on the mask 22. Then, the wafer 30 is placed on a wafer holder 26 on the XYZ stage device 25 (hereinafter, the XYZ stage device and the wafer holder are collectively referred to as a “wafer stage”), and has a predetermined position in accordance with a predetermined shot area allocation. And exposure of each shot area is performed. At this time, as will be described later, the mask blind 21 is adjusted, and only a necessary one of a plurality of device patterns arranged on the mask is projected on the wafer. Further, for each shot area, the height of the wafer surface is detected by the wafer surface height detection system 27, and at least one of the height and the inclination of the wafer stage is controlled based on the detection result. (Hereinafter, the height adjustment and the tilt adjustment of the stage are collectively referred to as “focus adjustment”).
[0032]
Hereinafter, the exposure procedure will be described more specifically for the step-and-repeat method and the step-and-scan method.
[0033]
In the case of a step-and-repeat type exposure apparatus, at the time of exposure, the mask holder 23 is fixed at a predetermined position, and a portion of the mask 22 in an illumination area regulated by the mask blind 21 is illuminated. Then, the pattern on the mask provided in the illumination area is reduced at the reduction rate of the projection optical system 24, and the illumination area on the surface of the wafer 30 located below the projection optical system 24 is reduced at the reduction rate. To the area of the specified size. At the same time, the wafer stage on which the wafer 30 is placed is moved to a predetermined position according to the shot area allocation. As a result, a predetermined pattern is projected onto a predetermined shot area, and the wafer is exposed. Then, the entire surface of the wafer 30 is exposed by moving the wafer stage stepwise in the XY plane and performing the same exposure each time.
[0034]
At the position where the wafer stage has been moved in accordance with the shot area allocation, prior to exposure of each shot area, the wafer surface height detection system 27 detects the height of a plurality of locations on the wafer surface. Then, using the data, at least one, and preferably both, of the height and inclination in the Z direction of the wafer stage are controlled so that the entire shot area is focused.
[0035]
In a step-and-repeat type exposure apparatus, a maximum exposure area (exposure area) in which exposure can be performed within a required dimensional error range is defined. Then, the wafer surface height detection positions are provided at a total of five points, for example, at the center of the exposure-possible region and at positions slightly inside from the four corners. When all five points are inside the wafer edge of the wafer 30 and the data of the wafer surface height is obtained at all the detection positions, the focusing can be performed with a predetermined accuracy.
[0036]
In the case of a step-and-scan exposure apparatus, a second mask blind (not shown) is provided in addition to the mask blind 21 shown in FIG. The mask 22 is illuminated by the illumination light formed into a slit shape by the second mask blind. Then, the pattern provided in the slit-shaped illumination area is reduced at the reduction rate of the projection optical system 24, and the illumination area on the surface of the wafer 30 located below the projection optical system 24 is reduced at the reduction rate. Projected onto the slit exposure area.
[0037]
Then, while keeping the second mask blind fixed, the mask holder 23 and the wafer stage are synchronously moved in a direction intersecting the longitudinal direction of the slit-shaped exposure region (usually a direction intersecting vertically), and the mask 23 and the wafer stage are moved. The wafer 30 is moved (scanned). As a result, the pattern in the illumination area regulated by the mask blind 21 of the mask 22 is projected onto the shot area on the wafer 30, and the wafer is exposed. At this time, the mask blind 21 is also moved in synchronization with the mask 22. Actually, exposure is performed by moving the wafer while the position of the slit-shaped exposure area is fixed. However, effectively, the shot is performed by moving (scanning) the slit-shaped exposure area on the wafer. It can be considered that the exposure in the area is performed.
[0038]
Exposure of the entire surface of the wafer 30 by stepping is the same as in the step-and-repeat method.
[0039]
In the case of the step-and-scan method, a plurality of wafer surface height detection positions are provided in or near the slit-shaped exposure region on the moving direction side thereof, and the height of the wafer surface is detected. Utilizing this result, the height or inclination of the stage is controlled so that the wafer surface in the portion where the slit-shaped exposure area is presently is focused. The wafer surface height detection position may be arranged in one or more rows in the longitudinal direction of the slit-shaped exposure area (usually, a direction perpendicular to the scanning direction) and slightly shorter than the dimension of the slit-shaped exposure area in the longitudinal direction. And moves in synchronization with scanning of the slit-shaped exposure area. Then, while detecting the surface height in the shot area, if all the detection positions are inside the wafer edge of the wafer 30, the focus adjustment can be performed with a predetermined accuracy.
[0040]
In both the step-and-repeat method and the step-and-scan method, as described above, detection of the wafer surface height of each shot area is performed by exposing the wafer stage according to the shot area allocation in order to perform exposure of each shot area. It is possible to perform focus adjustment and exposure at the position where is moved.
[0041]
In this case, as shown in FIG. A wafer surface height detection system 27 is provided at a position where exposure is performed. Further, the wafer surface height detection system 27 can be provided at a position different from the position where the exposure is performed. In this case, prior to exposure, at the position where the surface height detection system 27 is provided, the wafer stage is moved according to the shot area allocation, the wafer surface height is detected for each shot area, and the result is stored. . Then, at the time of exposure of each shot area, focus adjustment is performed using the stored measurement result.
[0042]
Next, the semiconductor device mask of the present invention will be described in detail. FIG. 4 is a diagram showing an embodiment of the semiconductor device mask 22 of the present invention.
[0043]
In the semiconductor device mask 22 shown in FIG. 4, a plurality of the same device patterns 2 for exposing a wafer are arranged. One central region (first region) 101 in which two device patterns 2 are arranged vertically and horizontally, and peripheral regions (second region 2 to ninth region) 102 to 109 arranged outside the central region. is there. The peripheral areas are two peripheral areas (third area, eighth area) 103 and 108 in which two device patterns are arranged horizontally, and two peripheral areas (fifth area, There are four peripheral areas (second area, fourth area, seventh area, and ninth area) 102, 104, 107, and 109 in which one device pattern is arranged. Also, between the central region (first region) 101 and peripheral regions (third, sixth, eighth, and fifth regions) 103, 105, 108, and 105 adjacent to the central region, and peripheral regions adjacent to each other. Between each other, a light-shielding band 100 that blocks light and separates regions from each other is arranged.
[0044]
The width of the light shielding band 100 is, for example, 300 μm. On the other hand, between the plurality of device patterns 2 arranged in the same area, a scribe area having a width smaller than the width of the light-shielding band, for example, 100 μm or less is provided. As described above, the exposure apparatus 50 used in the exposure method of the present invention has the mask blind 21 that regulates the illumination area. The setting position of the mask blind 21 has an error of 100 μm or more. The width of the light-shielding band 100 is larger than the position setting error of the mask blind 21.
[0045]
Each of these dimensions is a dimension when projected on the wafer 30. That is, the actual dimensions are obtained by multiplying these dimensions by the reciprocal of the reduction ratio. Hereinafter, unless otherwise specified, dimensions on a mask are also expressed as dimensions projected on a wafer.
[0046]
As described above, the semiconductor device mask 22 is divided into a plurality of regions, and one central region is provided with one first region 101 in which the device patterns 2 are arranged most. The second to ninth regions 102 to 109 in which 2 are arranged are provided. In particular, in the example of FIG. 4, a plurality of peripheral regions 102 to 109 are arranged so as to surround the center region 101. At the boundary between the regions, a light-shielding band 100 whose width is wider than the interval between the device patterns and wider than the position setting error of the mask blind 21 that regulates the illumination region of the exposure apparatus 50 is provided. . Therefore, since the illumination light can be completely blocked by blinds in areas other than the required area, the exposure can be limited to any area.
[0047]
Here, an example of the semiconductor device mask 22 in which 16 identical device patterns 2 are arranged has been described, but the number of device patterns 2 is not limited to 16. Also, the number of device patterns arranged in the central region and the peripheral region is not limited to this example.
[0048]
FIG. 5 is a diagram showing an embodiment of the exposure method of the present invention.
[0049]
In FIG. 5, the boundaries between shot areas are represented by solid lines, and the boundaries between chips are represented by thin broken lines. The same applies to FIGS. 6, 8, and 10 described later.
[0050]
As shown in FIG. 5, a central shot area where the first device area of the mask 22 is projected and four device patterns 2 are transferred on the inner side (central part) of the wafer 30 excluding a part adjacent to the wafer edge 31. Reference numerals 201 are assigned to each of a plurality of vertical and horizontal lines at a constant pitch. However, when the central shot area 201 is allocated, a chip is generated in which only a part of the device pattern is transferred. One device pattern 2 of the mask 22 is arranged around the wafer so that the chip is not formed. Peripheral shot areas 202a to 202c are allocated to which one of the second to ninth areas in which the two device patterns 2 are arranged vertically or horizontally are projected.
[0051]
The mask 22 and the wafer 30 shown in FIG. 4 are placed on the exposure apparatus 50 shown in FIG. 3 in the central portion of the wafer where the central shot area 201 is allocated, and the exposure apparatus 50 shown in FIG. Exposure is performed by projecting the central region 101 by covering the peripheral region second to ninth regions of the mask 22 with the mask blind 21.
[0052]
In the peripheral portion of the wafer, for example, when exposing the peripheral shot area 202a indicated by oblique lines in FIG. 5, the third area of the mask 22 is projected onto the peripheral shot area 202a and exposed, that is, the third area of the mask 22 is exposed. When the mask blind 21 is extended to the position of the light-shielding band 10 surrounding the outside of the first to ninth regions and the illumination region is not regulated by the mask blind 21, the center of the mask 22 is located in a range indicated by 210 a in FIG. The wafer stage is moved so that the wafer 30 is located at a position where the entire area and the peripheral areas (first to ninth areas) are projected. Then, an area other than the third area of the mask 22 is covered with the mask blind 21, and the third area is projected to expose the wafer. As a result, the two device patterns arranged side by side, which are arranged in the third region of the mask 22, are transferred to the peripheral shot region 202a indicated by oblique lines.
[0053]
Similarly, for example, when exposing the peripheral shot area 202b indicated by oblique lines in FIG. 5, if the illumination area regulation by the mask blind 21 is not performed, the central area and the peripheral area of the mask 22 are projected in the range 210b. After the wafer stage is moved to a position other than the second area, the mask 22 covers an area other than the second area with the mask blind 21, and projects the second area to expose the wafer. As a result, one device pattern arranged in the second area is transferred to the peripheral shot area 202b indicated by oblique lines. Further, when exposing the peripheral shot area 202c, if the certification area regulation by the mask blind is not performed, the wafer stage is moved to a position where the central area and the peripheral area of the mask 22 are projected in the range of 201c, The fifth area is projected, and two vertically arranged device patterns arranged in the fifth area are transferred.
[0054]
As described above, the mask 22 is divided into the plurality of regions 101 to 109 by the light-shielding band having a width equal to or larger than the position setting error of the mask blind 21 of the exposure apparatus 50, and the peripheral portion of the wafer where chipped chips can be generated is masked. An area in which chipped chips are not generated is selected from the peripheral area of No. 22, light is shielded by a mask blind in areas other than the selected area, and the wafer is exposed by the selected area. As a result, generation of chipped chips can be prevented, and generation of particles due to film peeling can be prevented.
[0055]
In the embodiment of the exposure method of the present invention described above, as shown in FIG. 4, the mask 22 in which the peripheral regions 102 to 109 are arranged outside all four sides and all four vertices of the rectangular central region 101 is used. used. That is, the mask 22 shown in FIG. 4 has two peripheral regions 103 and 108 in which a plurality of device patterns 2 are arranged in the horizontal direction, and a peripheral region in which a plurality of device patterns 2 are arranged in the vertical direction. Two peripheral regions 105, 106, 102, 104, 107, and 109 are provided, each of which has one device pattern. However, it is not essential to use all of the peripheral regions 102 to 109 in order to prevent occurrence of a chip. For example, a central area includes a peripheral area in which a plurality of device patterns are arranged in a horizontal direction, a peripheral area in which a plurality of device patterns are arranged in a vertical direction, and a peripheral area in which one device pattern is arranged. Even if a mask arranged outside the two sides and one vertex of 101 is used, the occurrence of chipped chips can be prevented.
[0056]
However, as described later, in order to prevent the occurrence of defocus, it is preferable to use a mask in which peripheral regions are arranged outside all sides and vertices of the central region 101 as shown in FIG.
[0057]
In the mask 22 shown in FIG. 4, the central region 101 and all of the peripheral regions 102 to 109 are arranged on the same substrate. As described above, by using the mask in which both the central region and the plurality of peripheral regions are arranged on the same substrate, one wafer 30 or a plurality (for example, 25) wafers including the wafer 30 can be obtained. The exposure time can be reduced by eliminating the necessity of exchanging masks in the process of exposure processing for one lot constituted.
[0058]
However, the exposure method of the present invention is performed while exchanging the mask for the central region in which the central region is arranged and the mask for the peripheral region in which all or a part of the peripheral region is arranged as necessary. You can also.
[0059]
In this case, for example, if the central region mask is provided with a central region in which four device patterns 2 are arranged vertically and horizontally, that is, a total of 16 device patterns 2 are arranged, each step when exposing the central portion of the wafer 30 is performed. 16 device patterns can be transferred. As a result, the number of steps and the exposure time required to expose one wafer can be reduced.
[0060]
Further, in addition to such a mask for the central region, a mask as shown in FIG. 4 can be used as a mask for the peripheral region. Then, the central region 101 of the mask 22 in FIG. 4 is used as an intermediate region in which a plurality of device patterns are arranged vertically and horizontally, although the number is small compared to a central region mask in which 16 device patterns are arranged. be able to. That is, the outermost peripheral portion of the peripheral portion excluding the central portion exposed using the central region mask is exposed using any of the second to ninth peripheral regions, and the outermost peripheral portion is exposed. An intermediate portion between the portion and the central portion can be exposed using the intermediate region.
[0061]
In this case, paying attention to the exposure processing of the outermost peripheral portion and the intermediate portion, as in the embodiment described with reference to FIG. 5, an appropriate one of the central region and the peripheral region arranged on one mask Is used to expose a central portion and a peripheral portion of a wafer. That is, the intermediate portion and the outermost peripheral portion in this case correspond to the central portion and the peripheral portion in the embodiment described with reference to FIG. 5, respectively.
[0062]
FIG. 6 is a schematic configuration diagram showing an example of a processed wafer exposed by the exposure method according to the embodiment of the present invention.
[0063]
The processed wafer 40 shown in FIG. 6 has a circular shape, and a wafer edge 41 is formed several mm inward from the peripheral edge.
[0064]
In the center of the processed wafer 40, 173 center shot areas 201 each forming four chips, which are projected and exposed to the first area of the mask 22, are formed.
[0065]
On the other hand, in the peripheral portion of the wafer, five peripheral shot regions 202 where the second region of the mask 22 is projected and exposed so as not to generate chipped chips, five peripheral shot regions 203 where the third region is exposed, Five peripheral shot areas 204 where the fourth area is exposed, two peripheral shot areas 205 where the fifth area is exposed, two peripheral shot areas 206 where the sixth area is exposed, and 5 where the seventh area is exposed One peripheral shot area 207, four peripheral shot areas 208 where the eighth area is exposed, and five peripheral shot areas 209 where the ninth area is exposed are formed.
[0066]
As described above, the processed wafer exposed by the exposure method of the present embodiment does not generate chipped chips and does not generate particles due to film peeling.
[0067]
However, even when a chip does not occur, occurrence of defocus cannot always be prevented. In order to completely prevent the occurrence of defocus, it is necessary to appropriately assign shot areas in consideration of the type of exposure apparatus to be used and the arrangement of the wafer surface height detection position. For that purpose, it may be necessary to optimize the arrangement of the mask to be used.
[0068]
First, the case of the step and repeat method will be described.
[0069]
FIG. 7 schematically shows the relationship between the wafer surface height detection positions 5a to 5e located at the center and four corners of the exposure area in the step-and-repeat type exposure apparatus, and the position where the mask 22 is projected. Was. In the case shown in FIG. 7B, the wafer surface is located at the center and four corners of the range where the central region 101 and the peripheral regions 102 to 109 of the mask 22 are projected when the illumination region regulation by the mask blind 21 is not performed. Height detection positions 5a to 5e are located. Therefore, if the range 210 where the entire central region and the peripheral region is projected is within the wafer edge, all the wafer surface height detection positions are located inside the wafer edge 31 and the wafer edge height detection positions are located at all the wafer surface height detection positions. Of the wafer surface can be measured. Then, by utilizing the measurement result, the height and inclination of the wafer stage can be adjusted, and accurate focusing can be performed.
[0070]
When shot area allocation is performed as shown in FIG. 5, this condition is satisfied in a portion near the center of the wafer 30, and defocus does not occur. However, in the portion close to the wafer edge 31, even if the shot is arranged so as to expose the central region of the mask 22 in FIG. 5, some of the plurality of wafer surface height detection positions are outside the wafer edge 31, and defocusing occurs. May occur.
[0071]
For example, FIG. 8A shows an example in which defocus occurs as described above. In FIG. 8A, when exposing the central area 101 of the mask 22 to the position P1 indicated by oblique lines, the area 210 on which the central area and the entire peripheral area are projected when the illumination area is not regulated by the mask blind 21. , Indicated by a thick broken line. As shown in FIG. 8A, a part of a range 210 in which the entire central region and the peripheral region is projected is protruded outside the wafer edge 31, and the first to fifth detections of the wafer surface heights located at the four corners are performed. The first detection position 5a among the positions 5a to 5e extends outside the wafer edge 31. Therefore, defocus may occur in this shot area.
[0072]
On the other hand, FIG. 8B shows an example in which the shot area allocation is changed so that defocus does not occur.
[0073]
In FIG. 8A, the position P1 indicated by oblique lines, which has been shot area allocation so as to expose the central area 101 of the mask, is changed in FIG. Done.
[0074]
That is, the lower half of the position P <b> 2 indicated by the oblique line rising to the left is exposed in the third region 103 of the mask 22. In this case, the range 210 in which the entire central region and peripheral region are projected is indicated by a thick broken line. That is, in order to perform exposure in the third region 103 at the position P2 indicated by the oblique line rising leftward, the wafer stage is set so that the range 210 where the entire central region and the peripheral region of the mask 22 is projected is at the position indicated by the thick broken line. To move. As can be seen from the figure, in this case, the range 210 in which the entire central region and peripheral region are projected falls inside the wafer edge 31. Accordingly, all of the wafer surface height detection positions 5a to 5e are arranged inside the wafer edge 31, and the occurrence of defocus can be prevented. The position P3 indicated by the upper right diagonal line in the upper half is further divided into two portions, left and right, and each is assigned so as to be exposed in the second region 102 of the mask 22, so that defocusing is also performed in this portion. Can be prevented from occurring.
[0075]
Further, in FIG. 8B, the assignment was changed so that defocus does not occur also in other shot areas. For example, the allocation is changed so that the position P4 indicated by the cross hatching is exposed in the fifth region 105 of the mask 22.
[0076]
Note that, depending on the number of wafer surface height detection positions of the exposure apparatus and their respective roles, it is not always necessary to allocate shot areas so that all of them are located within the wafer edge 31. For example, a number of wafer surface height detection positions required to assure predetermined focus accuracy are provided relatively inside the exposure area, and additional wafer surface height detection positions are further provided outside the exposure area. It is assumed that an exposure apparatus having a focus control function for further improving accuracy is used when measurement data is obtained and obtained therefrom.
[0077]
In this case, since only the wafer surface position detection positions necessary to guarantee the predetermined accuracy are provided inside, all of the necessary wafer surface height detection positions are all within the wafer edge 31. The shot area allocation may be performed so that the shot area is located at the position. The same can be considered when using a step-and-scan type exposure apparatus.
[0078]
In the above description, as shown in FIG. 7B, it is assumed that all the wafer surface height detection positions 5a to 5e fall within the range 210 where the central region and the peripheral region of the mask 22 are projected. did. However, depending on the dimensions of the device pattern 2 and the arrangement of the wafer surface height detection position, as shown in FIG. 7A, the width of the light shielding bands 100a to 100d of the mask 22 is changed to the width of the mask blind 21 of the exposure apparatus. Even when the size is set to be sufficient to absorb the set position error, the wafer surface height detection positions 5a, 5b, 5d, and 5e located at the four corners of the exposure area are projected over the central area and the entire peripheral area. It may be outside the range 210. In such a case, in a portion close to the wafer edge 31, even if exposure is performed using any of the peripheral regions, it may not be possible to put all of the wafer surface height detection positions 5 a to 5 e into the wafer edge 31.
[0079]
As a countermeasure, as shown in FIG. 7B, the width of the light-shielding bands 100a to 100d is increased so that all the wafer surface height detection positions 5a to 5e are projected over the entire central region and the peripheral region. It is possible to optimize the arrangement of the peripheral region in the mask 22 so as to be within 210.
[0080]
Next, the case of the step-and-scan method will be described.
[0081]
In FIG. 9, the slit-shaped exposure region 15 and the wafer surface height detection positions 5a to 5e, and the central region and peripheral regions (second to ninth regions) of the mask 22 are projected in the step-and-scan exposure apparatus. The relationship with the position is schematically shown.
[0082]
The figure shows a state in which the illumination area regulation by the mask blind 21 is not performed. In this example, the detection points 5 are arranged in a row in a direction intersecting (orthogonal to) the scanning direction A in which the slit-shaped exposure area 15 moves, that is, in the longitudinal direction of the slit-shaped exposure area 15. It moves in the scanning direction A in synchronization with the movement. Then, the height of the surface of the wafer at each detection point 5 is measured at a predetermined timing. For example, the wafer surface height detection position 5 is provided at the tip of the slit-shaped exposure area 15 on the movement direction A side or at a position slightly preceding. The measurement of the wafer surface height at each detection position is repeatedly performed during the period in which the scanning of the slit-shaped exposure region 15 is performed, and the height and inclination of the XYZ stage device 25 are adjusted based on the results. Perform continuously. As a result, a state in which a portion of the surface of the wafer 30 that is being exposed in the slit-shaped exposure region is being focused is maintained.
[0083]
Actually, the slit-shaped exposure area 15 and the wafer surface height detection position 5 are fixed, and the wafer 30 and the mask 22 move synchronously. However, for convenience, the slit-shaped exposure area 15 and the wafer surface height Description will be made on the assumption that the detection position 5 moves.
[0084]
Here, in order to perform accurate focus adjustment, it is necessary that all of the wafer surface height detection positions 5a to 5e are inside the wafer edge 31 of the wafer 30, and the height of the wafer surface can be accurately measured. However, unlike the case of the step-and-repeat method, the center of the mask 22 is covered over the entire range in which the wafer surface height detection positions 5a to 5e move, that is, when the illumination area regulation by the mask blind 21 is not performed. It is not essential that all the detection positions 5 a to 5 e are always inside the wafer edge 31 in the entire region where the region and the peripheral region are projected.
[0085]
For example, in the example shown in FIG. 9B, when exposing a shot area that projects one of the central area of the mask 22 or the fifth and sixth peripheral areas disposed on the left and right of the central area. think of. In this case, in order to perform accurate focus adjustment, five points are required while the wafer surface height detection position is moving within a range in which the exposed central region or the fifth and sixth peripheral regions are projected. Are required to be inside the wafer edge 31. However, for example, the wafer surface height detection position 5 is set within the range in which the second, third, and fourth peripheral regions disposed above the region to be exposed are projected (when the illumination region is not regulated by the mask blind 21). There is no problem if a part or all of the detection position is outside the wafer edge 31 while is moving. That is, even if an abnormal measurement result is obtained at the detection position located outside the wafer edge 31 during the period in which the detection position is outside the region to be exposed, If focus adjustment is performed using only the measurement result obtained in step (1), it is possible to prevent occurrence of defocus.
[0086]
FIG. 10A shows an example of a case where defocus occurs when the slit-shaped exposure area is scanned in the vertical direction and exposed by the step-and-scan method in the shot area allocation described with reference to FIG. In FIG. 10A, when exposing the central area 101 of the mask 22 to the position P1 indicated by oblique lines in the figure, when the illumination area is not regulated by the mask blind 21, the central area 101 and the left and right sides thereof are arranged. A range 220 in which the fifth and sixth peripheral regions 105 and 106 are projected is indicated by a thick broken line. As shown in FIG. 10A, when measuring the wafer surface height in the area surrounded by the broken line, the leftmost wafer surface height detection position 5a protrudes outside the wafer edge 31. Therefore, defocus may occur in this shot area.
[0087]
On the other hand, FIG. 10B shows an example in which the shot area allocation is changed so that defocus does not occur. In FIG. 10A, the position P1 indicated by oblique lines, which has been shot area allocation so as to expose the central area 101 of the mask, is divided in FIG. The date has been changed.
[0088]
First, a shot area allocation is performed so that a position P4 indicated by a cross diagonal line on the left half is exposed in the fifth area 105 of the mask 22. In order to expose the position P4 in the fifth region, the wafer stage is moved such that the range 230 where the central region 101, the fifth region 105, and the sixth region 106 of the mask 22 are projected is a position indicated by a thick broken line. . As can be seen from the figure, in this case, all of the wafer surface height detection positions 5a to 5e fall within the wafer edge 31, and the occurrence of defocus can be prevented.
[0089]
Then, the position P5 of the right half, also indicated by the oblique line of the cross, is allocated as another shot area for projecting the fifth area 105 similarly. Further, in FIG. 10B, the shot area allocation is changed for other shot areas so that defocus does not occur. That is, a shot area for projecting the fifth area 105 is assigned to the position indicated by the oblique line of the cross, and a shot area for projecting the second area 102 is assigned to the position P3 indicated by the oblique line that rises to the right.
[0090]
As described above, in both the step-and-repeat method and the step-and-scan method, the shot areas are allocated as shown in FIGS. 8B and 10B in consideration of the arrangement of the wafer surface height detection position. In addition, the occurrence of defocus can be prevented even in the peripheral shot area. That is, by allocating shot areas as shown in FIGS. 8B and 10B, even in the peripheral shot area, the wafer edge height detection positions required to guarantee high focus accuracy are all set at the wafer edge height detection positions. The height of the inner surface is detected, and the height and inclination of the stage can be adjusted using the detection result.
[0091]
However, even when the shot areas are allocated as shown in FIG. 5, the amount of defocus can be reduced. That is, at the stage where the shot areas are allocated, it is possible to determine which of the plurality of wafer surface height detection positions is outside the wafer edge 31, so that the measurement position at other positions excluding the measurement data at that detection position can be determined. The stage can be controlled using only the measurement data. Since there are few data points that can be used, the focus accuracy is lower than in the case where the data of all the detection points can be used. In some cases, only one of the height and inclination of the stage can be controlled. However, occurrence of large defocus can be prevented.
[0092]
Also in the case of the step-and-scan method, it may be preferable to optimize the mask as in the case of the step-and-repeat method. For example, as shown in FIG. 9A, even when the width of the light-shielding bands 100a to 100d of the mask 22 is set to a size sufficient to absorb a setting position error of the mask blind 21 of the exposure apparatus, The wafer surface height detection positions 5a and 5e provided at both ends are further outside the range in which the central region and the peripheral region of the mask 22 are projected in the longitudinal direction (lateral direction in the drawing) of the slit exposure region 15. May be. In such a case, in the portion close to the wafer edge 31, even if the shot area is allocated so as to perform exposure using any of the peripheral areas, the shot area cannot be included in all the wafer edges 31 at the wafer surface height detection position. Sometimes.
[0093]
As a countermeasure against this, as shown in FIG. 9B, the widths of the light-shielding bands (light-shielding bands in the vertical direction in the figure) 100a and 100b that define the area between the slit-shaped exposure regions 15 in the longitudinal direction are increased. It is possible to optimize the inside of the mask 22 so that the wafer surface height detection position is within the range where the central region and the peripheral region are projected.
[0094]
9B, the wafer surface height detection position 5 is drawn so as to be located further above the upper end of the wafer 22. However, this detection position moves downward in the figure along with the movement of the slit-shaped exposure area 15, and when it reaches an appropriate position, the required surface height of the wafer is measured. That is, in the case of the step-and-scan method, even when the width of the light-shielding band in the longitudinal direction (the left-right direction in the drawing) of the slit-shaped exposure region 15 is optimized, the light shielding in the scanning direction (the vertical direction in the drawing) is performed. There is no need to optimize the bandwidth.
[0095]
【The invention's effect】
As described above, according to the semiconductor device mask of the present invention, the mask is divided into a plurality of individually projectable regions by the light-shielding band. Further, according to the exposure method of the present invention, exposure is performed by assigning a shot area for projecting an appropriate area of the mask to each of the central part and the peripheral part of the wafer. For this reason, chipped chips that are likely to occur in the peripheral portion of the wafer can be prevented, and the yield of semiconductor chips can be improved. In addition, it is possible to prevent the occurrence of defocus which is likely to occur in the peripheral portion of the wafer, and to further improve the yield of semiconductor chips.
[Brief description of the drawings]
FIG. 1 is a diagram showing a mask for a semiconductor device generally used conventionally.
FIG. 2 is a diagram showing an example of a device formed by exposing a wafer.
FIG. 3 is a schematic configuration diagram showing a main part of an exposure apparatus used in an embodiment of the exposure method of the present invention.
FIG. 4 is a view showing an embodiment of a semiconductor device mask of the present invention.
FIG. 5 is a diagram showing an embodiment of the exposure method of the present invention.
FIG. 6 is a schematic configuration diagram showing an embodiment of a processed wafer of the present invention.
FIG. 7 is a diagram showing a relationship between a position where a semiconductor device mask of the present embodiment is projected and a surface height detection position of a wafer.
FIG. 8 is a diagram showing shot area allocation for preventing occurrence of defocus when performing exposure by a step-and-repeat method.
FIG. 9
FIG. 4 is a diagram illustrating a relationship between a position where the semiconductor device mask of the present embodiment is projected, a slit-shaped exposure region, and a wafer surface height detection position.
FIG. 10
FIG. 9 is a diagram illustrating shot area allocation for preventing occurrence of defocus when performing exposure by a step-and-scan method.
[Explanation of symbols]
1,22 Masks for semiconductor devices
2 Device pattern
5 Wafer surface height detection position
5a First detection position
5b Second detection position
5c Third detection position
5d 4th detection position
5e Fifth detection position
10,30,40 wafer
11,31,41 Wafer edge
11a Effective area
11b Invalid area
12 shot area
12a Shot area that does not overlap the invalid area
12b Shot area formed around wafer
13 chips
15 Slit exposure area
20 Lighting system
21 Mask blind
22 Mask
22a frame
23 Mask holder
24 Projection optical system
25 XYZ stage device
26 Holder
27 Wafer surface height detection system
27a Light emitting unit
27b Light receiving sensor
50 Exposure equipment
100 shade zone
101 1st area
102 Second area
103 Third Area
104 4th area
105 5th Area
106 Area 6
107 7th area
108 Area 8
109 9th area
201 center shot area
202 Peripheral shot area where the second area is exposed
202a, 202b, 202c Shot areas indicated by oblique lines
203 Peripheral shot area where third area is exposed
204 Peripheral shot area where the fourth area is exposed
205 Peripheral shot area where fifth area is exposed
206 Peripheral shot area where the sixth area is exposed
207 Peripheral shot area where seventh area is exposed
208 Peripheral shot area where the eighth area is exposed
209 Peripheral shot area where ninth area is exposed
210 Range where the entire central area and peripheral area are projected
210a Position where third region is projected and exposed
210b Position where the second area is projected and exposed
210c Position where fifth region is projected and exposed
220 Range in which the central area, the fifth area, and the sixth area are projected

Claims (11)

A semiconductor device mask having the same plurality of device patterns, and exposing the wafer by projecting the device pattern onto a wafer mounted on a wafer stage of a projection exposure apparatus,
A central area in which a plurality of device patterns are arranged vertically and horizontally, a plurality of peripheral areas arranged outside the central area and at least one of the device patterns arranged, and a peripheral area adjacent to the central area and the central area A mask for a semiconductor device, comprising: a light-shielding band disposed between the region and between adjacent peripheral regions, and blocking a light to be irradiated to define the regions from each other. The plurality of peripheral regions include a peripheral region including one device pattern, a peripheral region in which a plurality of device patterns are vertically arranged, and a peripheral region in which a plurality of device patterns are horizontally arranged. 2. The semiconductor device mask according to claim 1, wherein: The projection exposure apparatus is for detecting the height of the surface of the wafer placed on the wafer stage at a plurality of detection positions to adjust the height or inclination of the stage,
The light-shielding band has a predetermined width so that the plurality of detection positions are arranged in a range in which the entire central region and the plurality of peripheral regions defined by the light-shielding band are projected on the wafer. 3. The mask for a semiconductor device according to claim 1, wherein the mask is provided. The projection exposure apparatus is a step-and-scan exposure apparatus that exposes the wafer by moving a slit-shaped exposure area to a wafer placed on the wafer stage, and adjusts the height of the surface of the wafer. It detects at a plurality of detection positions in the longitudinal direction of the slit-shaped exposure region and adjusts the height or inclination of the wafer stage,
In the light-shielding band, the plurality of detection positions are arranged within a longitudinal dimension of the slit-shaped exposure region in a range in which the central region and the plurality of peripheral regions defined by the light-shielding band are projected on the wafer. 3. The semiconductor device mask according to claim 1, wherein the mask has a predetermined width. A semiconductor device mask having the same plurality of device patterns and exposing the wafer by projecting the device patterns onto the wafer, comprising: a central region in which a plurality of device patterns are arranged vertically and horizontally; and a central region. A plurality of peripheral regions, each of which is arranged at least one of the device patterns, between the central region and the peripheral region adjacent to the central region and between adjacent peripheral regions, An exposure method for exposing a wafer mounted on a wafer stage of a projection exposure apparatus, using a semiconductor device mask having a light-shielding band that separates regions by shielding the irradiated light,
A central shot area on which the central area is projected is allocated to a central part of the wafer, and when the central area is projected, a part of the central part is protruded from a wafer edge. Performing shot area allocation for allocating a peripheral shot area in which one of the areas is projected inside the wafer edge;
The central portion of the wafer projects the central region onto the allocated central shot region, and exposes the plurality of peripheral regions by blocking light,
The peripheral portion of the wafer projects a corresponding peripheral region onto the allocated peripheral shot region, and exposes the peripheral region except for the central region and the corresponding peripheral region by shielding light. Exposure method. The projection exposure apparatus, for each of the shot areas, at a position where the wafer stage is moved according to the shot area allocation, the height of the surface of the wafer placed on the wafer stage to a wider range than the shot area Detected at a plurality of detection positions arranged, to adjust the height or inclination of the wafer stage,
The shot area allocation is performed in the wafer surface height detection in each of the central shot area and the peripheral shot area, such that the plurality of detection positions are arranged inside the wafer edge. The exposure method according to claim 5. The projection exposure apparatus is a step-and-scan type exposure apparatus that exposes the wafer by moving a slit-shaped exposure area on a wafer mounted on the wafer stage,
For each shot area, at the position where the wafer stage has been moved according to the shot area allocation, the height of the surface of the wafer placed on the wafer stage is set in the longitudinal direction of the slit-shaped exposure area. Is also detected at a plurality of detection positions arranged in a wide range, to adjust the height or inclination of the wafer stage,
The shot area allocation is performed in the wafer surface height detection in each of the central shot area and the peripheral shot area, such that the plurality of detection positions are arranged inside the wafer edge. The exposure method according to claim 5. The plurality of peripheral regions include a first peripheral region including one device pattern, a second peripheral region in which a plurality of device patterns are vertically arranged, and a third peripheral region in which a plurality of device patterns are horizontally arranged. A peripheral shot area, wherein the peripheral shot area includes a first peripheral shot area where the first peripheral area is projected, a second peripheral shot area where a second peripheral area is projected, 6. The exposure method according to claim 5, further comprising a third peripheral shot area onto which a third peripheral area is projected. A plurality of device patterns are arranged vertically and horizontally, and a central mask pattern region whose periphery is surrounded by a light-shielding band, and a plurality of peripheral mask pattern regions where at least one device pattern is arranged and the periphery is surrounded by a light-shielding band. An exposure method for exposing a wafer placed on a wafer stage of an exposure apparatus using
In the center of the wafer, a central shot area where the central mask pattern area is projected is allocated, and when the central mask pattern area is projected, a part of the central mask pattern area protrudes from a wafer edge. Performing a shot area allocation for allocating a peripheral shot area in which any one of the plurality of peripheral mask pattern areas is projected inside a wafer edge at a peripheral portion of the wafer;
The central portion of the wafer is exposed by projecting the central mask pattern region onto the allocated central shot region,
An exposure method, wherein a peripheral portion of the wafer is exposed by projecting a corresponding peripheral mask pattern region onto the allocated peripheral shot region. At least two mask pattern regions selected from the central mask pattern region and the plurality of peripheral mask pattern regions are arranged on the same mask substrate, and the peripheral portion of the wafer is assigned to the corresponding peripheral mask pattern region. 10. The exposure method according to claim 9, wherein the exposure is performed by projecting the projected light onto the peripheral shot area and exposing the other mask pattern area disposed on the same mask substrate by blocking light. The peripheral mask pattern region includes a first peripheral mask pattern region in which one device pattern is arranged, a second peripheral mask pattern region in which a plurality of the device patterns are vertically arranged, and a plurality of the device patterns. Has a third peripheral mask pattern region arranged horizontally,
The peripheral shot area includes a first peripheral shot area on which the first peripheral mask pattern area is projected, a second peripheral shot area on which the second peripheral mask pattern area is projected, and a third peripheral shot area. 11. The exposure method according to claim 9, further comprising a third peripheral shot area onto which a mask pattern area is projected.

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