JP2010128367A - Method for creating reticle layout data and device for creating reticle layout data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To create reticle layout data having various scribe widths in accordance with semiconductor chips, and to provide a method for creating reticle layout data and a device for creating reticle layout data. <P>SOLUTION: Scribe widths actually necessary for dicing are set for the reticle layout data of a plurality of types of semiconductor chips. A chip scribe region to be laid around each chip is created to have a half of the set scribe width actually necessary for dicing, with respect to the reticle layout data of the plurality of types of semiconductor chips. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a reticle layout data creation method and a reticle layout data creation apparatus.

  Conventionally, a plurality of semiconductor chips are formed on a single semiconductor substrate (wafer). For this reason, in the process step of manufacturing a semiconductor chip, the wafer is exposed by a step-and-repeat method using a stepper (exposure apparatus). As shown in FIG. 6, the step-and-repeat method includes mounting a reticle 60 on a stepper (not shown), sequentially moving to a predetermined shot position, and performing exposure processing on the wafer, and exposing patterns 61a to 61d on the wafer. Are sequentially exposed.

  The exposure patterns 61a to 61d are based on layout data of circuits mounted on the semiconductor chip. Since the exposure patterns 61a to 61d are different for each process step, a plurality of reticles 60 are required. Then, process processing is performed based on the exposure patterns 61a to 61d exposed on the wafer, and semiconductor elements, wirings, electrodes, and the like constituting a circuit mounted on the semiconductor chip are formed on the wafer. A plurality of semiconductor chips formed on the wafer are divided into individual semiconductor chips by cutting with a dicing blade.

  Incidentally, with the recent miniaturization of semiconductor chips, the manufacturing cost of reticles has increased. For this reason, conventionally, in order to reduce the manufacturing cost of a semiconductor chip, the width (scribe width) of a region (scribe region) for cutting a wafer with a dicing blade is narrowed to obtain a semiconductor chip that can be obtained from one wafer. The number is increased (see Patent Document 1).

  More specifically, as shown in FIG. 7, in the regions (reticle regions) 70 a to 70 d exposed by one exposure with a single reticle (not shown), the first scribe width 71 is formed on the dicing blade. The minimum distance that can be cut. Further, the second scribe width 72 between the semiconductor chips of the different adjacent reticle regions 70a to 70d has a width that can form an alignment mark for positioning. The second scribe width 72 is wider than the first scribe width 71.

Accordingly, the number of semiconductor chips that can be obtained from one wafer increases as the first scribe width 71 of the reticle regions 70a to 70d decreases. Thereby, the manufacturing cost per semiconductor chip is reduced.
JP 2006-140294 A

  By the way, in the trial production stage of a semiconductor chip, since only the number necessary for characteristic evaluation is generally manufactured, the number of semiconductor chips to be manufactured is small. For this reason, in the trial production stage of a semiconductor chip, a plurality of types of semiconductor chips are simultaneously formed on one wafer, and the manufacturing cost of the reticle and the wafer is reduced among the manufacturing costs of the semiconductor chip.

  However, when a plurality of types of semiconductor chips are simultaneously formed on one wafer, the scribe width of each semiconductor chip may be different. In the case where the scribe widths are different, conventionally, the scribe width is created by making the first scribe width 71 and the second scribe width 72 constant in the same row direction or column direction scribe width. Therefore, since it is necessary to make the first scribe width 71 and the second scribe width 72 constant in the same scribe width in the row direction or the column direction, a semiconductor chip with a wide scribe width is a scribe width of a semiconductor chip with a narrow scribe width. To match.

  However, when a plurality of semiconductor chips having different scribe widths are simultaneously formed on one wafer according to the scribe width of a semiconductor chip having a narrow scribe width as described above, the cost of cutting the wafer with a dicing blade (dicing cost) ) Becomes higher.

  That is, when the scribe width is different, the dicing blade to be used is different, and as the scribe width is narrow, an expensive dicing blade that is thin and highly accurate has to be used. In addition, when the scribe width is narrowed, it is sometimes necessary to first dig a groove in the wafer with a laser and then cut with a dicing blade.

  An object of the reticle layout data creation method and reticle layout data creation apparatus is to be able to create reticle layout data having different scribe widths according to semiconductor chips.

  In this reticle layout data creation method, in a reticle used in an exposure process for forming a plurality of types of semiconductor chips on a semiconductor substrate, a chip region in which the reticle layout data of each semiconductor chip is partitioned and arranged in a grid pattern; A reticle layout data creation method for creating a reticle layout data of a reticle having an outer periphery scribe area arranged on an outer periphery of the chip area, and for actually dicing the reticle layout data of the plurality of types of semiconductor chips. Each of the necessary scribe widths and a half width of the scribe width actually required for dicing are arranged on the outer periphery of the reticle layout data of the plurality of types of semiconductor chips. Chip scribe area It was to have a process to create, respectively.

  According to this reticle layout data creation method, the scribe width of the chip scribe area can be made different. Thereby, a plurality of semiconductor chips having different scribe widths can be mounted on one wafer. And according to the dicing conditions of the semiconductor chip mounted on one wafer, a wafer can be cut | disconnected and a semiconductor chip can be acquired.

  The disclosed reticle layout data creation method and reticle layout data creation apparatus can create reticle layout data having different scribe widths according to semiconductor chips.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS.
FIG. 1 shows a reticle layout data creation device 10. The reticle layout data creation device 10 includes an input device 11, a processing device 12, a display device 13, and first and second storage devices 14a and 14b. The input device 11 is used to instruct the processing device 12 to perform processing operations described later. The display device 13 displays the reticle layout data created by the processing device 12 as a figure. The processing device 12 is connected to the first and second storage devices 14a and 14b.

  The first storage device 14a stores circuit layout data, a processing program, and reticle design information for a circuit mounted on a semiconductor chip. The processing program is a program for creating reticle layout data. Reticle design information includes mark placement constraint conditions such as marks (dicing target marks) when cutting semiconductor chips placed in the scribe area, and scribe widths (dicing conditions) for each dicing blade (dicing conditions) used when cutting the wafer. Scribe creation conditions).

  In the present embodiment, the scribe creation conditions include four conditions of technologies “1” to “4”. Incidentally, the technology “1” has a scribe width of 100 μm, the technology “2” has a scribe width of 200 μm, the technology “3” has a 300 μm, and the technology “4” has a 400 μm.

  The first storage device 14a stores library data. This library data includes dicing target mark layout data. Then, the processing device 12 reads various data from the first storage device 14a as necessary.

  The second storage device 14b temporarily stores data created during the process of creating reticle layout data. The second storage device 14b includes a specification data table, and stores specification data of the semiconductor chip mounted on the reticle. The specification data includes the chip name, center coordinates, and dicing conditions. Then, the processing device 12 stores or reads various data stored from the second storage device 14b as necessary.

Next, a schematic structure of reticle layout data created by the reticle layout data creation apparatus 10 will be described.
FIG. 2 is a schematic configuration diagram for explaining reticle layout data.

As shown in FIG. 2, the entire reticle layout data 20 is composed of chip area data 21, outer periphery scribe area data 22, and shading band data 23.
The chip area data 21 is divided into arrangement areas Za to Zi surrounded by an alternate long and short dash line (chip size frame) 24 for arranging the first to ninth chip data A to I which are reticle layout data of the semiconductor chip. This is data of a region to be performed (chip region Z1). Arrangement regions Za to Zi (first to ninth chip data A to I) are divided into three rows and three columns on the lattice. The arrangement areas Za to Zi of the first to ninth chip data A to I are all the same size.

  The arrangement regions Za to Zi include first to ninth element regions Za1 to Zi1 and first to ninth chip scribe regions Za2 to Zi2, respectively. The first to ninth element regions Za1 to Zi1 are regions in which reticle layout data such as semiconductor elements, wirings, and vias for constituting a circuit mounted on a semiconductor chip are arranged in the corresponding arrangement regions Za to Zi. is there. The first to ninth chip scribe areas Za2 to Zi2 are areas that are cut by a dicing blade in the corresponding arrangement areas Za to Zi.

  Accordingly, the first to ninth chip data A to I arranged in the corresponding arrangement regions Za to Zi are the first to ninth element region data 25a to 25i specifying the first to ninth element regions Za1 to Zi1. The first to ninth chip scribe areas Za2 to Zi2 specify first to ninth chip scribe areas 26a to 26i, respectively.

  The first to ninth chip data A to I arranged in the corresponding arrangement areas Za to Zi are stored in the specification data table with dicing conditions set in advance. That is, the first, third, fifth to eighth chip data A, C, E to H are set to the technology “1”. The second chip data B is set to technology “3”. The fourth chip data D is set to technology “2”. The ninth chip data I is set to technology “4”.

  In the present embodiment, the wafer is cut by a dicing blade along the alternate long and short dash line (chip size frame) 24 between the adjacent first to ninth chip scribe areas Za2 to Zi2. At this time, the scribe width of the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i) is, for example, half of the scribe width based on the set dicing conditions. It has become.

  That is, the scribe width of the first, third, and fifth to eighth chip scribe areas Za2, Zc2, and Ze2 to Zh2 (first, third, and fifth to eighth chip scribe area data 26a, 26c, and 26e to 26h). Is 50 um. The scribe width of the second chip scribe area Zb2 (second chip scribe area data 26b) is 150 μm. Furthermore, the scribe width of the fourth chip scribe area Zd2 (fourth chip scribe area data 26d) is 100 μm. The scribe width of the ninth chip scribe area Zi2 (the ninth chip scribe area data 26i) is 200 μm.

  The outer periphery scribe area data 22 is data that designates an outer periphery scribe area Z2 cut by a dicing blade on the outer periphery of the chip area Z1. The outer peripheral scribe region Z2 is cut by a dicing blade along a one-dot chain line (chip size frame) 24 between the first to fourth and sixth to ninth chip scribe regions Za2 to Zd2 and Zf2 to Zi2 in the wafer. The

  The scribe width of the outer periphery scribe area Z2 (outer periphery scribe area data 22) is selected from the dicing conditions of the smallest scribe width among the dicing conditions of the first to ninth chip data A to I stored in the specification data table. , Has become half of its smallest scribe width. In the present embodiment, the scribe width of the outer scribe area Z2 (outer scribe area data 22) is ½ (50 um) of the scribe width (100 um) since the scribe width (100 um) of the technology “1” is the smallest. Yes.

  The shading band data 23 is a light leak between adjacent shots when a reticle layout pattern of a circuit mounted on a semiconductor chip formed on a reticle by a wafer exposure apparatus such as a stepper is transferred to a wafer by a step-and-repeat method. This is data for designating a light-shielding zone Z3 for preventing double exposure due to. The width of the shading zone area Z3 (shading zone data 23) is determined by the specifications of the stepper, and the width of the shading zone area Z3 (shading zone data 23) of this embodiment is 400 μm.

Next, a process for creating the entire reticle layout data 20 according to the present embodiment will be described.
The first to ninth element region data 25a to 25i arranged in the first to ninth element regions Za1 to Zi1 are layouts of circuits mounted on the semiconductor chip stored in the first storage device 14a by the processing device 12. Created based on data.

  Then, the processing device 12 includes the first to ninth chip scribe area data 26a of the first to ninth chip scribe areas Za2 to Zi2 constituting the entire reticle layout data 20 other than the first to ninth element area data 25a to 25i. ~ 26i, the outer periphery scribe area data 22 of the outer periphery scribe area Z2 and the light shielding band data 23 of the light shielding band area Z3 (frame data), the processing device 12 executes the processing of steps 30 to 39 shown in FIG. create.

  First, in step 30 (parameter input), the processing device 12 stores the specification data of the first to ninth chip data A to I mounted in the entire reticle layout data 20 from the input device 11 operated by the user in the second storage. The data is stored in a specification data table provided in the device 14b. Each specification data of the first to ninth chip data A to I is stored in the specification data table.

  Next, in step 31 (chip count), the processing device 12 reads the specification data of the first to ninth chip data A to I stored in the specification data table in step 30. Then, the processing device 12 counts the number of each specification data of the read first to ninth chip data A to I. That is, the processing device 12 counts the number of first to ninth chip data A to I mounted on the entire reticle layout data 20 and counts it as 9 chips.

In step 32 (read scribe creation conditions), the processing device 12 reads the scribe creation conditions stored in the first storage device 14a.
In step 33 (chip scribe data creation), the processing device 12 reads the specification data stored earliest among the specification data stored in the specification data table, and the processing after step 33 is unprocessed.

  In this embodiment, since the specification data of the first chip data A to the specification data of the ninth chip data I are stored in the specification data table in the order, the processing device 12 has the first chip data A arranged in the arrangement area Za. Read the specification data. Then, the processing device 12 selects the scribe width of the first chip scribe area Za2 corresponding to the dicing condition of the specification data of the first chip data A from the scribe creation conditions read in step 32. Then, the processing device 12 creates the first chip scribe area data 26a having the scribe width of the selected first chip scribe area Za2.

  That is, the scribe selected from the chip size frame 24 in which the first chip data A is arranged based on the scribe width 100 um corresponding to the technology “1” that is the dicing condition of the first chip data A arranged in the arrangement area Za. The first chip scribe area data 26a is created inside one half (50 um) of the width (100 um).

  In step 34 (whether there is an unprocessed chip?), The processing device 12 determines whether or not there are first to ninth chip data A to I for which the processing of steps 32 and 33 is not performed. That is, the processing device 12 determines whether or not the first to ninth chip scribe area data 26a to 26i corresponding to the number of chip data counted in step 31 have been created. If there is a chip that has not been subjected to the processing in steps 32 and 33 (YES in step 34), the process proceeds to step 32.

  That is, in the processing device 12, the first to ninth chip scribe area data 26a to 26i (first to ninth chip scribe areas Za2 to Zi2) corresponding to the number of chip data counted in step 31 are arranged in the entire reticle layout data 20. Steps 32-34 are repeated until

If there is no chip that has not performed the processing of steps 32 and 33 (NO in step 34), the processing device 12 proceeds to step 35.
In step 35 (minimum scribe width selection), the processing device 12 reads the dicing conditions of the first to ninth chip data A to I from the specification data table stored in the second storage device 14b. Then, the processing device 12 selects a dicing condition having the smallest scribe width among the dicing conditions of the read first to ninth chip data A to I. That is, the processing device 12 selects the technology “1” of the scribe width (100 μm) of the first, third, fifth to eighth chip data A, C, E to H, which is the minimum scribe width.

  In step 36 (peripheral scribe data creation), the processing device 12 creates the outer scribe area data 22 based on the scribe width (100 μm) of the technology “1” selected in step 35. In other words, the processing device 12 creates outer peripheral scribe area data 22 that is one half (50 um) of the scribe width (100 um) of the technology “1” selected in step 35 on the outer periphery of the chip area Z1 (chip area data 21). To do.

  The processing apparatus 12 temporarily stores the created first to ninth chip scribe areas Za2 to Zi2 in the first to ninth chip scribe area data 26a to 26i and the outer peripheral scribe area data 22 of the outer scribe area Z2 in the second storage device 14b. Store.

  In step 37 (shading zone data creation), the processing device 12 creates shading zone data 23 for the shading zone region Z3 having a preset width of 400 μm on the outer circumference of the outer circumference scribe region Z2 (outer circumference scribe region data 22).

  In step 38 (data synthesis), the processing device 12 reads the first to ninth chip scribe area data 26a to 26i and the outer periphery scribe area data 22 stored in the second storage device 14b in step 36. Then, the processing device 12 synthesizes the read first to ninth chip scribe area data 26a to 26i and the outer periphery scribe area data 22 with the shading band data 23 created in step 37 to create frame data.

In step 39 (layout data output), the processing device 12 outputs the frame data created in step 38 and ends the processing operation.
The following effects can be obtained with a wafer created using the reticle created by the reticle layout data creation apparatus 10 as described above.
(1) The scribe widths of the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i) can be set to different widths. Thereby, a plurality of semiconductor chips having different scribe widths can be mounted on one wafer. And according to the dicing conditions of the semiconductor chip mounted on one wafer, a wafer can be cut | disconnected and a semiconductor chip can be acquired.

  That is, a dicing apparatus that cuts a wafer with a dicing blade cuts the wafer and acquires semiconductor chips based on the first to ninth chip scribe area data 26a to 26i and the outer peripheral scribe area data 22. Conventionally, since the scribe width in the column direction or the row direction is constant, the dicing condition is limited to one type. In the present embodiment, the scribe width is set to a width according to the dicing conditions of the semiconductor chip. Thus, the wafer is cut under the dicing condition with the minimum scribe width of the semiconductor chip to be acquired.

  Therefore, when acquiring only semiconductor chips with dicing conditions with a wide scribe width, it is not necessary to match the semiconductor chips with dicing conditions with a narrow scribe width, and the wafer can be cut at low cost.

  That is, when acquiring a semiconductor chip created based on the ninth chip data I (technology “4” scribe width 400 μm) shown in FIG. 2, created based on the other first to eighth chip data A to H. When the obtained semiconductor chip is not acquired, the wafer may be cut under the dicing condition of technology “4”, and the wafer can be cut at low cost.

(Second Embodiment)
A second embodiment embodying the present invention will be described below with reference to FIGS. In the first embodiment, the processing device 12 creates frame data. In the second embodiment, a dicing target mark is provided for the frame data created in the first embodiment. Therefore, only the difference will be described for convenience of explanation.

FIG. 4 is a schematic configuration diagram for explaining the entire reticle layout data 20a.
For the description of the target mark arrangement method, the fourth chip data is set to technology “1”.

  As shown in FIG. 4, the entire reticle layout data 20 a includes first and second dicing target marks 41 and 42. The first dicing target mark 41 is different from the adjacent scribe width of the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i) and the outer scribe area Z2 (outer scribe area). In the adjacent scribe areas Za2 to Zd2 and Ze2 to Zi2 (first to fourth and sixth to ninth chip scribe area data 26a to 26d and 26f to 26i) of the data 22), step-and-repeat shown in FIG. The scribe areas where adjacent relations occur during the wafer exposure by the method (between scribe areas) are arranged at different scribe widths. For example, the ninth chip scribe area Zi2 (the ninth chip scribe area data 26i) of the scribe area that is adjacent to the seventh chip scribe area Zg2 (the seventh chip scribe area data 26g) during the wafer exposure by the step-and-repeat method. The scribe widths are arranged at different locations and become marks when the wafer is cut. Then, the first dicing target mark 41 has a peripheral scribe area Z2 that is different from the adjacent scribe widths of the adjacent first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i). In the case of the adjacent scribe areas Za2 to Zd2 and Ze2 to Zi2 (first to fourth and sixth to ninth chip scribe area data 26a to 26d and 26f to 26i) of the (peripheral scribe area data 22), FIG. The chip size frames 24 are arranged at both ends of one side of the scribe areas where the adjacent relations occur between the scribe areas (between the scribe areas) in the wafer exposure by the step-and-repeat method shown.

  The adjacent scribe widths of the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i) are adjacent to the peripheral scribe area Z2 (external scribe area data 22). In the case of scribe areas Za2 to Zd2 and Ze2 to Zi2 (first to fourth and sixth to ninth chip scribe area data 26a to 26d and 26f to 26i) to be performed, wafer exposure by the step-and-repeat method shown in FIG. Since the wafer can be cut even if there is no first dicing target mark 41 at a portion where the scribe width is different between the scribe regions (between the scribe regions) in which the adjacent relationship occurs, the entire reticle layout data 20a includes the first reticle layout data 20a. One dicing target mark 41 is not provided.

  The second dicing target mark 42 is arranged at a position where the arrangement areas Za to Zi (first to ninth chip data A to I) are not arranged in the chip area Z1 (chip area data 21), and cuts the wafer. It becomes a mark when doing. In the present embodiment, since the chip sizes of the placement areas Ze, Zh (fifth and eighth chip data E, H) are small, they are adjacent to the right of the placement areas Ze, Zh (fifth and eighth chip data E, H). Arrangement areas Za to Zi (first to ninth chip data A to I) are not arranged. For this reason, the second dicing target marks 42 are arranged at the four corners of the non-arranged region 50. When the first dicing target mark 41 is arranged at the four corners of the unarranged region 50, the first dicing target mark 41 is given priority and the second dicing target mark 42 is not arranged.

Next, a process for creating the entire reticle layout data 20a according to the present embodiment will be described.
As in the first embodiment, the processing device 12 performs the processing in step 30 to step 38 to create frame data including the first and second dicing target marks 41 and 42.

  In step 51 (is there a place where scribe data having different scribe widths are adjacent to each other), the processing device 12 determines whether the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26a). 26i) adjacent scribe width portions and scribe areas Za2 to Zd2 and Ze2 to Zi2 (first to fourth and sixth to ninth chip scribe area data) adjacent to the outer scribe area Z2 (outer scribe area data 22). 26a to 26d and 26f to 26i), whether or not there is a portion where the scribe width is different between scribe regions (between scribe regions) in which the adjacency relationship occurs during wafer exposure by the step-and-repeat method shown in FIG. To determine. The first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i) that are adjacent to each other at different scribe widths and the outer scribe area Z2 (outer scribe area data 22) In the case of Za2 to Zd2 and Ze to Zi2 (first to fourth and sixth to nine-chip 9 chip scribe area data 26a to 26d and 26f to 26i), during the wafer exposure by the step-and-repeat method shown in FIG. If there is a portion where the scribe width differs between the scribe regions where the adjacent relationship occurs (between scribe regions) (YES in step 51), the process proceeds to step 52.

  In step 52 (first dicing target mark arrangement), the processing apparatus 12 determines in step 51 that the adjacent scribe widths of the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i). Are different from each other, the scribe areas Za2 to Zd2 and Ze2 to Zi2 (first to fourth and sixth to ninth chip scribe area data 26a to 26d and 26f to 26i) adjacent to the outer scribe area Z2 (outer scribe area data 22). In this case, the scribing areas that are adjacent to each other (between the scribing areas) in the wafer exposure by the step-and-repeat method shown in FIG. At both ends of one side of the chip size frame 24, a first dicing machine After placing the Ttomaku 41, the process proceeds to step 53.

  On the other hand, the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i) are adjacent to adjacent portions having different scribe widths and the outer periphery scribe area Z2 (outer periphery scribe area data 22). In the case of the scribe areas Za2 to Zd2 and Ze2 to Zi2 (first to fourth and sixth to ninth chip scribe area data 26a to 26d and 26f to 26i), the wafer exposure by the step-and-repeat method shown in FIG. If there is no portion where the scribe width differs between the scribe areas (between the scribe areas) in which the adjacent relationship occurs (NO in step 51), the process proceeds to step 53.

  In step 53 (is there an area in which chip data is not arranged?), The processing device 12 in the chip area Z1 (chip area data 21), the arrangement areas Za to Zi (first to ninth chip data A to It is determined whether there is an area where I) is not yet arranged. When there is an area in which the arrangement areas Za to Zi (first to ninth chip data A to I) are not arranged in the chip area Z1 (chip area data 21) (YES in step 53), step 54 is performed. Migrate to

  In step 54 (second dicing target mark arrangement), the processing apparatus 12 is an area in which arrangement areas Za to Zi (first to ninth chip data A to I) are not arranged in the chip area Z1 (chip area data 21). After the second dicing target marks 42 are arranged at the four corners of 50, the process proceeds to step 55.

  On the other hand, in the chip area Z1 (chip area data 21), if there is no area where the arrangement areas Za to Zi (first to ninth chip data A to I) are not arranged (NO in step 53), the process proceeds to step 55. Transition.

In step 55 (reticle layout data output), the processing device 12 outputs frame data.
The following effects can be obtained with a wafer created using the reticle created by the reticle layout data creation apparatus 10 as described above.

  (1) The first dicing target mark 41 can be arranged in the entire reticle layout data 20a. As a result, when a plurality of semiconductor chips having different scribe widths are mounted on one wafer, the wafers can be cut with high precision at locations where adjacent semiconductor chips have different scribe widths.

That is, the dicing apparatus cuts the wafer along the center of the scribe width based on the first to ninth chip scribe area data 26a to 26i and the outer periphery scribe area data 22. When the scribe widths of adjacent semiconductor chips are different, when the wafer is cut along the center of the scribe width, regions (scribe regions) where the wafer is cut by a dicing blade are first to ninth element regions Za1 to Zi1 (first To the ninth element region data 25a to 25i), the first to ninth element regions Za1 to Zi1 (first to ninth element region data 25a to 25i) may be cut. In this case, by disposing the first dicing target mark 41 on the chip size frame, the wafer is cut along the chip size frame between adjacent semiconductor chips.
(2) The second dicing target mark 42 can be arranged in the entire reticle layout data 20a. As a result, when a plurality of semiconductor chips having different scribe widths are mounted on one wafer, the arrangement regions Za to Zi (first to ninth chip data A to I) in the chip region Z1 (chip region data 21) are not yet completed. It is possible to cut the wafer in the arrangement region 50 with high accuracy.

  That is, in the area 50 in which the arrangement areas Za to Zi (first to ninth chip data A to I) in the chip area Z1 (chip area data 21) are not arranged, the first to ninth chip scribe areas Za2 to Zi2 are arranged. Since there is no (first to ninth chip scribe area data 26a to 26i) and outer periphery scribe area Z2 (outer periphery scribe area data 22), the dicing apparatus does not cut the unarranged area 50. For this reason, by arrange | positioning the 2nd dicing target mark 42 in the area | region 50 in which arrangement | positioning area | region Za-Zi (1st-9th chip data A-I) in chip | tip area | region Z1 (chip area | region data 21) is not arranged, The unarranged region 50 is cut.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, the outer periphery scribe area Z2 (outer periphery scribe area data 22) is the dicing condition of the smallest scribe width among the dicing conditions of the first to ninth chip data A to I stored in the specification data table. Select and have become half of its minimum scribe width. However, the present invention is not limited to this, and dicing conditions for other scribe widths may be selected and ½ of the scribe width.

  In the above embodiment, the first to ninth chip scribe areas Za2 to Zi2 (first to ninth chip scribe area data 26a to 26i) are each half of the scribe width based on the set dicing conditions. ing. However, the scribe width may be narrower than a half of the scribe width based on the set dicing conditions.

It is a schematic block diagram of a reticle layout data creation device. It is explanatory drawing of the reticle layout data of 1st embodiment. It is a flowchart of the reticle layout data creation processing of the first embodiment. It is explanatory drawing of the reticle layout data of 2nd embodiment. It is a flowchart of the reticle layout data creation processing of the second embodiment. It is explanatory drawing which shows a step and repeat operation | movement. It is explanatory drawing of the conventional reticle layout data.

Explanation of symbols

20, 20a Reticle layout data Za2 to Zi2 Chip scribe area Z2 Peripheral scribe area 41, 42 Dicing target mark A to I Semiconductor chip reticle layout data 50 Unallocated area

Claims (6)

In a reticle used in an exposure process for forming a plurality of types of semiconductor chips on a semiconductor substrate, the reticle layout data of each semiconductor chip is arranged in a grid pattern, and arranged on the outer periphery of the chip area A reticle layout data creation method for creating reticle layout data of a reticle having an outer peripheral scribe area,
A step of setting a scribe width for reticle layout data of the plurality of types of semiconductor chips,
A reticle layout data having a width smaller than the set scribe width, and creating a chip scribe area arranged on the outer periphery of the plurality of types of semiconductor chip reticle layout data. How to make. In the reticle layout data creation method according to claim 1,
Selecting the smallest scribe width among the set scribe widths;
And a step of setting the width of the outer periphery scribe region by a width that is a half of the selected smallest scribe width and generating the outer periphery scribe region. In the reticle layout data creation method according to claim 1,
A step of determining whether or not there is a portion where the width of the chip scribe region is different in a portion where the reticle layout data of the plurality of types of semiconductor chips is adjacent;
In the determination, if there is a portion where the width of the chip scribe region is different in a portion where the reticle layout data of the plurality of types of semiconductor chips are adjacent, the portion where the width of the chip scribe region is different is dicing. And a step of placing a reference dicing target mark on the reticle layout data. In the reticle layout data creation method according to claim 1,
Determining whether there is an area where reticle layout data of the plurality of types of semiconductor chips is not arranged in the chip area;
In the determination, if there is a region where the reticle layout data of the plurality of types of semiconductor chips is not arranged in the chip region, dicing is performed in a region where the reticle layout data of the plurality of types of semiconductor chips is not arranged. And a step of arranging a dicing target mark serving as a reference when the reticle layout data is created. In the reticle layout data creation method according to claim 1,
The reticle layout data creation method, wherein the chip scribe area is created with a width that is a half of the set scribe width. In a reticle used in an exposure process for forming a plurality of types of semiconductor chips on a semiconductor substrate, the reticle layout data of each semiconductor chip is arranged in a grid pattern, and arranged on the outer periphery of the chip area A reticle layout data creation device for creating reticle layout data of a reticle having an outer peripheral scribe area,
Means for respectively setting a scribe width for reticle layout data of the plurality of types of semiconductor chips;
Means for creating chip scribe areas arranged on the outer periphery of the reticle layout data of the plurality of types of semiconductor chips, each having a width that is a half of the set scribe width. Layout data creation device.

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