JP4466057B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4466057B2 JP4466057B2 JP2003402907A JP2003402907A JP4466057B2 JP 4466057 B2 JP4466057 B2 JP 4466057B2 JP 2003402907 A JP2003402907 A JP 2003402907A JP 2003402907 A JP2003402907 A JP 2003402907A JP 4466057 B2 JP4466057 B2 JP 4466057B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- filler
- resin
- semiconductor device
- mold resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000011347 resin Substances 0.000 claims description 36
- 229920005989 resin Polymers 0.000 claims description 36
- 239000000945 filler Substances 0.000 claims description 27
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 2
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図4は、他の実施形態を示す概略断面図である。この例は、上記突起物15に替えて発泡樹脂を採用して、同様の効果をねらったものである。
40…モールド樹脂、41…フィラー。
Claims (2)
- ICチップ(10)をフィラー(41)を含有するモールド樹脂(40)により包み込むように封止してなる半導体装置において、
前記ICチップ(10)における前記モールド樹脂(40)と接する表面(11)は、当該表面(11)より突出するとともに、前記モールド樹脂(40)に含有される前記フィラー(41)の最小径よりも小さい間隔で配列された樹脂製円柱状の突起物(15)により被覆されており、
前記フィラー(41)の最小径は、数μm〜10μmであることを特徴とする半導体装置。 - 前記ICチップ(10)の前記表面(11)には保護膜(13)が設けられていることを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003402907A JP4466057B2 (ja) | 2003-12-02 | 2003-12-02 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003402907A JP4466057B2 (ja) | 2003-12-02 | 2003-12-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005166898A JP2005166898A (ja) | 2005-06-23 |
JP4466057B2 true JP4466057B2 (ja) | 2010-05-26 |
Family
ID=34726354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003402907A Expired - Lifetime JP4466057B2 (ja) | 2003-12-02 | 2003-12-02 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4466057B2 (ja) |
-
2003
- 2003-12-02 JP JP2003402907A patent/JP4466057B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2005166898A (ja) | 2005-06-23 |
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