JP4456154B2 - キャッシュメモリの動的再設定 - Google Patents

キャッシュメモリの動的再設定 Download PDF

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Publication number
JP4456154B2
JP4456154B2 JP2007534653A JP2007534653A JP4456154B2 JP 4456154 B2 JP4456154 B2 JP 4456154B2 JP 2007534653 A JP2007534653 A JP 2007534653A JP 2007534653 A JP2007534653 A JP 2007534653A JP 4456154 B2 JP4456154 B2 JP 4456154B2
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cache memory
cache
current
predetermined
processor
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Expired - Fee Related
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JP2007534653A
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Japanese (ja)
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JP2008515095A5 (https=
JP2008515095A (ja
Inventor
エル． ゴールデン マイケル
イー． クラス リチャード
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/27—Using a specific cache architecture
    • G06F2212/271—Non-uniform cache access [NUCA] architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
JP2007534653A 2004-10-01 2005-09-21 キャッシュメモリの動的再設定 Expired - Fee Related JP4456154B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/956,560 US7257678B2 (en) 2004-10-01 2004-10-01 Dynamic reconfiguration of cache memory
PCT/US2005/033671 WO2006039153A1 (en) 2004-10-01 2005-09-21 Dynamic reconfiguration of cache memory

Publications (3)

Publication Number Publication Date
JP2008515095A JP2008515095A (ja) 2008-05-08
JP2008515095A5 JP2008515095A5 (https=) 2008-11-13
JP4456154B2 true JP4456154B2 (ja) 2010-04-28

Family

ID=35519765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007534653A Expired - Fee Related JP4456154B2 (ja) 2004-10-01 2005-09-21 キャッシュメモリの動的再設定

Country Status (8)

Country Link
US (1) US7257678B2 (https=)
JP (1) JP4456154B2 (https=)
KR (1) KR101136141B1 (https=)
CN (1) CN101048763B (https=)
DE (1) DE112005002672B4 (https=)
GB (1) GB2432695B (https=)
TW (1) TWI403899B (https=)
WO (1) WO2006039153A1 (https=)

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US8327126B2 (en) * 2008-08-25 2012-12-04 International Business Machines Corporation Multicore processor and method of use that adapts core functions based on workload execution
US8271728B2 (en) * 2008-11-13 2012-09-18 International Business Machines Corporation Spiral cache power management, adaptive sizing and interface operations
US8195887B2 (en) * 2009-01-21 2012-06-05 Globalfoundries Inc. Processor power management and method
US8103894B2 (en) * 2009-04-24 2012-01-24 International Business Machines Corporation Power conservation in vertically-striped NUCA caches
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US8438410B2 (en) * 2010-06-23 2013-05-07 Intel Corporation Memory power management via dynamic memory operation states
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US8711633B2 (en) * 2011-05-12 2014-04-29 Micron Technology, Inc. Dynamic data caches, decoders and decoding methods
JP5820336B2 (ja) 2011-05-20 2015-11-24 株式会社半導体エネルギー研究所 半導体装置
JP5820335B2 (ja) 2011-05-20 2015-11-24 株式会社半導体エネルギー研究所 半導体装置
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JP6012263B2 (ja) 2011-06-09 2016-10-25 株式会社半導体エネルギー研究所 半導体記憶装置
US8595464B2 (en) * 2011-07-14 2013-11-26 Oracle International Corporation Dynamic sizing of translation lookaside buffer for power reduction
US8868843B2 (en) 2011-11-30 2014-10-21 Advanced Micro Devices, Inc. Hardware filter for tracking block presence in large caches
US20130138884A1 (en) * 2011-11-30 2013-05-30 Hitachi, Ltd. Load distribution system
CN103246542B (zh) * 2012-02-01 2017-11-14 中兴通讯股份有限公司 智能缓存及智能终端
US9135182B2 (en) 2012-06-01 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Central processing unit and driving method thereof
US20140136793A1 (en) * 2012-11-13 2014-05-15 Nvidia Corporation System and method for reduced cache mode
US9360924B2 (en) 2013-05-29 2016-06-07 Intel Corporation Reduced power mode of a cache unit
US9568986B2 (en) 2013-09-25 2017-02-14 International Business Machines Corporation System-wide power conservation using memory cache
JP6474280B2 (ja) 2014-03-05 2019-02-27 株式会社半導体エネルギー研究所 半導体装置
EP3055774B1 (en) * 2014-12-14 2019-07-17 VIA Alliance Semiconductor Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode
JP6218971B2 (ja) 2014-12-14 2017-10-25 ヴィア アライアンス セミコンダクター カンパニー リミテッド アドレス・タグ・ビットに基づく動的キャッシュ置換ウェイ選択
US9798668B2 (en) 2014-12-14 2017-10-24 Via Alliance Semiconductor Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
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JP6405331B2 (ja) * 2016-03-22 2018-10-17 日本電信電話株式会社 キャッシュ管理システム、評価方法、管理サーバ、物理サーバ、および、測定サーバ
JP6511023B2 (ja) * 2016-08-22 2019-05-08 日本電信電話株式会社 仮想マシン管理装置およびデプロイ可否判断方法
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Also Published As

Publication number Publication date
WO2006039153A1 (en) 2006-04-13
DE112005002672T5 (de) 2007-11-29
US7257678B2 (en) 2007-08-14
GB0705275D0 (en) 2007-04-25
KR20070054715A (ko) 2007-05-29
KR101136141B1 (ko) 2012-04-17
DE112005002672B4 (de) 2010-12-02
US20060075192A1 (en) 2006-04-06
CN101048763B (zh) 2012-05-23
JP2008515095A (ja) 2008-05-08
TW200627148A (en) 2006-08-01
GB2432695B (en) 2008-07-09
TWI403899B (zh) 2013-08-01
GB2432695A (en) 2007-05-30
CN101048763A (zh) 2007-10-03

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