CN101048763B - 一种配置处理器的高速缓冲存储器的方法与处理器 - Google Patents

一种配置处理器的高速缓冲存储器的方法与处理器 Download PDF

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Publication number
CN101048763B
CN101048763B CN2005800330956A CN200580033095A CN101048763B CN 101048763 B CN101048763 B CN 101048763B CN 2005800330956 A CN2005800330956 A CN 2005800330956A CN 200580033095 A CN200580033095 A CN 200580033095A CN 101048763 B CN101048763 B CN 101048763B
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cache
use amount
cache memory
numerical value
memory
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Chinese (zh)
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CN101048763A (zh
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M·L·戈尔登
R·E·克拉斯
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MediaTek Inc
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GlobalFoundries Inc
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/126Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1028Power efficiency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/27Using a specific cache architecture
    • G06F2212/271Non-uniform cache access [NUCA] architecture
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
CN2005800330956A 2004-10-01 2005-09-21 一种配置处理器的高速缓冲存储器的方法与处理器 Expired - Lifetime CN101048763B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/956,560 2004-10-01
US10/956,560 US7257678B2 (en) 2004-10-01 2004-10-01 Dynamic reconfiguration of cache memory
PCT/US2005/033671 WO2006039153A1 (en) 2004-10-01 2005-09-21 Dynamic reconfiguration of cache memory

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CN101048763A CN101048763A (zh) 2007-10-03
CN101048763B true CN101048763B (zh) 2012-05-23

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Country Link
US (1) US7257678B2 (https=)
JP (1) JP4456154B2 (https=)
KR (1) KR101136141B1 (https=)
CN (1) CN101048763B (https=)
DE (1) DE112005002672B4 (https=)
GB (1) GB2432695B (https=)
TW (1) TWI403899B (https=)
WO (1) WO2006039153A1 (https=)

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JP5820335B2 (ja) 2011-05-20 2015-11-24 株式会社半導体エネルギー研究所 半導体装置
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JP6012263B2 (ja) 2011-06-09 2016-10-25 株式会社半導体エネルギー研究所 半導体記憶装置
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US9135182B2 (en) 2012-06-01 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Central processing unit and driving method thereof
US20140136793A1 (en) * 2012-11-13 2014-05-15 Nvidia Corporation System and method for reduced cache mode
US9360924B2 (en) 2013-05-29 2016-06-07 Intel Corporation Reduced power mode of a cache unit
US9568986B2 (en) 2013-09-25 2017-02-14 International Business Machines Corporation System-wide power conservation using memory cache
JP6474280B2 (ja) 2014-03-05 2019-02-27 株式会社半導体エネルギー研究所 半導体装置
EP3055774B1 (en) * 2014-12-14 2019-07-17 VIA Alliance Semiconductor Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode
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Also Published As

Publication number Publication date
WO2006039153A1 (en) 2006-04-13
DE112005002672T5 (de) 2007-11-29
US7257678B2 (en) 2007-08-14
GB0705275D0 (en) 2007-04-25
KR20070054715A (ko) 2007-05-29
KR101136141B1 (ko) 2012-04-17
DE112005002672B4 (de) 2010-12-02
US20060075192A1 (en) 2006-04-06
JP2008515095A (ja) 2008-05-08
TW200627148A (en) 2006-08-01
GB2432695B (en) 2008-07-09
TWI403899B (zh) 2013-08-01
JP4456154B2 (ja) 2010-04-28
GB2432695A (en) 2007-05-30
CN101048763A (zh) 2007-10-03

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