JP4456066B2 - 電子メモリを備えたアクティブセキュリティデバイス - Google Patents
電子メモリを備えたアクティブセキュリティデバイス Download PDFInfo
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- JP4456066B2 JP4456066B2 JP2005375135A JP2005375135A JP4456066B2 JP 4456066 B2 JP4456066 B2 JP 4456066B2 JP 2005375135 A JP2005375135 A JP 2005375135A JP 2005375135 A JP2005375135 A JP 2005375135A JP 4456066 B2 JP4456066 B2 JP 4456066B2
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- G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
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Description
・通電されているとき、情報の消失をもたらす短絡を生じさせることなく、構成部品のケーシングからいかにして樹脂を除去するか、
・構成部品の正確な系統図、
・メモリの「スクランブリング」テーブル、
・メモリプレーン中の秘密のアドレス、および、
・アドレスバスおよびデータバスのリアルタイムでの書込みおよび読取りを行なう正しい方法、
が知られていても、情報へのアクセスが全体として不可能である。
図1のセキュリティデバイスは、次のように作動する。
電気的接続が、簡単な接触、接着またはインジウムボールを用いたロウ付けにより内部で確保されているならば、接触を破壊することなく2つの集積回路を分離することは不可能である。
Claims (16)
- 秘密情報を収納したセキュリティデバイスであって、
前記情報を受け入れるメモリ領域を備えた集積回路と、
探索に対する防護を形成すべく少なくとも前記メモリ領域を覆いかつ該メモリ領域に固定される保護手段と、
前記秘密情報に対するアクセスを防止するアクセス防止手段とを備え、
前記保護手段には少なくとも第2集積回路(2)が含まれており、前記集積回路と第2集積回路との相互作用接続手段(9、9′)と、少なくとも前記集積回路内に設けられた少なくとも第2集積回路を認証する認証手段とを有することを特徴とし、少なくとも前記第2集積回路の認証がなされないときに前記アクセス防止手段によりメモリ領域の前記秘密情報を破壊するよう設計されているセキュリティデバイス。 - 前記認証手段はダイナミックセッション秘密鍵を用いる手順を使用していることを特徴とする請求項1に記載のセキュリティデバイス。
- 前記集積回路は互いに並べて配置されかつこれらの集積回路を互いに接続する外部電気接続部(9)を有していることを特徴とする請求項1又は2に記載のセキュリティデバイス。
- 前記集積回路は面対面構造に配置されかつこれらの集積回路を互いに接続する内部電気接続部(9′)を有していることを特徴とする請求項1又は2に記載のセキュリティデバイス。
- 前記集積回路は面対面構造に配置された電気接続部(8、8′)を有していることを特徴とする請求項4に記載のセキュリティデバイス。
- 前記集積回路はロウ付けにより接続されていることを特徴とする請求項5に記載のセキュリティデバイス。
- 前記接続は導電性接着剤により行なわれることを特徴とする請求項5に記載のセキュリティデバイス。
- 前記集積回路は面対面構造に配置されかつ電磁的または容量的な内部接続部を有していることを特徴とする請求項1又は2に記載のセキュリティデバイス。
- 同一接続部が第1集積回路に給電しかつデータを伝達することを特徴とする請求項8に記載のセキュリティデバイス。
- 前記集積回路の接続部が集積回路のそれぞれの接触面の中央領域にあることを特徴とする請求項4乃至9のうちいずれか1項に記載のセキュリティデバイス。
- 前記集積回路が接着剤の層(7)により一体に固定されていることを特徴とする請求項1乃至10のうちいずれか1項に記載のセキュリティデバイス。
- 前記集積回路の固定および電気的接続が導電性接着剤により行なわれることを特徴とする請求項7乃至11のうちいずれか1項に記載のセキュリティデバイス。
- 前記第2集積回路が更にメモリ領域(6′)を有し、前記電子回路には双方向認証手段が設けられていることを特徴とする請求項1乃至12のうちいずれか1項に記載のセキュリティデバイス。
- 少なくとも1つの集積回路が、秘密情報を収納するRAMを有していることを特徴とする請求項1乃至13のうちいずれか1項に記載のセキュリティデバイス。
- 各集積回路が、秘密情報を得ることができる他の集積回路の回路要素(6、6′)を覆っていることを特徴とする請求項1乃至14のうちいずれか1項に記載のセキュリティデバイス。
- 前記第1集積回路または第2集積回路への給電が内部電気接続部(9′)を介して行なわれることを特徴とする請求項4に記載のセキュリティデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9413886A FR2727226B1 (fr) | 1994-11-17 | 1994-11-17 | Dispositif de securite actif a memoire electronique |
FR9502796A FR2727227B1 (fr) | 1994-11-17 | 1995-03-08 | Dispositif de securite actif a memoire electronique |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51661296A Division JP4278176B2 (ja) | 1994-11-17 | 1995-11-15 | 電子メモリを備えたアクティブセキュリティデバイス |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006216020A JP2006216020A (ja) | 2006-08-17 |
JP4456066B2 true JP4456066B2 (ja) | 2010-04-28 |
Family
ID=26231546
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51661296A Expired - Fee Related JP4278176B2 (ja) | 1994-11-17 | 1995-11-15 | 電子メモリを備えたアクティブセキュリティデバイス |
JP2005375135A Expired - Fee Related JP4456066B2 (ja) | 1994-11-17 | 2005-12-27 | 電子メモリを備えたアクティブセキュリティデバイス |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51661296A Expired - Fee Related JP4278176B2 (ja) | 1994-11-17 | 1995-11-15 | 電子メモリを備えたアクティブセキュリティデバイス |
Country Status (7)
Country | Link |
---|---|
US (1) | US5877547A (ja) |
EP (1) | EP0792497B1 (ja) |
JP (2) | JP4278176B2 (ja) |
DE (1) | DE69504208T2 (ja) |
ES (1) | ES2122702T3 (ja) |
FR (1) | FR2727227B1 (ja) |
WO (1) | WO1996016378A1 (ja) |
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FR2784768A1 (fr) * | 1998-10-16 | 2000-04-21 | Schlumberger Ind Sa | Puce a circuits integres securisee contre l'action de rayonnements electromagnetiques |
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DE19957120A1 (de) * | 1999-11-26 | 2001-05-31 | Infineon Technologies Ag | Vertikal integrierte Schaltungsanordnung und Verfahren zum Betreiben einer vertikal integrierten Schaltungsanordnung |
JP3553457B2 (ja) * | 2000-03-31 | 2004-08-11 | シャープ株式会社 | 半導体装置およびその製造方法 |
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-
1995
- 1995-03-08 FR FR9502796A patent/FR2727227B1/fr not_active Expired - Fee Related
- 1995-11-15 DE DE69504208T patent/DE69504208T2/de not_active Expired - Lifetime
- 1995-11-15 EP EP95940311A patent/EP0792497B1/fr not_active Expired - Lifetime
- 1995-11-15 US US08/836,563 patent/US5877547A/en not_active Expired - Lifetime
- 1995-11-15 ES ES95940311T patent/ES2122702T3/es not_active Expired - Lifetime
- 1995-11-15 JP JP51661296A patent/JP4278176B2/ja not_active Expired - Fee Related
- 1995-11-15 WO PCT/FR1995/001497 patent/WO1996016378A1/fr active IP Right Grant
-
2005
- 2005-12-27 JP JP2005375135A patent/JP4456066B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO1996016378A1 (fr) | 1996-05-30 |
EP0792497A1 (fr) | 1997-09-03 |
DE69504208D1 (de) | 1998-09-24 |
FR2727227B1 (fr) | 1996-12-20 |
EP0792497B1 (fr) | 1998-08-19 |
DE69504208T2 (de) | 1999-04-29 |
US5877547A (en) | 1999-03-02 |
JP2006216020A (ja) | 2006-08-17 |
JP4278176B2 (ja) | 2009-06-10 |
ES2122702T3 (es) | 1998-12-16 |
JPH10509260A (ja) | 1998-09-08 |
FR2727227A1 (fr) | 1996-05-24 |
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