JP4447377B2 - Insulated gate semiconductor device and manufacturing method thereof - Google Patents

Insulated gate semiconductor device and manufacturing method thereof Download PDF

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JP4447377B2
JP4447377B2 JP2004158575A JP2004158575A JP4447377B2 JP 4447377 B2 JP4447377 B2 JP 4447377B2 JP 2004158575 A JP2004158575 A JP 2004158575A JP 2004158575 A JP2004158575 A JP 2004158575A JP 4447377 B2 JP4447377 B2 JP 4447377B2
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trench
insulating layer
semiconductor device
forming
deposited insulating
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秀史 高谷
恭輔 宮城
公守 濱田
康嗣 大倉
規仁 戸倉
晃 黒柳
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Toyota Motor Corp
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
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    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Description

本発明は，トレンチゲート構造を有する絶縁ゲート型半導体装置およびその製造方法に関する。さらに詳細には，半導体層にかかる電界を緩和することにより，高耐圧化と低オン抵抗化との両立を図った絶縁ゲート型半導体装置およびその製造方法に関するものである。   The present invention relates to an insulated gate semiconductor device having a trench gate structure and a method for manufacturing the same. More specifically, the present invention relates to an insulated gate semiconductor device that achieves both high breakdown voltage and low on-resistance by relaxing an electric field applied to a semiconductor layer, and a method for manufacturing the same.

従来から，パワーデバイス用の絶縁ゲート型半導体装置として，トレンチゲート構造を有するトレンチゲート型半導体装置が提案されている。このトレンチゲート型半導体装置では，一般的に高耐圧化と低オン抵抗化とがトレードオフの関係にある。   Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulated gate type semiconductor device for power devices. In this trench gate type semiconductor device, a high breakdown voltage and a low on-resistance are generally in a trade-off relationship.

そこで，本出願人は，トレードオフの問題を解決したトレンチゲート型半導体装置として，図３に示すような絶縁ゲート型半導体装置９００を提案している（特願２００３−３４９８０６号）。この絶縁ゲート型半導体装置９００では，Ｐ- ボディ領域４１を貫通してなるゲートトレンチ２１が設けられている。そして，ゲートトレンチ２１の底部から不純物（ボロン等）を注入することによって形成されるＰ- フローティング領域５１が設けられている。絶縁ゲート型半導体装置９００では，このＰ- フローティング領域５１により電界強度のピーク値を低減することができる。 Therefore, the present applicant has proposed an insulated gate semiconductor device 900 as shown in FIG. 3 as a trench gate semiconductor device that solves the trade-off problem (Japanese Patent Application No. 2003-349806). In this insulated gate semiconductor device 900, a gate trench 21 penetrating the P − body region 41 is provided. A P − floating region 51 formed by implanting impurities (boron or the like) from the bottom of the gate trench 21 is provided. In the insulated gate semiconductor device 900, the peak value of the electric field strength can be reduced by the P − floating region 51.

この絶縁ゲート型半導体装置９００では，ゲートトレンチ２１のようにトレンチ内部の所定の深さまで絶縁物を埋め込んだトレンチを有している。このようなトレンチを形成するためには，一旦全てのトレンチに対して絶縁物を充填し，その後にゲートトレンチ２１内に充填した絶縁物の一部を除去する工程（エッチバック）が必要となる。   The insulated gate semiconductor device 900 has a trench in which an insulator is buried to a predetermined depth inside the trench, like the gate trench 21. In order to form such a trench, a process (etchback) is required in which all the trenches are once filled with an insulator and then a part of the insulator filled in the gate trench 21 is removed. .

この絶縁物のエッチバックの際，堆積絶縁層２３の中央部分に図４に示すようなくさび状の溝８１が形成されることがある。このくさび状の溝８１が形成されてしまう主な理由は次のとおりである。ゲートトレンチ２１内の堆積絶縁層２３は，ＣＶＤ法にてゲートトレンチ２１の壁面に絶縁物を堆積させることにより形成される。そのため，堆積絶縁層２３の中央部分にはシームやボイドが生じる。そして，シームやボイドが生じている堆積絶縁膜２３に対してウェットエッチングにてエッチバックを行うと，中央部分にてエッチングが急速に進行する。これにより，堆積絶縁層２３の中央部分にくさび状の溝８１が形成されてしまうのである。   When this insulator is etched back, a wedge-shaped groove 81 may be formed in the central portion of the deposited insulating layer 23 as shown in FIG. The main reason why the wedge-shaped groove 81 is formed is as follows. The deposited insulating layer 23 in the gate trench 21 is formed by depositing an insulator on the wall surface of the gate trench 21 by the CVD method. Therefore, seams and voids are generated in the central portion of the deposited insulating layer 23. When etching back is performed by wet etching on the deposited insulating film 23 in which seams and voids are generated, the etching proceeds rapidly at the central portion. As a result, a wedge-shaped groove 81 is formed in the central portion of the deposited insulating layer 23.

さらに，くさび状の溝８１が形成された堆積絶縁層２３上にゲート電極２２を形成すると，そのくさび状の溝８１内にゲート材が進入することとなる。そして，くさび状の溝８１内にゲート材が進入すると，半導体層内の空乏層の伸び方が設計と異なってしまう。その結果，所望の電界分布が形成されず，ドレイン−ソース間の耐圧の低下を招いてしまう。   Further, when the gate electrode 22 is formed on the deposited insulating layer 23 in which the wedge-shaped groove 81 is formed, the gate material enters the wedge-shaped groove 81. When the gate material enters the wedge-shaped groove 81, the depletion layer in the semiconductor layer is extended differently from the design. As a result, a desired electric field distribution is not formed, and the breakdown voltage between the drain and the source is lowered.

そこで，堆積絶縁層内に発生するシームやボイドの影響を回避する技術が幾つか提案されている。例えば，一般的な方法として，リン添加ガラス（ＰＳＧ），ボロン・リン添加ガラス（ＢＰＳＧ）等の不純物をドープした材料を堆積絶縁層の主原料として利用する方法（例えば，特許文献１）がある。この方法は，埋め込み後の熱処理（リフロー）により，埋め込まれた酸化膜が溶融する性質を利用している。   Therefore, several techniques for avoiding the effects of seams and voids generated in the deposited insulating layer have been proposed. For example, as a general method, there is a method in which an impurity-doped material such as phosphorus-added glass (PSG) or boron-phosphorus-added glass (BPSG) is used as a main raw material for the deposited insulating layer (for example, Patent Document 1). . This method utilizes the property that the buried oxide film is melted by heat treatment (reflow) after filling.

また，この他にボイドやシームの影響を回避する技術として，例えば特許文献２に開示されている半導体装置の製造方法がある。この半導体装置の製造方法では，ドライエッチングにてエッチバックを行い，さらにドライエッチング時のエッチングガスに水素を含むガスを利用している。
特開平８−２２７９３５号公報 特開平８−２０３８７１号公報 As another technique for avoiding the influence of voids and seams, for example, there is a method for manufacturing a semiconductor device disclosed in Patent Document 2. In this semiconductor device manufacturing method, etch back is performed by dry etching, and a gas containing hydrogen is used as an etching gas at the time of dry etching.
JP-A-8-227935 JP-A-8-203871

しかしながら，前記した絶縁物の埋め込み方法には，次のような問題があった。すなわち，絶縁ゲート型半導体装置９００では，その埋め込み酸化膜がチャネル領域に隣接することとなる。そのため，ＢＰＳＧ等の不純物をドープした酸化膜を絶縁ゲート型半導体装置９００に適用する場合，リフロー時にボロン，リン等の不純物がチャネル領域となるシリコン層へ拡散し，素子特性に悪影響を与えることが懸念される。   However, the above-described method for embedding an insulator has the following problems. That is, in the insulated gate semiconductor device 900, the buried oxide film is adjacent to the channel region. Therefore, when an oxide film doped with impurities such as BPSG is applied to the insulated gate semiconductor device 900, impurities such as boron and phosphorus diffuse into the silicon layer serving as a channel region during reflow, which may adversely affect element characteristics. Concerned.

また，特許文献２に開示された技術は，あくまでドライエッチングによって生じる不具合を回避するものである。しかしながら，絶縁ゲート型半導体装置９００のようにトレンチ部の壁面にチャネル領域を設ける半導体装置では，ドライエッチングを行うことによって生じるデポ物や逆スパッタ物等を除去するための洗浄処理を行う必要がある。具体的には，ウェットエッチングを行ってトレンチ部に付着したデポ物や逆スパッタ物等を除去する必要がある。そのため，堆積絶縁層はウェットエッチングにも耐えるものである必要がある。しかし，特許文献２に開示された技術はウェットエッチングによるくさび状の溝の発生を抑制しえない。そのため，素子特性のばらつきの問題が解消するまでには至らない。   Further, the technique disclosed in Patent Document 2 avoids problems caused by dry etching. However, in a semiconductor device in which a channel region is provided on the wall surface of the trench portion, such as the insulated gate semiconductor device 900, it is necessary to perform a cleaning process to remove deposits, reverse spatters, and the like generated by dry etching. . Specifically, it is necessary to remove deposits and reverse spatters attached to the trench by wet etching. Therefore, the deposited insulating layer needs to withstand wet etching. However, the technique disclosed in Patent Document 2 cannot suppress the generation of wedge-shaped grooves due to wet etching. For this reason, the problem of variation in element characteristics cannot be solved.

本発明は，前記した従来の技術が有する問題点を解決するためになされたものである。すなわちその課題とするところは，堆積絶縁層内の膜質を改善し，堆積絶縁層内のシームやボイドの影響による素子特性の劣化を抑制した絶縁ゲート型半導体装置の製造方法を提供することにある。   The present invention has been made to solve the above-described problems of the prior art. That is, the problem is to provide a method of manufacturing an insulated gate semiconductor device that improves the film quality in the deposited insulating layer and suppresses deterioration of element characteristics due to the effects of seams and voids in the deposited insulating layer. .

この課題の解決を目的としてなされた絶縁ゲート型半導体装置の製造方法は，トレンチ型電極構造を有する絶縁ゲート型半導体装置の製造方法であって，半導体基板の上面からトレンチ部を形成するトレンチ部形成工程と，トレンチ部形成工程にてトレンチ部を形成した後に，そのトレンチ部の底部から不純物を注入する不純物注入工程と，不純物注入工程にて不純物を注入した後に，そのトレンチ部内に絶縁物の堆積による堆積絶縁層を形成する絶縁物堆積工程と，絶縁物堆積工程にて堆積絶縁層を形成した後に，堆積絶縁層の一部を除去するエッチバック工程と，エッチバック工程にて堆積絶縁層の一部を除去した後に，水素と酸素との混合気体の酸化性雰囲気中，９００℃から１０００℃の範囲内の温度にてアニール処理を行うアニール工程と，アニール工程にてアニール処理を行った後に，ウェットエッチングにて表面の酸化膜層を除去するウェットエッチング工程と，ウェットエッチング工程にて酸化膜を除去した後に，トレンチ部の壁面に沿って絶縁膜を形成する絶縁膜形成工程と，絶縁膜形成工程にて絶縁膜を形成した後に，堆積絶縁層の上面上に電極層を形成する電極層形成工程と含んでいる。 A method of manufacturing an insulated gate semiconductor device for solving this problem is a method of manufacturing an insulated gate semiconductor device having a trench electrode structure, in which a trench portion is formed from an upper surface of a semiconductor substrate. And after forming the trench portion in the trench portion forming step, an impurity implantation step for injecting impurities from the bottom of the trench portion, and after implanting the impurities in the impurity implantation step , depositing an insulator in the trench portion An insulating deposition process for forming a deposited insulating layer by etching, an etch back process for removing a portion of the deposited insulating layer after forming the deposited insulating layer in the insulator depositing process, and an after removal of the part, in an oxidizing atmosphere of a mixed gas of hydrogen and oxygen, Annie performing annealing at a temperature in the range from 900 ° C. to 1000 ° C. And after the annealing process in the annealing process, the wet etching process in which the oxide film layer on the surface is removed by wet etching, and after the oxide film is removed in the wet etching process, along the wall surface of the trench portion. An insulating film forming step for forming an insulating film and an electrode layer forming step for forming an electrode layer on the upper surface of the deposited insulating layer after forming the insulating film in the insulating film forming step are included.

本発明の絶縁ゲート型半導体装置の製造方法では，トレンチ部形成工程にてトレンチ部を形成した後に，絶縁物堆積工程にてそのトレンチ部内に絶縁物を堆積している。ここで，トレンチ部内に堆積する絶縁物としては，ボロンやリン等の不純物が添加されていない絶縁物が適しており，例えばシランガスやＴＥＯＳを主原料としてＣＶＤ法によってトレンチ部の壁面に堆積する酸化膜が該当する。そして，堆積絶縁層を形成した後にエッチバック工程にて堆積絶縁層の一部を除去する。具体的に堆積絶縁層は，ドライエッチングによりのエッチバックされる。   In the method for manufacturing an insulated gate semiconductor device of the present invention, after forming the trench portion in the trench portion forming step, an insulator is deposited in the trench portion in the insulator deposition step. Here, as the insulator deposited in the trench portion, an insulator to which impurities such as boron and phosphorus are not added is suitable. For example, an oxide deposited on the wall surface of the trench portion by a CVD method using silane gas or TEOS as a main material. Applicable to membranes. Then, after forming the deposited insulating layer, a part of the deposited insulating layer is removed by an etch back process. Specifically, the deposited insulating layer is etched back by dry etching.

その後，酸化性雰囲気にてアニール処理を行う。例えば，Ｈ2 とＯ2 との混合気体の雰囲気中で酸化アニール処理を行う。このアニール処理によって，シリコン層の表面に酸化膜が成長し，堆積絶縁層中のシームが消滅する。さらに，酸化性雰囲気中にてアニール処理を行っているため，堆積絶縁層の表層部に含まれるシリコン原子の未結合子がＳｉＯ2 結合に置換される。すなわち，堆積絶縁層の表層部の化学的結合力が強化される。これにより，その後のウェットエッチング工程にてウェットエッチングを行ったとしても，堆積絶縁層中にくさび状の溝は形成されない。よって，電極形成工程にて形成される電極層の形状は安定している。従って，素子特性にばらつきは生じない。なお，電極層は，絶縁膜を形成した後に，ポリシリコンの堆積，不純物拡散，ポリシリコンのドライエッチング，キャップ酸化等を経て形成される。 Thereafter, annealing is performed in an oxidizing atmosphere. For example, oxidation annealing is performed in an atmosphere of a mixed gas of H 2 and O 2 . By this annealing treatment, an oxide film grows on the surface of the silicon layer, and the seam in the deposited insulating layer disappears. Furthermore, since annealing is performed in an oxidizing atmosphere, unbonded silicon atoms contained in the surface layer portion of the deposited insulating layer are replaced with SiO 2 bonds. That is, the chemical bond strength of the surface layer portion of the deposited insulating layer is strengthened. As a result, even if wet etching is performed in the subsequent wet etching process, a wedge-shaped groove is not formed in the deposited insulating layer. Therefore, the shape of the electrode layer formed in the electrode forming process is stable. Therefore, there is no variation in element characteristics. The electrode layer is formed through polysilicon deposition, impurity diffusion, polysilicon dry etching, cap oxidation, and the like after the insulating film is formed.

また，本発明の絶縁ゲート型半導体装置の製造方法は，絶縁物堆積工程にて堆積絶縁層を形成する前であってトレンチ部形成工程にてトレンチ部を形成した後に，そのトレンチ部の底部から不純物を注入する不純物注入工程を含んでいるとよりよい。すなわち，トレンチ部の底部から不純物を注入することにより，半導体基板の厚さ方向の所望の位置にフローティング領域を設けることができる。このフローティング領域によって，電界集中を緩和し，耐圧を向上させることができる。   In addition, the method for manufacturing an insulated gate semiconductor device according to the present invention includes the step of forming a trench portion in the trench portion forming step before forming the deposited insulating layer in the insulator deposition step and then forming the trench portion from the bottom of the trench portion. It is better if an impurity implantation step for implanting impurities is included. That is, by injecting impurities from the bottom of the trench, a floating region can be provided at a desired position in the thickness direction of the semiconductor substrate. This floating region can alleviate electric field concentration and improve breakdown voltage.

また，本発明のトレンチ部形成工程では，テーパ形状のトレンチ部を形成することとするとよりよい。すなわち，トレンチ部の形状がテーパ形状であるため，エッチバック工程時にトレンチ部の肩部が削られて丸みをおびる。そのため，トレンチ部の肩部での電界集中が回避され，高耐圧化を図ることができる。また，そのトレンチ部のテーパの角度が８５度から８９度までの範囲内であることとするとよりよい。すなわち，テーパの角度が８５度より小さいと不純物注入工程にてトレンチ部の壁面に不純物が入り易く，素子特性の変動が大きい。一方，テーパの角度が８９度より大きいと絶縁物堆積工程にて絶縁物の埋め込み性が悪い。よって，テーパの角度が８５度から８９度までの範囲内であれば，酸化膜の埋め込み性が良く，かつイオン注入による素子特性の変動は小さい。   In the trench part forming step of the present invention, it is better to form a tapered trench part. That is, since the shape of the trench portion is tapered, the shoulder portion of the trench portion is shaved and rounded during the etch back process. As a result, electric field concentration at the shoulder of the trench is avoided, and a high breakdown voltage can be achieved. Further, it is more preferable that the taper angle of the trench portion is in the range of 85 degrees to 89 degrees. That is, if the taper angle is smaller than 85 degrees, impurities are likely to enter the wall surface of the trench portion in the impurity implantation step, and the variation in device characteristics is large. On the other hand, if the taper angle is larger than 89 degrees, the insulating property is poor in the insulating material deposition process. Therefore, if the taper angle is in the range of 85 to 89 degrees, the oxide film is well-embedded, and the variation in device characteristics due to ion implantation is small.

また，本発明の絶縁ゲート型半導体装置は，半導体基板内の上面側に位置し第１導電型半導体であるボディ領域と，ボディ領域の下面と接し第２導電型半導体であるドリフト領域と，半導体基板の上面からボディ領域を貫通しその底部がボディ領域の下面より下方に位置するトレンチ部と，ドリフト領域に囲まれるとともにトレンチ部の底部を包含し，第１導電型半導体であるフローティング領域とを有する絶縁ゲート型半導体装置であって，トレンチ部は，テーパ形状であって，そのテーパの角度が８５度から８９度までの範囲内であり，トレンチ部内には，絶縁物を堆積してなる堆積絶縁層と，堆積絶縁層上に位置し，ボディ領域と対面する電極層と，電極層とボディ領域とを隔離する絶縁膜とが形成されており，トレンチ部の壁面は，半導体基板の厚さ方向の，堆積絶縁層と電極層との界面の位置にて段状をなしていることを特徴としている。
The insulated gate semiconductor device of the present invention includes a body region that is located on the upper surface side of the semiconductor substrate and is a first conductivity type semiconductor, a drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor, A trench portion penetrating the body region from the upper surface of the substrate and having a bottom portion located below the lower surface of the body region; and a floating region that is surrounded by the drift region and includes the bottom portion of the trench portion and is a first conductivity type semiconductor An insulated gate semiconductor device comprising: a trench portion having a taper shape, wherein the taper angle is in a range from 85 degrees to 89 degrees, and the trench portion is formed by depositing an insulator. An insulating layer, an electrode layer located on the deposited insulating layer and facing the body region, and an insulating film separating the electrode layer and the body region are formed. Conductor substrate in the thickness direction, is characterized in that it forms a stepped at the interface between the positions of the deposited insulating layer and the electrode layer.

本発明によれば，堆積絶縁層のエッチバックを行った後に酸化性雰囲気中でアニール処理を行っている。これにより，堆積絶縁層の表層部の化学的結合力を強化し，ウェットエッチングによるくさび状の溝の発生を抑制している。従って，堆積絶縁層内の膜質を改善し，堆積絶縁層内のシームやボイドの影響による素子特性の劣化を抑制した絶縁ゲート型半導体装置の製造方法が実現されている。   According to the present invention, after the deposited insulating layer is etched back, the annealing process is performed in an oxidizing atmosphere. This strengthens the chemical bond strength of the surface layer of the deposited insulating layer and suppresses the generation of wedge-shaped grooves due to wet etching. Accordingly, a method of manufacturing an insulated gate semiconductor device has been realized in which the film quality in the deposited insulating layer is improved and deterioration of element characteristics due to the effects of seams and voids in the deposited insulating layer is suppressed.

以下，本発明を具体化した実施の形態について，添付図面を参照しつつ詳細に説明する。なお，本実施の形態は，絶縁ゲートへの電圧印加により，ドレイン−ソース間（ＤＳ間）の導通をコントロールするパワーＭＯＳに本発明を適用したものである。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to a power MOS that controls conduction between a drain and a source (between DS) by applying a voltage to an insulated gate.

実施の形態に係る絶縁ゲート型半導体装置１００（以下，「半導体装置１００」とする）は，図１の断面図に示す構造を有している。なお，本明細書においては，Ｎ+ 基板１１（Ｎ+ ドレイン領域１１）と，Ｎ+ 基板１１上にエピタキシャル成長により形成した単結晶シリコンの部分とを合わせた全体を半導体基板と呼ぶこととする。 An insulated gate semiconductor device 100 (hereinafter referred to as “semiconductor device 100”) according to the embodiment has a structure shown in the cross-sectional view of FIG. In the present specification, the whole of the N + substrate 11 (N + drain region 11) and the single crystal silicon portion formed by epitaxial growth on the N + substrate 11 is referred to as a semiconductor substrate.

半導体装置１００では，半導体基板内における図１中の上面側に，Ｎ+ ソース領域３１が設けられている。一方，下面側にはＮ+ ドレイン領域１１が設けられている。それらの間には上面側から順に，Ｐ- ボディ領域４１およびＮ- ドリフト領域１２が設けられている。なお，Ｐ- ボディ領域４１およびＮ- ドリフト領域１２を合わせた領域（以下，「エピタキシャル層」とする）の厚さは，ＤＳ耐圧が７０Ｖ程度ではおよそ５．５μｍ（そのうち，Ｐ- ボディ領域４１の厚さは，およそ１．０μｍ）である。 In the semiconductor device 100, an N + source region 31 is provided on the upper surface side in FIG. On the other hand, an N + drain region 11 is provided on the lower surface side. Between them, a P − body region 41 and an N − drift region 12 are provided in this order from the upper surface side. The thickness of the region (hereinafter referred to as “epitaxial layer”) including the P − body region 41 and the N − drift region 12 is approximately 5.5 μm (including the P − body region 41 when the DS breakdown voltage is about 70V). Is approximately 1.0 μm).

また，半導体基板の上面側の一部を掘り込むことによりトレンチ部が形成されている。具体的には，セルエリアにゲートトレンチ２１が，終端エリアに終端トレンチ６１がそれぞれ設けられている。各トレンチの深さはおよそ２．３μｍであり，Ｐ- ボディ領域４１を貫通している。また，各トレンチは，トレンチ形成直後の段階でその開口部の幅がおよそ０．４μｍであり，厚さ方向のドレイン電極側（下面側）に向けてその幅が狭くなる形状，いわゆるテーパ形状に設けられている。また，そのテーパの角度は，８５度から８９度までの範囲内である。また，ゲートトレンチ２１の幅は広い部位でおよそ０．７μｍであり，アスペクト比は３以上となっている。 Further, a trench portion is formed by digging a part of the upper surface side of the semiconductor substrate. Specifically, the gate trench 21 is provided in the cell area, and the termination trench 61 is provided in the termination area. Each trench has a depth of approximately 2.3 μm and penetrates the P − body region 41. In addition, each trench has a width of about 0.4 μm immediately after the trench is formed, and a shape in which the width becomes narrower toward the drain electrode side (lower surface side) in the thickness direction, a so-called tapered shape. Is provided. The taper angle is in the range of 85 degrees to 89 degrees. The width of the gate trench 21 is about 0.7 μm at a wide portion, and the aspect ratio is 3 or more.

また，ゲートトレンチ２１の底部には，絶縁物の堆積による堆積絶縁層２３が形成されている。具体的に本形態の堆積絶縁層２３では，ゲートトレンチ２１の底部からおよそ１．１μｍの高さの位置まで酸化シリコンを堆積させている。また，終端トレンチ６１には，絶縁物の堆積による堆積絶縁層６３が形成されている。終端トレンチ６１の内部は，堆積絶縁層６３によって充填されている。この堆積絶縁層２３および堆積絶縁層６３は，シランガスあるいはＴＥＯＳを主原料としてＣＶＤ法による酸化シリコンの堆積によって形成されたものである。なお，詳細については後述する。   A deposited insulating layer 23 is formed on the bottom of the gate trench 21 by depositing an insulator. Specifically, in the deposited insulating layer 23 of this embodiment, silicon oxide is deposited from the bottom of the gate trench 21 to a height of about 1.1 μm. A deposited insulating layer 63 is formed in the termination trench 61 by depositing an insulator. The interior of the termination trench 61 is filled with a deposited insulating layer 63. The deposited insulating layer 23 and the deposited insulating layer 63 are formed by depositing silicon oxide by a CVD method using silane gas or TEOS as a main material. Details will be described later.

さらに，堆積絶縁層２３上には，ポリシリコンの堆積によるゲート電極２２が形成されている。また，ゲートトレンチ２１の壁面の形状は，堆積絶縁層２３とゲート電極２２との界面の位置で段状となっている。そして，ゲートトレンチ２１の壁面には，その段差より上方の位置にゲート酸化膜２４が，下方の位置に熱酸化膜８３がそれぞれ形成されている。また，ゲート電極２２は，ゲート絶縁膜２４を介して半導体基板のＮ+ ソース領域３１およびＰ- ボディ領域４１と対面している。すなわち，ゲート電極２２は，ゲート絶縁膜２４によりＮ+ ソース領域３１およびＰ- ボディ領域４１から絶縁されている。 Further, a gate electrode 22 is formed on the deposited insulating layer 23 by depositing polysilicon. The shape of the wall surface of the gate trench 21 is stepped at the position of the interface between the deposited insulating layer 23 and the gate electrode 22. On the wall surface of the gate trench 21, a gate oxide film 24 is formed at a position above the step, and a thermal oxide film 83 is formed at a position below the step. Further, the gate electrode 22 faces the N + source region 31 and the P − body region 41 of the semiconductor substrate through the gate insulating film 24. That is, the gate electrode 22 is insulated from the N + source region 31 and the P − body region 41 by the gate insulating film 24.

このような構造を持つ半導体装置１００では，ゲート電極２２への電圧印加によりＰ- ボディ領域４１にチャネル効果を生じさせ，もってＮ+ ソース領域３１とＮ+ ドレイン領域１１との間の導通をコントロールしている。 In the semiconductor device 100 having such a structure, a channel effect is generated in the P − body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N + source region 31 and the N + drain region 11. is doing.

さらに，半導体装置１００には，Ｎ- ドリフト領域１２に囲まれたフローティング領域が形成されている。具体的には，セルエリアにＰフローティング領域５１が，終端エリアにＰフローティング領域５３がそれぞれ設けられている。これらのＰフローティング領域は，ゲートトレンチ２１あるいは終端トレンチ６１の底部からボロン等をイオン注入し，その後の熱拡散処理を経て形成された領域であり，各Ｐフローティング領域は，図１中の正面から見てゲートトレンチ２１あるいは終端トレンチ６１の底部を中心とした略円形形状となっている。また，隣り合うＰフローティング領域間には，十分なスペースがある。よって，オン状態において，Ｐフローティング領域５１の存在がドレイン電流に対する妨げとなることはない。また，Ｐフローティング領域５１の半径は，堆積絶縁層２３の厚さの１／２以下である。従って，堆積絶縁層２３の上端は，Ｐフローティング領域５１の上端よりも上方に位置する。よって，堆積絶縁層２３上に堆積するゲート電極２２とＰフローティング領域５１とは対面していない。 Further, a floating region surrounded by the N − drift region 12 is formed in the semiconductor device 100. Specifically, a P floating region 51 is provided in the cell area, and a P floating region 53 is provided in the termination area. These P floating regions are regions formed by ion implantation of boron or the like from the bottom of the gate trench 21 or the termination trench 61 and subsequent thermal diffusion treatment, and each P floating region is viewed from the front in FIG. As seen, it has a substantially circular shape centered on the bottom of the gate trench 21 or the termination trench 61. In addition, there is sufficient space between adjacent P floating regions. Therefore, in the ON state, the presence of the P floating region 51 does not hinder the drain current. The radius of the P floating region 51 is ½ or less of the thickness of the deposited insulating layer 23. Therefore, the upper end of the deposited insulating layer 23 is located above the upper end of the P floating region 51. Therefore, the gate electrode 22 deposited on the deposited insulating layer 23 and the P floating region 51 do not face each other.

本形態の半導体装置１００は，Ｎー ドリフト領域１２内にＰフローティング領域５１が設けられていることにより，それを有しない絶縁ゲート型半導体装置と比較して，次のような特性を有する。すなわち，ＤＳ間への印加電圧によって，Ｎ- ドリフト領域１２とＰ- ボディ領域４１との間のＰＮ接合箇所からドレイン電極に向けて空乏層が広がる。このとき，そのＰＮ接合箇所の近傍が電界強度のピークとなる。そして，空乏層の先端がＰフローティング領域５１に到達すると，Ｐフローティング領域５１がパンチスルー状態となってその電位が固定される。さらに，ＤＳ間の印加電圧が高い場合には，Ｐフローティング領域５１の下端部からも空乏層が形成される。そして，Ｎ- ドリフト領域１２とＰ- ボディ領域４１との間のＰＮ接合箇所とは別に，Ｐフローティング領域５１の下端部の近傍も電界強度のピークとなる。すなわち，電界のピークを２箇所に形成でき，最大ピーク値を低減することで高耐圧化を図ることができる。また，高耐圧であることから，Ｎ- ドリフト領域１２の不純物濃度を上げて低オン抵抗化を図ることができる。 The semiconductor device 100 according to the present embodiment has the following characteristics as compared with an insulated gate semiconductor device that does not include the P floating region 51 provided in the N − drift region 12. In other words, the depletion layer spreads from the PN junction portion between the N − drift region 12 and the P − body region 41 toward the drain electrode by the voltage applied across the DS. At this time, the vicinity of the PN junction portion has a peak of electric field strength. When the tip of the depletion layer reaches the P floating region 51, the P floating region 51 enters a punch-through state, and its potential is fixed. Further, when the applied voltage between the DSs is high, a depletion layer is also formed from the lower end of the P floating region 51. In addition to the PN junction between the N − drift region 12 and the P − body region 41, the vicinity of the lower end of the P floating region 51 also has a peak electric field strength. That is, the electric field peak can be formed at two locations, and the maximum withstand voltage can be increased by reducing the maximum peak value. Further, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration of the N − drift region 12.

また，半導体装置１００では，トレンチ２１内に所定の厚みを有する堆積絶縁層２３を設けることが必要となる。すなわち，Ｐフローティング領域５１は，後述するようにトレンチ２１の底部からのイオン注入等により形成される。そのため，ゲートトレンチ２１の底部には少なからず損傷が生じている。そこで，堆積絶縁層２３を設けることにより，ゲートトレンチ２１の底部の損傷による影響を回避し，素子特性の劣化や信頼性の低下を防止するのである。また，堆積絶縁層２３にてゲート電極２２とＰフローティング領域５１との対面による影響を緩和し，Ｐー ボディ領域４１内のオン抵抗を低減している。   Further, in the semiconductor device 100, it is necessary to provide the deposited insulating layer 23 having a predetermined thickness in the trench 21. That is, the P floating region 51 is formed by ion implantation from the bottom of the trench 21 as will be described later. For this reason, the bottom of the gate trench 21 is not a little damaged. Therefore, by providing the deposited insulating layer 23, the influence of damage to the bottom of the gate trench 21 is avoided, and deterioration of device characteristics and deterioration of reliability are prevented. In addition, the deposited insulating layer 23 reduces the influence of the facing of the gate electrode 22 and the P floating region 51, and reduces the on-resistance in the P− body region 41.

続いて，図１に示した半導体装置１００の製造プロセスについて，図２のプロセス説明図を基に説明する。なお，図２はゲートトレンチ２１の形成プロセスを説明するための説明図であり，Ｐ- ボディ領域４１，Ｎ+ ソース領域３１，Ｐフローティング領域５１等の半導体層の構成要素については省略している。また，本製造プロセスでは，Ｎ+ ドレイン領域１１となるＮ+ 基板上にＮ- 型シリコン層をエピタキシャル成長により形成し，その後のイオン注入や熱拡散処理等によりＰ- ボディ領域４１が形成された半導体基板を出発基板とする。なお，Ｐ- ボディ領域４１，Ｎ+ ソース領域３１，コンタクトＰ+ 領域は，ゲートトレンチ２１の形成前に形成することもゲートトレンチ２１の形成後に形成することもできる。 Next, a manufacturing process of the semiconductor device 100 shown in FIG. 1 will be described based on the process explanatory diagram of FIG. FIG. 2 is an explanatory diagram for explaining the formation process of the gate trench 21, and the components of the semiconductor layer such as the P − body region 41, the N + source region 31, and the P floating region 51 are omitted. . In this manufacturing process, an N − -type silicon layer is formed by epitaxial growth on an N + substrate to be the N + drain region 11, and a P − body region 41 is formed by subsequent ion implantation or thermal diffusion treatment. Let the substrate be the starting substrate. The P − body region 41, the N + source region 31, and the contact P + region can be formed before the gate trench 21 is formed or after the gate trench 21 is formed.

まず，所望のパターンを転写したマスク材を半導体基板上に形成し，図２（ａ）に示すようにドライエッチングによりゲートトレンチ２１を形成する。このとき，ゲートトレンチ２１をテーパ形状となるようにエッチングする。具体的には，ゲートトレンチ２１の開口部から下面側に向けて０．５μｍまでの範囲で測定したテーパの角度（図２（ａ）中のθ１）およびゲートトレンチ２１の底部から上面側に向けて０．５μｍまでの範囲で測定したテーパの角度（図２（ａ）中のθ２）がともに８５度から８９度までの範囲内となるようにエッチングする。   First, a mask material to which a desired pattern is transferred is formed on a semiconductor substrate, and a gate trench 21 is formed by dry etching as shown in FIG. At this time, the gate trench 21 is etched to have a tapered shape. Specifically, the taper angle (θ1 in FIG. 2A) measured in the range from the opening of the gate trench 21 to 0.5 μm toward the lower surface and the bottom of the gate trench 21 toward the upper surface. Etching is performed so that both taper angles (θ2 in FIG. 2A) measured in the range up to 0.5 μm are in the range from 85 degrees to 89 degrees.

なお，テーパの角度を８５度から８９度までの範囲内とする理由は次のとおりである。すなわち，テーパの角度を８５度より小さくするとその後の酸化膜の埋め込み性は向上するが，その後のイオン注入時にゲートトレンチ２１の壁面に不純物が注入されてしまう。特に，ゲートトレンチ２１の壁面のうちのチャネル領域となる部分に不純物を注入してしまうと素子特性が大幅に変化する。また，テーパの角度を小さくしすぎるとゲートトレンチ２１の底部が尖った形状となってしまうため，Ｐフローティング領域５１のサイズをコントロールすることが困難となる。また，深さが深いゲートトレンチ２１を形成すると必然的にゲートトレンチ２１の開口部が広くなり，半導体装置自体のコンパクト化の妨げとなる。一方，テーパの角度を８９度より大きくするとこれらの問題は生じないが，酸化膜の埋め込み性が低下する。そのため，テーパの角度は，８５度から８９度までの範囲内とすることが適当である。   The reason why the taper angle is in the range from 85 degrees to 89 degrees is as follows. In other words, if the taper angle is smaller than 85 degrees, the burying property of the oxide film thereafter is improved, but impurities are implanted into the wall surface of the gate trench 21 during the subsequent ion implantation. In particular, if the impurity is implanted into the portion of the wall surface of the gate trench 21 that will become the channel region, the device characteristics will change significantly. Further, if the taper angle is too small, the bottom of the gate trench 21 has a sharp shape, which makes it difficult to control the size of the P floating region 51. Further, when the deep gate trench 21 is formed, the opening of the gate trench 21 is inevitably widened, which hinders the compactness of the semiconductor device itself. On the other hand, if the taper angle is greater than 89 degrees, these problems do not occur, but the embeddability of the oxide film decreases. Therefore, it is appropriate that the taper angle is in the range of 85 degrees to 89 degrees.

次に，ＣＤＥ（ケミカルドライエッチング）等の等方的なエッチング法を利用して各トレンチの壁面を平滑化し，その後に所望の厚さの犠牲酸化膜を形成する。ゲートトレンチ２１の底面から不純物のイオン注入を行う。これにより，ゲートトレンチ２１の下方にＮ- ドリフト領域１２に囲まれたＰフローティング領域５１が形成される。犠牲酸化膜の形成後にイオン注入を行うのは，ゲートトレンチ２１の側壁に不純物を注入しないようにするためである。イオン注入後は，犠牲酸化膜を除去する。 Next, the wall surface of each trench is smoothed by using an isotropic etching method such as CDE (chemical dry etching), and then a sacrificial oxide film having a desired thickness is formed. Impurity ions are implanted from the bottom of the gate trench 21. As a result, a P floating region 51 surrounded by the N − drift region 12 is formed below the gate trench 21. The reason why ion implantation is performed after the formation of the sacrificial oxide film is to prevent impurities from being implanted into the side walls of the gate trench 21. After the ion implantation, the sacrificial oxide film is removed.

次に，図２（ｂ）に示すようにゲートトレンチ２１の壁面に沿って厚さが３０ｎｍ〜５０ｎｍのシリコン酸化膜８５を形成する。すなわち，ゲートトレンチ２１内に酸化膜を埋め込む前に，半導体基板の表面上にシリコン酸化膜８５を形成する。このシリコン酸化膜８５により，後述する絶縁膜の埋め込み性が向上するとともに界面準位の影響を排除することが可能となる。   Next, as shown in FIG. 2B, a silicon oxide film 85 having a thickness of 30 nm to 50 nm is formed along the wall surface of the gate trench 21. That is, before the oxide film is embedded in the gate trench 21, a silicon oxide film 85 is formed on the surface of the semiconductor substrate. The silicon oxide film 85 improves the filling property of an insulating film, which will be described later, and can eliminate the influence of the interface state.

次に，図２（ｃ）に示すようにゲートトレンチ２１に対して不純物がドープされていない，いわゆるノンドープの絶縁膜の埋め込みを行う。この絶縁膜の埋め込み処理では，シリコン酸化膜８５上に埋め込み絶縁膜を堆積することでその埋め込み絶縁膜とシリコン酸化膜８５とが一体化し，半導体基板上に６００ｎｍ程度の膜厚の堆積絶縁層２３が形成される。具体的には，例えば反応ガスをＴＥＯＳとＯ2 とを含む混合ガスとし，成膜温度を６００℃〜６８０℃として，減圧ＣＶＤ法によって半導体基板上にＴＥＯＳ系の酸化膜を形成する。 Next, as shown in FIG. 2C, the gate trench 21 is filled with a so-called non-doped insulating film that is not doped with impurities. In this insulating film embedding process, the embedded insulating film is deposited on the silicon oxide film 85 so that the embedded insulating film and the silicon oxide film 85 are integrated, and the deposited insulating layer 23 having a thickness of about 600 nm is formed on the semiconductor substrate. Is formed. Specifically, for example, a reactive gas is a mixed gas containing TEOS and O 2 , a film forming temperature is 600 ° C. to 680 ° C., and a TEOS-based oxide film is formed on the semiconductor substrate by a low pressure CVD method.

次に，半導体基板のうちの終端エリアにレジストを形成した後，図２（ｄ）に示すように堆積絶縁層２３に対してドライエッチングを行う。これにより，堆積絶縁層２３の一部が除去（エッチバック）され，ゲート電極２２を形成するためのスペースが確保される。ドライエッチングの手段としては，例えば高選択比エッチングが可能なＲＩＥ（反応性イオンエッチング）法が用いられる。すなわち，ＲＩＥ法にてエッチバックを行うことで，シームの有無に関わらず酸化膜が厚さ方向に均等に除去される。なお，エッチバックに利用するエッチングガスは，エッチングされる材料により適宜選択される。例えば，本形態のようにシリコン酸化膜を除去するには，Ｃ4Ｆ8が使用される。また、エッチングガスにはＯ2 ，Ａｒ等のその他のガスを添加してもよい。 Next, after forming a resist in the terminal area of the semiconductor substrate, dry etching is performed on the deposited insulating layer 23 as shown in FIG. Thereby, a part of the deposited insulating layer 23 is removed (etched back), and a space for forming the gate electrode 22 is secured. As a dry etching means, for example, an RIE (reactive ion etching) method capable of high selective etching is used. That is, by performing etch back by the RIE method, the oxide film is uniformly removed in the thickness direction regardless of the presence or absence of seams. The etching gas used for etch back is appropriately selected depending on the material to be etched. For example, C 4 F 8 is used to remove the silicon oxide film as in this embodiment. Further, other gases such as O 2 and Ar may be added to the etching gas.

次に，不要なレジストを除去し，絶縁膜が形成された半導体基板に対し，酸化性雰囲気にてアニール処理を行う。具体的には，例えばＨ2 とＯ2 との混合気体の雰囲気中，９００℃〜１０００℃の範囲内の温度により，２０分程度の時間，酸化アニール処理を行う。このアニール処理によって堆積絶縁層２３の緻密化が図られる。さらに，酸化性雰囲気中にてアニール処理を行っていることから，図２（ｅ）に示すようにゲートトレンチ２１の壁面に沿って熱酸化膜８３が形成される。この熱酸化膜８３の成長により，ゲートトレンチ２１中の壁面上に堆積する絶縁膜がそのトレンチの中央部分に向けて押し出される。さらに，堆積絶縁層２３の表層部（上面部）では，シリコン原子の未結合子が酸素と反応することでＳｉＯ2 結合に置換される。これにより，堆積絶縁層２３の表層部では，堆積絶縁層２３中のシームが消滅するとともに化学的結合力が強化され，後述するウェットエッチングに対する耐性が向上する。なお，酸化アニール処理の方法としては，例えば水素燃焼酸化法やドライ酸化法がある。 Next, unnecessary resist is removed, and the semiconductor substrate on which the insulating film is formed is annealed in an oxidizing atmosphere. Specifically, for example, an oxidation annealing process is performed for about 20 minutes at a temperature in the range of 900 ° C. to 1000 ° C. in an atmosphere of a mixed gas of H 2 and O 2 . By this annealing treatment, the deposited insulating layer 23 is densified. Further, since annealing is performed in an oxidizing atmosphere, a thermal oxide film 83 is formed along the wall surface of the gate trench 21 as shown in FIG. By the growth of the thermal oxide film 83, the insulating film deposited on the wall surface in the gate trench 21 is pushed out toward the central portion of the trench. Further, in the surface layer portion (upper surface portion) of the deposited insulating layer 23, unbonded silicon atoms react with oxygen to be replaced with SiO 2 bonds. As a result, in the surface layer portion of the deposited insulating layer 23, the seam in the deposited insulating layer 23 disappears and the chemical bonding force is strengthened, and resistance to wet etching described later is improved. Examples of the oxidation annealing method include a hydrogen combustion oxidation method and a dry oxidation method.

なお，酸化膜を埋め込んだ直後に酸化アニール処理を行うとしてもボイドやシームを消滅させることができるが，本形態のようにエッチバック後に酸化アニール処理を行う方が次の点で有利である。すなわち，酸化膜を埋め込んだ直後に酸化アニール処理では，ゲートトレンチ２１内の深い位置に生じたボイド等を消滅させることができないことがある。一方，エッチバック後のアニール処理によれば，ウェットエッチングに対する耐性を強化したい部分について確実にボイド等を消滅させることができるとともに膜質を改善させることができる。よって，より確実にくさび状の溝の発生を抑制することができる。さらに，エッチバック後の酸化アニール処理では，酸化膜を埋め込んだ直後の酸化アニール処理と比較して，低温でかつ短時間で行うことができるために熱負荷が小さい。また，半導体基板に生じる残留応力も小さい。   Even if the oxidation annealing process is performed immediately after the oxide film is buried, voids and seams can be eliminated. However, the oxidation annealing process after the etch-back as in this embodiment is advantageous in the following points. That is, there are cases where voids and the like generated at deep positions in the gate trench 21 cannot be eliminated by the oxidation annealing process immediately after the oxide film is buried. On the other hand, according to the annealing treatment after the etch back, voids and the like can be surely eliminated and the film quality can be improved in the portion where the resistance to wet etching is desired to be enhanced. Therefore, the generation of wedge-shaped grooves can be suppressed more reliably. Furthermore, the oxidation annealing treatment after etch back has a lower thermal load because it can be performed at a lower temperature and in a shorter time than the oxidation annealing treatment immediately after the oxide film is buried. Also, the residual stress generated in the semiconductor substrate is small.

次に，半導体基板の表面に対して洗浄処理を行う。具体的には，フッ酸系の薬液（例えばＢＨＦ（緩衝フッ酸））によるウェットエッチングを行う。このウェットエッチングにより，酸化アニール処理にて半導体基板の表面に形成された熱酸化膜８３や堆積絶縁層２３の表層部が除去される。これにより，エッチバック時のドライエッチングにてゲートトレンチ２１の壁面に生じる付着物やダメージ層が熱酸化膜８３とともに除去される。なお，先の酸化アニール処理によって，堆積絶縁層２３ではシームが消滅している。そのため，堆積絶縁層２３に対してウェットエッチングを行ったとしても，堆積絶縁膜２３にくさび状の溝（図４参照）は形成されない。なお，この洗浄処理によってゲートトレンチ２１の壁面のうちの露出している部分が僅かに後退する。これにより，図２（ｆ）に示すようにゲートトレンチ２１の壁面の形状が段状となる。   Next, a cleaning process is performed on the surface of the semiconductor substrate. Specifically, wet etching using a hydrofluoric acid chemical solution (for example, BHF (buffered hydrofluoric acid)) is performed. By this wet etching, the thermal oxide film 83 formed on the surface of the semiconductor substrate by the oxidation annealing process and the surface layer portion of the deposited insulating layer 23 are removed. As a result, deposits and damage layers generated on the wall surface of the gate trench 21 by dry etching during etch back are removed together with the thermal oxide film 83. Note that the seam disappears in the deposited insulating layer 23 by the previous oxidation annealing treatment. Therefore, even if wet etching is performed on the deposited insulating layer 23, a wedge-shaped groove (see FIG. 4) is not formed in the deposited insulating film 23. Note that the exposed portion of the wall surface of the gate trench 21 is slightly retracted by this cleaning process. As a result, the shape of the wall surface of the gate trench 21 is stepped as shown in FIG.

その後，熱酸化処理を行い，図２（ｇ）に示すようにエピタキシャル層の表面に膜厚が１００ｎｍ程度の酸化膜２４を形成する。この酸化膜２４がゲート酸化膜２４となる。具体的には，Ｈ2 とＯ2 との混合気体の雰囲気中，９００℃〜１１００℃の範囲内の温度にて熱酸化処理を行う。 Thereafter, thermal oxidation treatment is performed to form an oxide film 24 having a thickness of about 100 nm on the surface of the epitaxial layer as shown in FIG. This oxide film 24 becomes the gate oxide film 24. Specifically, thermal oxidation treatment is performed at a temperature in the range of 900 ° C. to 1100 ° C. in an atmosphere of a mixed gas of H 2 and O 2 .

次に，エッチバックにて確保したスペースに対し，図２（ｈ）に示すようにゲート材２２を堆積する。具体的にゲート材２２の成膜条件としては，例えば反応ガスをＳｉＨ4 を含む混合ガスとし，成膜温度を５８０℃〜６４０℃とし，常圧ＣＶＤ法によって８００ｎｍ程度の膜厚のポリシリコン膜を形成する。このポリシリコン膜がゲート電極２２となる。なお，ゲート電極２２を形成する方法としては，導体を直接ゲートトレンチ２１内に堆積する方法の他，一旦高抵抗の半導体を堆積させた後にその絶縁層に対して不純物を拡散させる方法がある。最後に，ゲート材２２に対してエッチングを行い，その後にソース電極，ドレイン電極等を形成することにより，図１に示したような半導体装置１００が作製される。 Next, a gate material 22 is deposited in the space secured by etch back as shown in FIG. Specifically, the film formation conditions for the gate material 22 include, for example, a reactive gas mixed gas containing SiH 4 , a film formation temperature of 580 ° C. to 640 ° C., and a polysilicon film having a thickness of about 800 nm by atmospheric pressure CVD. Form. This polysilicon film becomes the gate electrode 22. As a method of forming the gate electrode 22, there is a method of depositing a conductor directly in the gate trench 21 or a method of once depositing a high resistance semiconductor and then diffusing impurities into the insulating layer. Finally, the gate material 22 is etched, and then a source electrode, a drain electrode, and the like are formed, whereby the semiconductor device 100 as shown in FIG. 1 is manufactured.

以上詳細に説明したように，本形態の製造方法にて製造される半導体装置１００は，従来の半導体装置の製造方法と比較して，次のような特性を有する。すなわち，ノンドープの堆積絶縁層２３を形成し，その堆積絶縁層２３の一部をエッチバックした後に酸化アニール処理を行うことにより，ゲートトレンチ２１の壁面沿いに熱酸化膜８３を形成することとしている。この酸化アニール処理により，堆積絶縁層２３の表層部の化学的結合力を強化している。そのため，エッチバック後の洗浄処理（ウェットエッチング）にて，堆積絶縁層２３中にくさび状の溝は形成されない。この製造方法によると，アスペクト比が高いトレンチ部内に絶縁物を充填する場合，すなわちトレンチ部内の深い部分にシームが発生する場合であっても確実にくさび状の溝の発生を抑制することができる。そのため，ゲート電極２２の形状は安定し，素子特性にばらつきは生じない。よって，堆積絶縁層内の膜質を改善し，堆積絶縁層内のシームやボイドの影響による素子特性の劣化を抑制した絶縁ゲート型半導体装置の製造方法が実現されている。   As described above in detail, the semiconductor device 100 manufactured by the manufacturing method of the present embodiment has the following characteristics as compared with the conventional method of manufacturing a semiconductor device. That is, the thermal oxide film 83 is formed along the wall surface of the gate trench 21 by forming a non-doped deposited insulating layer 23 and performing an oxidation annealing process after etching back a part of the deposited insulating layer 23. . By this oxidation annealing treatment, the chemical bonding strength of the surface layer portion of the deposited insulating layer 23 is enhanced. Therefore, a wedge-shaped groove is not formed in the deposited insulating layer 23 by the cleaning process (wet etching) after the etch back. According to this manufacturing method, even when an insulator is filled in a trench portion having a high aspect ratio, that is, when a seam is generated in a deep portion in the trench portion, the generation of a wedge-shaped groove can be surely suppressed. . Therefore, the shape of the gate electrode 22 is stable, and the element characteristics do not vary. Therefore, a method for manufacturing an insulated gate semiconductor device has been realized in which the film quality in the deposited insulating layer is improved and deterioration of element characteristics due to the effects of seams and voids in the deposited insulating layer is suppressed.

また，ドライエッチング時にゲートトレンチ２１の壁面に生じる付着物やダメージ層の除去は，一般的にＣＤＥ（ケミカルドライエッチング）や，犠牲酸化後のウェットエッチングや，これらの併用によって行われる。しかしながら，本形態の製造方法によると，酸化性雰囲気でのアニール処理によってゲートトレンチ２１の壁面に熱酸化膜８３を成長させている。そして，この熱酸化膜８３にエッチバック時のドライエッチングによる付着物やダメージ層が取り込まれる。そのため，熱酸化膜８３のウェットエッチング時に，エッチバック時の付着物やダメージ層の除去を兼ねることが可能である。よって，製造工程が簡素化される。   Also, removal of deposits and damaged layers generated on the wall surface of the gate trench 21 during dry etching is generally performed by CDE (chemical dry etching), wet etching after sacrificial oxidation, or a combination thereof. However, according to the manufacturing method of this embodiment, the thermal oxide film 83 is grown on the wall surface of the gate trench 21 by annealing in an oxidizing atmosphere. Then, deposits and damage layers due to dry etching at the time of etch back are taken into this thermal oxide film 83. Therefore, it is possible to remove deposits and damaged layers at the time of etch back at the time of wet etching of the thermal oxide film 83. Therefore, the manufacturing process is simplified.

また，ゲートトレンチ２１は，８５度から８９度の範囲内のテーパ角度を有するテーパ形状となっている。この範囲内であれば，酸化膜の埋め込み性が良く，かつイオン注入による素子特性の変動は小さい。   The gate trench 21 has a tapered shape having a taper angle in the range of 85 to 89 degrees. Within this range, the oxide film can be embedded well, and the variation in device characteristics due to ion implantation is small.

また，犠牲酸化処理や埋め込み前酸化処理を低温で行うと，ゲートトレンチ２１の肩部が尖り易い。そして，その肩部が尖れば尖るほどゲート耐圧は低下する。しかし，ゲートトレンチ２１の形状をテーパ形状とすることにより，エッチバック時のドライエッチングの際，ゲートトレンチ２１の肩部が削られて丸みをおびる。そのため，ゲート耐圧の低下が抑制される。   Further, when the sacrificial oxidation process or the pre-filling oxidation process is performed at a low temperature, the shoulder of the gate trench 21 tends to be sharp. And, the sharper the shoulder, the lower the gate breakdown voltage. However, by making the shape of the gate trench 21 tapered, the shoulder portion of the gate trench 21 is shaved and rounded during dry etching during etch back. As a result, a decrease in gate breakdown voltage is suppressed.

なお，本実施の形態は単なる例示にすぎず，本発明を何ら限定するものではない。したがって本発明は当然に，その要旨を逸脱しない範囲内で種々の改良，変形が可能である。例えば，各半導体領域については，Ｐ型とＮ型とを入れ替えてもよい。また，ゲート絶縁膜２４については，酸化膜に限らず，窒化膜等の他の種類の絶縁膜でもよいし，複合膜でもよい。また，半導体についても，シリコンに限らず，他の種類の半導体（ＳｉＣ，ＧａＮ，ＧａＡｓ等）であってもよい。また，実施の形態の絶縁ゲート型半導体装置は，Ｐ型基板を用いたパワーＭＯＳやＩＧＢＴに対しても適用可能である。   Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, for each semiconductor region, P-type and N-type may be interchanged. Further, the gate insulating film 24 is not limited to an oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.). The insulated gate semiconductor device of the embodiment can also be applied to a power MOS or IGBT using a P-type substrate.

また，本実施の形態では，イオン注入直後にＰフローティング領域５１を形成しているが，これに限るものではない。すなわち，Ｐフローティング領域５１の形成を後の酸化アニール工程で兼用してもよい。   In the present embodiment, the P floating region 51 is formed immediately after ion implantation, but the present invention is not limited to this. That is, the formation of the P floating region 51 may also be used in the subsequent oxidation annealing step.

実施の形態に係る絶縁ゲート型半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on embodiment. 実施の形態に係る絶縁ゲート型半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the insulated gate semiconductor device which concerns on embodiment. 従来の絶縁ゲート型半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the conventional insulated gate semiconductor device. くさび状の溝が形成された堆積絶縁層を示す断面図である。It is sectional drawing which shows the deposited insulating layer in which the wedge-shaped groove | channel was formed.

符号の説明Explanation of symbols

１１ Ｎ+ ドレイン領域
１２ Ｎ- ドリフト領域
２１ トレンチ（トレンチ部）
２２ ゲート電極（電極層）
２３ 堆積絶縁層（堆積絶縁層）
２４ ゲート絶縁膜（絶縁膜）
３１ Ｎ+ ソース領域
４１ Ｐ- ボディ領域
５１ Ｐフローティング領域
８１ くさび状の溝
８２ ボイド
８３ 熱酸化膜
１００ 絶縁ゲート型半導体装置 11 N + drain region 12 N − drift region 21 trench (trench portion)
22 Gate electrode (electrode layer)
23 Deposition insulation layer (Deposition insulation layer)
24 Gate insulating film (insulating film)
31 N + source region 41 P - body region 51 P floating region 81 wedge-shaped groove 82 void 83 thermal oxide film 100 insulated gate semiconductor device

Claims (3)

トレンチ型電極構造を有する絶縁ゲート型半導体装置の製造方法において，
半導体基板の上面からトレンチ部を形成するトレンチ部形成工程と，
前記トレンチ部形成工程にてトレンチ部を形成した後に，そのトレンチ部の底部から不純物を注入する不純物注入工程と，
前記不純物注入工程にて不純物を注入した後に，そのトレンチ部内に絶縁物の堆積による堆積絶縁層を形成する絶縁物堆積工程と，
前記絶縁物堆積工程にて堆積絶縁層を形成した後に，堆積絶縁層の一部を除去するエッチバック工程と，
前記エッチバック工程にて堆積絶縁層の一部を除去した後に，水素と酸素との混合気体の酸化性雰囲気中，９００℃から１０００℃の範囲内の温度にてアニール処理を行うアニール工程と，
前記アニール工程にてアニール処理を行った後に，ウェットエッチングにて表面の酸化膜層を除去するウェットエッチング工程と，
前記ウェットエッチング工程にて酸化膜を除去した後に，トレンチ部の壁面に沿って絶縁膜を形成する絶縁膜形成工程と，
前記絶縁膜形成工程にて絶縁膜を形成した後に，堆積絶縁層の上面上に電極層を形成する電極層形成工程と含むことを特徴とする絶縁ゲート型半導体装置の製造方法。 In a method of manufacturing an insulated gate semiconductor device having a trench type electrode structure,
Forming a trench portion from the upper surface of the semiconductor substrate;
An impurity implantation step of implanting impurities from the bottom of the trench portion after forming the trench portion in the trench portion formation step;
An insulator deposition step of forming a deposited insulating layer by depositing an insulator in the trench portion after implanting impurities in the impurity implantation step ;
An etch back step of removing a portion of the deposited insulating layer after forming the deposited insulating layer in the insulator deposition step;
An annealing step of performing an annealing treatment at a temperature in the range of 900 ° C. to 1000 ° C. in an oxidizing atmosphere of a mixed gas of hydrogen and oxygen after removing a part of the deposited insulating layer in the etch back step;
A wet etching step of removing a surface oxide film layer by wet etching after performing the annealing process in the annealing step;
An insulating film forming step of forming an insulating film along the wall surface of the trench portion after removing the oxide film in the wet etching step;
A method of manufacturing an insulated gate semiconductor device, comprising: forming an electrode layer on an upper surface of a deposited insulating layer after forming an insulating film in the insulating film forming step. 請求項１に記載する絶縁ゲート型半導体装置の製造方法において，
前記トレンチ部形成工程では，テーパの角度が８５度から８９度までの範囲内であるテーパ形状のトレンチ部を形成することを特徴とする絶縁ゲート型半導体装置の製造方法。 In the manufacturing method of the insulated gate semiconductor device according to claim 1,
In the trench part forming step, a tapered trench part having a taper angle in a range of 85 degrees to 89 degrees is formed . 半導体基板内の上面側に位置し第１導電型半導体であるボディ領域と，前記ボディ領域の下面と接し第２導電型半導体であるドリフト領域と，半導体基板の上面から前記ボディ領域を貫通しその底部が前記ボディ領域の下面より下方に位置するトレンチ部と，前記ドリフト領域に囲まれるとともに前記トレンチ部の底部を包含し，第１導電型半導体であるフローティング領域とを有する絶縁ゲート型半導体装置において，
前記トレンチ部は，テーパ形状であって，そのテーパの角度が８５度から８９度までの範囲内であり，
前記トレンチ部内には，
絶縁物を堆積してなる堆積絶縁層と，
前記堆積絶縁層上に位置し，前記ボディ領域と対面する電極層と，
前記電極層と前記ボディ領域とを隔離する絶縁膜とが形成されており，
前記トレンチ部の壁面は，半導体基板の厚さ方向の，前記堆積絶縁層と前記電極層との界面の位置にて段状をなしていることを特徴とする絶縁ゲート型半導体装置。 A body region that is a first conductivity type semiconductor located on the upper surface side in the semiconductor substrate, a drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor, and penetrates the body region from the upper surface of the semiconductor substrate; In an insulated gate semiconductor device, comprising: a trench portion whose bottom is positioned below the lower surface of the body region; and a floating region that is surrounded by the drift region and includes the bottom of the trench portion and is a first conductivity type semiconductor ,
The trench portion has a tapered shape, and an angle of the taper is in a range from 85 degrees to 89 degrees,
In the trench part,
A deposited insulating layer formed by depositing an insulator;
An electrode layer located on the deposited insulating layer and facing the body region;
An insulating film separating the electrode layer and the body region is formed;
2. The insulated gate semiconductor device according to claim 1, wherein the wall surface of the trench portion is stepped at the interface between the deposited insulating layer and the electrode layer in the thickness direction of the semiconductor substrate.
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