JP2020047729A - Manufacturing method of semiconductor device - Google Patents

Abstract

To provide a technique capable of suppressing cracks in an insulating layer formed in a trench.SOLUTION: A manufacturing method of a semiconductor device includes a step of forming a first insulating layer by performing chemical vapor deposition under a pressure of 150 Pa or more and 300 Pa or less on an inner surface of a trench formed on an upper surface of the semiconductor substrate, a first heat-treating step of heat-treating the semiconductor substrate and shrinking the first insulating layer after forming the first insulating layer, a step of filling the trench by forming a second insulating layer on a surface of the first insulating layer by performing chemical vapor deposition under a pressure of 150 Pa or more and 300 Pa or less after the first heat-treating step, and a second heat-treating step of heat treating the semiconductor substrate after forming the second insulating layer.SELECTED DRAWING: Figure 5

Description

  The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

  Patent Literature 1 discloses a semiconductor device in which an insulating layer is formed at a bottom of a trench provided on an upper surface of a semiconductor substrate. In manufacturing the semiconductor device, first, a first insulating layer is formed on the inner surface of the trench by performing chemical vapor deposition under a first pressure. Then, a second insulating layer is formed on the surface of the first insulating layer by performing chemical vapor deposition in the trench under a second pressure higher than the first pressure. Further, in a step after the first insulating layer and the second insulating layer are formed, heat treatment is performed on the semiconductor substrate.

  In the manufacturing method of Patent Literature 1, the first insulating layer is formed under the first pressure (that is, relatively low pressure). It becomes an insulating layer. On the other hand, since the second insulating layer is formed under a second pressure higher than the first pressure (that is, a relatively high pressure), the second insulating layer is formed at a higher speed, It becomes a sparse insulating layer.

  In the manufacturing method of Patent Literature 1, a heat treatment is performed on the semiconductor substrate after the first insulating layer and the second insulating layer are formed, so that the first insulating layer and the second insulating layer thermally contract. The first insulating layer, which is a dense insulating layer, has less shrinkage due to heat treatment than the second insulating layer, which is a sparse insulating layer. As described above, in the manufacturing method of Patent Document 1, since the first insulating layer that is not easily shrunk is formed on the inner surface of the trench, high stress is hardly generated in the trench, and the first insulating layer and the second insulating layer are not formed. It is described that the occurrence of cracks is suppressed.

JP 2015-126027 A

  In the technique of Patent Document 1, since the first insulating layer is formed by performing chemical vapor deposition under a relatively low pressure, the thickness of the first insulating layer is thin at the bottom of the trench, Becomes thicker from the bottom to the top. For this reason, when the second insulating layer is formed, the upper end of the trench is easily closed, and voids (voids) and seams (the deposited layers are in physical contact with each other) inside the second insulating layer. (A part that is not chemically bonded). Therefore, the heat treatment may cause cracks in the insulating layer starting from voids or seams. The present specification provides a technique capable of suppressing cracks in an insulating layer formed in a trench.

  In the method for manufacturing a semiconductor device disclosed in this specification, a first insulating layer is formed by performing chemical vapor deposition under a pressure of 150 Pa or more and 300 Pa or less on an inner surface of a trench formed on an upper surface of a semiconductor substrate. Performing a heat treatment on the semiconductor substrate after the first insulating layer is formed to shrink the first insulating layer; and performing the first heat treatment after the first heat treatment. Forming a second insulating layer on the surface of the insulating layer by performing chemical vapor deposition under a pressure of 150 Pa or more and 300 Pa or less, and filling the trench with the second insulating layer; After the insulating layer is formed, a second heat treatment step of heat-treating the semiconductor substrate is provided.

  In the above manufacturing method, first, a first insulating layer is formed by performing chemical vapor deposition on the inner surface of the trench under a pressure of 150 Pa or more and 300 Pa or less, and then the first insulating layer is heat-treated. As described above, since the first insulating layer is formed under a relatively high pressure, the first insulating layer is formed with a relatively uniform thickness on the inner surface of the trench. Then, by heat-treating the first insulating layer, the first insulating layer is contracted and densified. After that, the second insulating layer is formed by performing chemical vapor deposition under a pressure of 150 Pa or more and 300 Pa or less (relatively high pressure). Since the first insulating layer has a relatively uniform thickness, the upper end of the trench is not easily closed when forming the second insulating layer. Therefore, in the above-described manufacturing method, when forming the second insulating layer, voids and seams are hardly generated inside the second insulating layer. In addition, since the first insulating layer is densified by the first heat treatment step, shrinkage due to heat treatment of the semiconductor substrate thereafter is small, and stress is hardly generated inside the trench. Thus, according to the above manufacturing method, cracks in the insulating layer formed in the trench can be suppressed.

FIG. 2 is a top view of the MOSFET 10. FIG. 2 is a vertical sectional view of the MOSFET 10 taken along the line II-II in FIG. 1. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10.

  FIG. 1 shows a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 10 of the embodiment. The MOSFET 10 includes a semiconductor substrate 12, an electrode, an insulating layer, and the like. In FIG. 1, illustration of electrodes, insulating layers, and the like on the upper surface 12a of the semiconductor substrate 12 is omitted for easy viewing. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as an x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as a y direction, and a thickness direction of the semiconductor substrate 12 is referred to as a z direction. The semiconductor substrate 12 is made of, for example, SiC (silicon carbide).

  As shown in FIG. 1, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends linearly and long in the y direction. The plurality of trenches 22 are arranged at intervals in the x direction. As shown in FIG. 2, a gate insulating layer 24 and a gate electrode 26 are arranged inside each trench 22.

The gate insulating layer 24 covers the inner surface of the trench 22. The gate insulating layer 24 is made of SiO ₂ (silicon dioxide). The gate insulating layer 24 has a bottom insulating layer 24a and a side insulating film 24b. The bottom insulating layer 24a is disposed at the bottom of the trench 22. The bottom insulating layer 24a covers the side surface of the trench 22 near the bottom surface of the trench. The side insulating film 24b covers the side of the trench 22 located above the bottom insulating layer 24a.

  The gate electrode 26 is disposed above the bottom insulating layer 24a. That is, the insulating layer between the gate electrode 26 and the bottom surface of the trench 22 is the bottom insulating layer 24a. The insulating layer between the gate electrode 26 and the side surface of the trench 22 is the side surface insulating film 24b. The gate electrode 26 is insulated from the semiconductor substrate 12 by the bottom insulating layer 24a and the side insulating film 24b. The upper surface of the gate electrode 26 is covered with an interlayer insulating film 28.

  The thickness of the side insulating film 24b (that is, the distance between the side surface of the trench 22 and the side surface of the gate electrode 26) depends on the thickness of the bottom insulating layer 24a (that is, the width between the upper surface and the lower surface of the bottom insulating layer 24a (in other words, , The distance between the lower end of the gate electrode 26 and the bottom surface of the trench 22).

  As shown in FIG. 2, an upper electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at a portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. The lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

  As shown in FIG. 2, inside the semiconductor substrate 12, a plurality of n-type source regions 30 and a plurality of p-type body regions 32 (specifically, a plurality of body contact regions 32a and a main body region 32b) are provided. An n-type drift region 34, an n-type drain region 35, and a plurality of p-type bottom regions 36 are provided.

  When turning on the MOSFET 10, a gate-on potential (potential higher than the gate threshold) is applied to the gate electrode 26. Then, a channel (inversion layer) is formed in the main body region 32b in a range in contact with the side surface insulating film 24b, and the MOSFET 10 is turned on. When the MOSFET 10 is turned off, a gate-off potential (a potential equal to or lower than a gate threshold) is applied to the gate electrode 26. Then, the channel formed in main body region 32b disappears, and MOSFET 10 is turned off.

  Next, a method for manufacturing the MOSFET 10 will be described with reference to FIGS. First, as shown in FIG. 3, a trench 22 is formed on the upper surface of the semiconductor substrate 12. Although only one trench 22 is shown in FIGS. 3 to 8, a plurality of trenches 22 are actually formed on the upper surface of the semiconductor substrate 12. It should be noted that the element structure inside the semiconductor substrate 12 is omitted in FIGS.

  Next, as shown in FIG. 4, the first insulating layer 40 is formed on the inner surface of the trench 22 by chemical vapor deposition (hereinafter, referred to as CVD (Chemical Vapor Deposition)) under a pressure of 150 Pa or more and 300 Pa or less, for example. To form At this time, the first insulating layer 40 is formed so as to cover the inner surface of the trench 22 and the upper surface 12a of the semiconductor substrate 12. That is, the first insulating layer 40 is formed so as not to fill the trench 22. Since the first insulating layer 40 is formed under a relatively high pressure (150 Pa or more and 300 Pa or less), it becomes a sparse insulating layer having a relatively uniform thickness with respect to the inner surface of the trench 22.

Next, as shown in FIG. 5, the semiconductor substrate 12 is heat-treated to shrink the first insulating layer 40. Thereby, the first insulating layer 40 is densified (that is, becomes a dense insulating layer). The heat treatment of the semiconductor substrate 12 in the step of shrinking the first insulating layer 40 is performed in a non-oxidizing atmosphere such as an N ₂ (nitrogen) atmosphere or an Ar (argon) atmosphere. Thereby, generation of defects in the semiconductor substrate 12 due to oxidation of the semiconductor substrate 12 is suppressed.

  Next, as shown in FIG. 6, for example, the second insulating layer 42 is formed on the surface of the first insulating layer 40 by CVD under a pressure of 150 Pa or more and 300 Pa or less. At this time, the second insulating layer 42 is formed so as to fill the trench 22. Since the second insulating layer 42 is formed under a relatively high pressure (150 Pa or more and 300 Pa or less), it becomes a sparse insulating layer.

Next, as shown in FIG. 7, the semiconductor substrate 12 is heat-treated to shrink the second insulating layer 42. Thereby, the second insulating layer is densified. Since the first insulating layer 40 has already been densified in the above-described steps, it hardly shrinks. At this time, the second insulating layer 42 is contracted such that the etching rate of the second insulating layer 42 is substantially equal to the etching rate of the first insulating layer 40. The heat treatment of the semiconductor substrate 12 in the step of shrinking the second insulating layer 42 is performed in a non-oxidizing atmosphere such as an N ₂ atmosphere or an Ar atmosphere. Therefore, also in this step, occurrence of defects in the semiconductor substrate 12 due to oxidation of the semiconductor substrate 12 is suppressed.

  Next, as shown in FIG. 8, by dry-etching the first insulating layer 40 and the second insulating layer 42, a part of the first insulating layer 40 and the second insulating layer 42 in the trench 22 is formed. Then, the first insulating layer 40 and the second insulating layer 42 on the upper surface 12a of the semiconductor substrate 12 are removed. At this time, as shown in FIG. 8, dry etching is performed so that the first insulating layer 40 and the second insulating layer 42 remain at the bottom of the trench 22. Since the etching rates of the first insulating layer 40 and the second insulating layer 42 are substantially equal, the upper surface of the first insulating layer 40 and the upper surface of the second insulating layer 42 remaining in the trench 22 are substantially flat. Note that the remaining first insulating layer 40 and second insulating layer 42 become the bottom insulating layer 24a shown in FIG.

  Next, by subjecting the semiconductor substrate 12 to a heat treatment, a sacrificial oxide film is formed on the inner surface of the trench 22 that is not covered with the first insulating layer 40 and the second insulating layer 42. This heat treatment is performed at substantially the same temperature as the densification step of the first insulating layer 40 and the densification step of the second insulating layer 42. Next, the sacrificial oxide film formed on the inner surface of the trench 22 is removed by wet etching. Thereby, the damaged layer formed on the inner surface of the trench 22 by the above-described dry etching is removed.

  Next, the semiconductor substrate 12 is annealed by nitriding. The nitridation annealing is performed at a temperature higher than the densification step of the first insulating layer 40 and the densification step of the second insulating layer 42. Thereafter, the MOSFET 10 shown in FIGS. 1 and 2 is completed by forming the side surface insulating film 24b, the gate electrode 26, the interlayer insulating film 28, the upper electrode 70, the lower electrode 72, and the like by a conventionally known method.

  In the manufacturing method of this embodiment, first, the first insulating layer 40 is formed on the inner surface of the trench 22 by CVD under a pressure of 150 Pa or more and 300 Pa or less, and then the first insulating layer 40 is heat-treated. As described above, since the first insulating layer 40 is formed under a relatively high pressure, the first insulating layer 40 is formed with a relatively uniform thickness on the inner surface of the trench 22. Then, by heat-treating the first insulating layer 40, the first insulating layer 40 is contracted and densified. After that, the second insulating layer 42 is formed by CVD under a pressure of 150 Pa or more and 300 Pa or less. Since the first insulating layer 40 has a relatively uniform thickness, the upper end of the trench 22 is not easily closed when the second insulating layer 42 is formed. Therefore, according to the manufacturing method of the present embodiment, when forming the second insulating layer 42, voids and seams are hardly generated inside the second insulating layer 42.

  Further, the first insulating layer 40 and the second insulating layer 42 are densified by heat treatment after their formation. Therefore, in the subsequent heat treatment of the semiconductor substrate 12 (that is, heat treatment for forming a sacrificial oxide film or nitridation annealing), the contraction of the first insulating layer 40 and the second insulating layer 42 is small, and the stress inside the trench 22 is reduced. Is unlikely to occur. Further, even when the bottom insulating layer 24a (that is, the first insulating layer 40 and the second insulating layer 42) becomes hot when the MOSFET 10 is used, stress does not easily occur in the bottom insulating layer 24a. Therefore, according to the manufacturing method of the present embodiment, cracks in the first insulating layer 40 and the second insulating layer 42 (that is, the bottom insulating layer 24a) formed in the trench 22 can be suppressed.

  In the above-described embodiment, the step of densifying the second insulating layer 42 is performed, but the step of densifying the second insulating layer 42 may not be performed. In such a configuration, since the second insulating layer 42 is not densified, if the temperature of the second insulating layer 42 subsequently becomes high, the second insulating layer 42 is likely to contract. However, even in such a configuration, since the first insulating layer 40 does not shrink and the second insulating layer 42 shrinks, the shrinkage is smaller than when the entire bottom insulating layer 24a shrinks. Therefore, stress generated in the bottom insulating layer 24a can be suppressed, and cracks in the bottom insulating layer 24a can be suppressed.

  In the above-described embodiment, the steps of densifying the first insulating layer 40 and the step of densifying the second insulating layer 42 are performed in a non-oxidizing atmosphere. May perform these steps in an oxidizing atmosphere.

  The technical elements disclosed in this specification are listed below. The following technical elements are each independently useful.

  In one example of the manufacturing method disclosed in this specification, before the second heat treatment step, the semiconductor substrate is heat-treated to contract the second insulating layer, and after the third heat treatment step. Before the second heat treatment step, the method may further include a step of etching the first insulating layer and the second insulating layer to leave the first insulating layer and the second insulating layer at the bottom of the trench. Good.

  In such a structure, the difference between the etching rate of the second insulating layer and the etching rate of the first insulating layer can be reduced by contracting the second insulating layer in the third heat treatment step. Therefore, when the first insulating layer and the second insulating layer are etched, the remaining upper surface of the first insulating layer and the upper surface of the second insulating layer can be made substantially flat.

  In the example manufacturing method disclosed in this specification, the first heat treatment step may be performed in a non-oxidizing atmosphere, and the third heat treatment step may be performed in a non-oxidizing atmosphere.

  In such a configuration, generation of defects in the semiconductor substrate due to oxidation of the semiconductor substrate is suppressed.

  As described above, specific examples of the present invention have been described in detail, but these are merely examples, and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in the present specification or the drawings simultaneously achieves a plurality of objects, and has technical utility by achieving one of the objects.

10: MOSFET
12: semiconductor substrate 12a: upper surface 12b: lower surface 22: trench 24: gate insulating layer 24a: bottom insulating layer 24b: side insulating film 26: gate electrode 28: interlayer insulating film 30: source region 32: body region 34: drift region 35 : Drain region 36: bottom region 40: first insulating layer 42: second insulating layer 70: upper electrode 72: lower electrode

Claims (3)

A method for manufacturing a semiconductor device, comprising:
Forming a first insulating layer on the inner surface of the trench formed on the upper surface of the semiconductor substrate by performing chemical vapor deposition under a pressure of 150 Pa or more and 300 Pa or less;
After forming the first insulating layer, heat-treating the semiconductor substrate to shrink the first insulating layer;
Forming a second insulating layer on the surface of the first insulating layer by performing chemical vapor deposition under a pressure of 150 Pa or more and 300 Pa or less after the first heat treatment step; Filling the trench by
A second heat treatment step of heat-treating the semiconductor substrate after forming the second insulating layer;
A production method comprising: A third heat treatment step of heat-treating the semiconductor substrate to shrink the second insulating layer before the second heat treatment step;
After the third heat treatment step and before the second heat treatment step, the first insulation layer and the second insulation layer are etched to form the first insulation layer and the second insulation layer at the bottom of the trench. Leaving the second insulating layer,
The production method according to claim 1, further comprising: Performing the first heat treatment step in a non-oxidizing atmosphere;
Performing the third heat treatment step in a non-oxidizing atmosphere;
The method according to claim 2.

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