CN103794482B - The forming method of metal gates - Google Patents
The forming method of metal gates Download PDFInfo
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- CN103794482B CN103794482B CN201210422991.3A CN201210422991A CN103794482B CN 103794482 B CN103794482 B CN 103794482B CN 201210422991 A CN201210422991 A CN 201210422991A CN 103794482 B CN103794482 B CN 103794482B
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 39
- 239000002184 metal Substances 0.000 title claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 180
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 229920005591 polysilicon Polymers 0.000 claims abstract description 57
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 48
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims description 45
- 239000007789 gas Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 8
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 239000002346 layers by function Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- 229910052715 tantalum Inorganic materials 0.000 description 2
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- 229910004143 HfON Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
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- 239000013039 cover film Substances 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
A kind of forming method of metal gates, including: Semiconductor substrate is provided；Interface material, high-K dielectric layer and polysilicon layer is sequentially formed at semiconductor substrate surface；Polysilicon layer surface is carried out the first nitrogen treatment, forms nitrogen silicon compound on polysilicon layer surface；After first nitrogen treatment, forming hard mask layer on the polysilicon layer, hard mask layer has the opening of the nitrogen silicon compound on exposed polysilicon layer surface；Etch described polysilicon layer, high-K dielectric layer and interface material along opening, form boundary layer, high-K gate dielectric layer and pseudo-grid；Forming interlayer dielectric layer at semiconductor substrate surface, the surface of interlayer dielectric layer flushes with pseudo-grid top surface；Remove dummy gate, form groove；Fill full metal in a groove, form metal gates.Nitrogen silicon compound can stop oxygen element to pass the pasc reaction formation silicon oxide of polysilicon layer and semiconductor substrate surface, makes the thickness of interface material keep constant.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly to the forming method of a kind of metal gates.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is more and more less,
In order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, high K gate dielectric layer and metal gate
The gate stack structure of pole is introduced in MOS transistor.Metal material pair in order to avoid metal gates
The impact of other structures of transistor, the gate stack structure of described metal gates and high K gate dielectric layer is generally adopted
Make by " rear grid (gate last) " technique.
Fig. 1 ~ Fig. 4 is that prior art uses " rear grid " technique to form the method cross-section structure signal of metal gates
Figure.Referring first to Fig. 1, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 sequentially forms
Interface material 101, high-K dielectric layer 102 and polysilicon layer 103；Described polysilicon layer 103 is formed hard
Mask layer 104, described hard mask layer 104 has the opening on exposed polysilicon layer 103 surface.Described boundary layer
The material of 101 is silicon oxide.
Then, refer to Fig. 2, with described hard mask layer 104 as mask, be sequentially etched described polysilicon layer
103, high-K dielectric layer 102 and interface material 101, is formed and is positioned at the interface in described Semiconductor substrate 100
Layer 105, it is positioned at the high-K gate dielectric layer 106 on boundary layer 105 surface, is positioned at high-K gate dielectric layer 106 surface
Pseudo-grid 107.
Then, refer to Fig. 3, remove shown hard mask layer 104(with reference to Fig. 2)；Serve as a contrast at described quasiconductor
Forming dielectric layer 108, the surface of dielectric layer 108 flushes with the surface of pseudo-grid 107 at the end 100.
Then, refer to Fig. 4, remove dummy gate 107(with reference to Fig. 3), form groove；In a groove
Fill full metal, form metal gates 109.
But, the thickness of the interface material (or boundary layer) that prior art is formed easily changes, shadow
Ring the stability of transistor.
More manufacture methods about metal gates, refer to U.S. of Publication No. US2002/0064964A1
State's patent.
Summary of the invention
The problem that the present invention solves is to improve the stability of transistor.
For solving the problems referred to above, technical solution of the present invention provides the forming method of a kind of metal gates, bag
Include: Semiconductor substrate is provided；Sequentially form interface material at described semiconductor substrate surface, high K is situated between
Matter layer and polysilicon layer；Described polysilicon layer surface is carried out the first nitrogen treatment, on polysilicon layer surface
Form nitrogen silicon compound；After first nitrogen treatment, form hard mask layer on the polysilicon layer, described firmly cover
Film layer has the opening of the nitrogen silicon compound on exposed polysilicon layer surface；Along opening etch described polysilicon layer,
High-K dielectric layer and interface material, formation is positioned at the boundary layer of semiconductor substrate surface, is positioned at boundary layer
On high-K gate dielectric layer and the pseudo-grid that are positioned in high-K dielectric layer；Formed at described semiconductor substrate surface
Interlayer dielectric layer, the surface of interlayer dielectric layer flushes with pseudo-grid top surface；Remove dummy gate, formed
Groove；Fill full metal in a groove, form metal gates.
Optionally, the material of described boundary layer is silicon oxide or silicon oxynitride.
Optionally, the thickness of described boundary layer is 5 ~ 30 angstroms.
Optionally, described first nitrogen treatment is the first annealing, is passed through gas NH during the first annealing3。
Optionally, the temperature of described first annealing is 300～1000 degrees Celsius, and the first annealing time is 5 ~ 200
Second, the pressure of the first annealing chamber is 0.5 ~ 780 torr.
Optionally, the gas being passed through during described first annealing also includes N2O。
Optionally, before forming interlayer dielectric layer, also include: dummy gate is carried out the second nitrogen treatment,
Sidewall surfaces in dummy gate forms nitrogen silicon compound.
Optionally, described second nitrogen treatment is the second annealing, is passed through gas NH during the second annealing3。
Optionally, the temperature of described second annealing is 300 ~ 1000 degrees Celsius, and the second annealing time is 5 ~ 200
Second, the pressure of the second annealing chamber is 0.5 ~ 780 torr.
Optionally, the gas being passed through during described second annealing also includes N2O。
Optionally, also include: form diffusion impervious layer on described high-K dielectric layer surface；Atmosphere at ammonia
In enclosing, described high-K dielectric layer and diffusion impervious layer are annealed.
Optionally, also include: the both sides sidewall in dummy gate forms side wall.
Optionally, also include: sidewall and lower surface at described groove form functional layer.
Compared with prior art, technical solution of the present invention has the advantage that
After forming polysilicon layer, described polysilicon layer is carried out the first nitrogen treatment, at polysilicon layer table
Face forms nitrogen silicon compound, owing to the consistency of nitrogen silicon compound is more than the consistency of polysilicon, therefore can
Effectively stop the oxygen element in air to arrive the surface of Semiconductor substrate through polysilicon layer, follow-up carry out
During various technique, prevent the oxygen element pasc reaction in an environment of high temperature with semiconductor substrate surface from forming oxygen
SiClx, oxide can make the thickness of interface material thickening, forms boundary layer at etching interface material layer
Time so that the thickness of boundary layer also can be thickening, and the actual (real) thickness of boundary layer goes out with the design thickness of boundary layer
Existing deviation, affects performance and the stable type of transistor.
Further, the temperature of described first annealing is 300 ~ 1000 degrees Celsius, and the first annealing time is 5 ~ 200
Second, the pressure of the first annealing chamber is 0.5 ~ 780 torr so that the first annealing forms nitrogen silicon compound thickness relatively
Thin, compactness is preferable, and covers the surface of polysilicon layer uniformly.
Further, carrying out the second nitrogen treatment, the sidewall surfaces in dummy gate forms relatively thin nitrogen silication
Compound, the nitrogen silicon compound of the sidewall surfaces of pseudo-grid and the nitrogen silicon compound of pseudo-grid top surface so that pseudo-
Grid are isolated with outside, follow-up when carrying out the higher process technique of temperature, such as: use depositing operation shape
When becoming side wall and dielectric layer, the oxygen element in environment is stoped to pass sidewall and the top surface arrival circle of pseudo-grid
The surface of the Semiconductor substrate under surface layer, in an environment of high temperature, with the pasc reaction shape in Semiconductor substrate
Silicon oxide is become to make the thickness of boundary layer thickening, the stability of the transistor that impact is formed.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of prior art metal gates forming process；
Fig. 5 ~ Figure 11 is the cross-sectional view of embodiment of the present invention metal gates forming process.
Detailed description of the invention
Inventor finds, prior art is when making metal gates, and the thickness of the boundary layer ultimately formed is total
It is thicker than the thickness of interface material so that the actual (real) thickness of boundary layer goes out with the design thickness of boundary layer
Existing deviation, affects performance and the stable type of transistor.
Inventor further study show that, existing interface material is formed typically by thermal oxidation technology,
After forming interface material, polysilicon layer, hard mask layer, dielectric layer etc. are all to be sunk by chemical gaseous phase
Long-pending technique is formed, and during chemical vapor deposition method, the temperature of deposition chambers is higher (500 ~ 800 degrees Celsius),
In an environment of high temperature, part oxygen element can pass polysilicon layer, hard mask layer arrives Semiconductor substrate
Surface, produces reaction with the silicon of semiconductor substrate surface and forms silicon oxide, so that interface material
Thickness is thickening.
For solving the problems referred to above, inventor proposes the forming method of a kind of metal gates, is forming polysilicon
After Ceng, described polysilicon layer is carried out the first nitrogen treatment, forms nitrogen silicon compound on polysilicon layer surface,
Owing to the consistency of nitrogen silicon compound is more than the consistency of polysilicon, therefore can effectively stop in air
Oxygen element arrives the surface of Semiconductor substrate through polysilicon layer, follow-up when carrying out various technique, makes interface
The thickness of material layer keeps constant or change is less.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.When describing the embodiment of the present invention in detail, for ease of saying
Bright, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it is at this
Should not limit the scope of the invention.Additionally, length, width and the degree of depth should be comprised in actual fabrication
Three-dimensional space.
Fig. 5 ~ Figure 11 is the cross-sectional view of embodiment of the present invention metal gates forming process.
With reference to Fig. 5, it is provided that Semiconductor substrate 300, described Semiconductor substrate 300 sequentially forms interface
Material layer 301, high-K dielectric layer 302 and polysilicon layer 303, described interface material 301 is positioned at partly leads
On body substrate 300, high-K dielectric layer 302 is positioned at interface material 301 surface, polysilicon layer 303
In high-K dielectric layer 302 surface.
The material of described interface material 301 is silicon oxide, and the formation process of interface material 301 is heat
Oxidation, the thickness of interface material 301 is 5 ~ 30 angstroms, and described interface material 301 is used for avoiding high K
Dielectric layer and the mismatch directly contacting generation lattice of raceway groove, reduce leakage current, additionally high K dielectric simultaneously
Layer 302 is in the better quality of interface material 301 growth.
In other embodiments of the invention, the material of described interface material is silicon oxynitride, interface material
The formation process of the bed of material is chemical gaseous phase deposition.
Described high-K dielectric layer 302 is subsequently used for being formed the high-K gate dielectric layer of transistor, high-K dielectric layer 302
Material is hafnium oxide (HfO2) the most optionally comprise other high dielectric constant materials, such as: TiO2、
HfZrO、Ta2O3、ZrO2Or ZrSiO2。
In other embodiments of the invention, after forming described high-K dielectric layer, also include: described
High-K dielectric layer surface forms diffusion impervious layer；To described high-K dielectric layer and diffusion in the atmosphere of ammonia
Anneal in barrier layer.Anneal in the atmosphere of ammonia in high-K dielectric layer, in high-K dielectric layer
Surface forms the compound of HfON, can effectively stop that extraneous oxygen element is by high-K dielectric layer diffusion half
The surface of conductor substrate, thus prevent interface material 301 thickening.
The material of described diffusion impervious layer is the single or multiple lift stacked structure of Ti, Ta, TiN, TaN.
Described polysilicon layer 303 is subsequently used for forming pseudo-grid.
The material of described Semiconductor substrate 300 can be monocrystal silicon (Si) or SiGe (GeSi), carborundum
(SiC)；Can also be silicon-on-insulator (SOI), germanium on insulator (GOI)；Or can also be its
Its material.Described Semiconductor substrate 300 can also according to design requirement inject certain dopant ion with
Change electrical parameter.It is also formed with fleet plough groove isolation structure in described Semiconductor substrate 300 (in figure not
Illustrate), described fleet plough groove isolation structure, for isolating different transistors, prevents electricity between different crystal pipe
Learn connect, the material of described fleet plough groove isolation structure can be silicon oxide, silicon nitride, silicon oxynitride wherein
One or more.
Then, refer to Fig. 6, described polysilicon layer 303 surface is carried out the first nitrogen treatment, at polycrystalline
Silicon layer 303 surface forms nitrogen silicon compound 304.
Described first nitrogen treatment is the first annealing, is passed through gas NH during the first annealing3, at the environment of high temperature
Under, NH3Pasc reaction with polysilicon layer 303 surface forms the nitrogen silicon compound 304 of one layer of thin layer, nitrogen silicon
Compound 304 thickness is 5 ~ 30 angstroms, and described nitrogen silicon compound 304 not only covers the top of polysilicon layer 303
Surface, portion also covers the sidewall surfaces of polysilicon layer 303, and described nitrogen silicon compound 304 is mainly composed of nitrogen
SiClx or silicon oxynitride or both mixture, owing to the consistency of nitrogen silicon compound 304 is higher than polycrystalline
The consistency of silicon layer 303, follow-up when carrying out the higher process technique of temperature, such as: follow-up to use chemistry
Gas-phase deposition forms hard mask layer and relevant etching technics, nitrogen silicon compound on polysilicon 303
304 can effectively stop the oxygen element in air to arrive quasiconductor through polysilicon layer 303 and high-K dielectric layer
The surface of substrate 300, in an environment of high temperature, prevents the silicon of oxygen element and Semiconductor substrate 300 surface
Reaction forms oxide, and oxide can make the thickness of interface material 301 thickening, subsequent etching interface
When material layer 301 forms boundary layer so that the thickness of boundary layer also can be thickening so that the reality of boundary layer
There is deviation with the design thickness of boundary layer in thickness, affects performance and the stable type of transistor.
The temperature of described first annealing is 300 ~ 1000 degrees Celsius, and the first annealing time is 5 ~ 200 seconds, the
The pressure of one annealing chamber is 0.5 ~ 780 torr so that the first annealing forms nitrogen silicon compound 304 thinner thickness,
Compactness is preferable, and covers the surface of polysilicon layer 303 uniformly, can more effective isolation from oxygen element.
The gas being passed through during described first annealing also includes N2O so that nitrogen silicon compound 304 is containing more
SiON, to strengthen the isolation effect of nitrogen silicon compound 304.
Then, refer to Fig. 7, to polysilicon layer 303(with reference to Fig. 6) carry out the first nitrogen treatment after,
Forming hard mask layer 305 on polysilicon layer 303, described hard mask layer 305 has exposed polysilicon layer
The opening of the nitrogen silicon compound 304 on 303 surfaces；With described hard mask layer 305 as mask, etch along opening
Described polysilicon layer 303, high-K dielectric layer 302 and interface material 301(are with reference to Fig. 6), form position
Boundary layer 306 in Semiconductor substrate 300 surface, the high-K gate dielectric layer 307 being positioned on boundary layer 306
With the pseudo-grid 308 being positioned in high-K dielectric layer 307.Remaining part nitrogen silicon compound 304 on pseudo-grid 308
A part as pseudo-grid 308.
The material of described hard mask layer 305 is amorphous carbon, SiN, SiON, SiCN, SiC or BN,
Hard mask layer 305 formation process is chemical vapor deposition method, and the opening in hard mask layer 305 passes through light
Carve and etching technics is formed.When forming hard mask layer 305, nitrogen silicon compound 304 can effectively stop
Oxygen element in air passes polysilicon layer 303.
The technique of etches polycrystalline silicon layer 303 is plasma etching, and the gas that plasma etching uses is
HBr and Cl2, owing to the nitrogen silicon compound 304 on polysilicon layer 303 surface is relatively thin, plasma etching energy
The etching nitrogen silicon compound being easier to, therefore without extra etch step to etch nitrogen silicon compound.
Then, refer to Fig. 8, dummy gate 308 is carried out the second nitrogen treatment, in dummy gate 308
Sidewall surfaces formed nitrogen silicon compound 309.Nitrogen silicon compound 309 is as a part for pseudo-grid 308.
Carrying out the second nitrogen treatment, the sidewall surfaces in dummy gate 308 forms relatively thin nitrogen silicon compound
309, the nitrogen silicon compound 309 of the sidewall surfaces of pseudo-grid 308 and the nitrogen silicon compound of pseudo-grid top surface
304 so that pseudo-grid are isolated with outside, follow-up when carrying out the higher process technique of temperature, such as: employing
Depositing operation forms side wall and during dielectric layer, stop oxygen element in environment through the sidewall of pseudo-grid 308 and
The surface of the Semiconductor substrate 300 under top surface arrival boundary layer 306, in an environment of high temperature, with
Pasc reaction in Semiconductor substrate 300 forms silicon oxide and makes the thickness of boundary layer 306 thickening, affects shape
The stability of the transistor become.
Described second nitrogen treatment is the second annealing, is passed through gas NH during the second annealing3, described second annealing
Temperature be 300 ~ 1000 degrees Celsius, the second annealing time is 5 ~ 200 seconds, second annealing chamber pressure
Being 0.5 ~ 780 torr, the gas being passed through during described second annealing also includes N2O, makes the sidewall table of pseudo-grid 308
The thinner thickness of the nitrogen silicon compound 309 that face is formed, compactness is preferable, and covers pseudo-grid 308 uniformly
The surface of sidewall.
Then, refer to Fig. 9, remove described hard mask layer 305(with reference to Fig. 8)；Serve as a contrast at described quasiconductor
Basal surface 300 forms interlayer dielectric layer 310, the surface of interlayer dielectric layer 310 and pseudo-grid 308 top surface
Flush.
The technique removing described hard mask layer 305 is dry or wet etch technique, removes hard mask layer 305
After, also include: the both sides sidewall in dummy gate 308 forms side wall (not shown)；With described puppet
Grid 308 and side wall are mask, and the Semiconductor substrate 300 of dummy gate 308 both sides is carried out ion implanting,
The source/drain region (not shown) of transistor is formed in the Semiconductor substrate 300 of pseudo-grid 308 both sides.
Finally, refer to Figure 10 and Figure 11, remove dummy gate 308(and include pseudo-grid 308 top surface
Nitrogen silicon compound 304 and the nitrogen silicon compound 309 of both sides sidewall surfaces), formed groove 311；Recessed
Functional layer 312 is formed on the sidewall of groove 311 and bottom；In groove 311, fill full metal, form metal gate
Pole.
The material of described functional layer 312 is Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN or TiAlN.
Described metal is Al, Cu, Ti, Ag, Au, Pt, Ni one of which or several
To sum up, the forming method of embodiment of the present invention metal gates, after forming polysilicon layer, to described
Polysilicon layer carries out the first nitrogen treatment, forms nitrogen silicon compound on polysilicon layer surface, due to nitrogen silication
The consistency of compound, more than the consistency of polysilicon, therefore can stop the oxygen element in air to pass effectively
Polysilicon layer arrives the surface of Semiconductor substrate, follow-up when carrying out various technique, prevents oxygen element at high temperature
In the environment of form silicon oxide with the pasc reaction of semiconductor substrate surface, oxide can make interface material
Thickness thickening, subsequent etching interface material formed boundary layer time so that the thickness of boundary layer also can become
Thick so that deviation occur in the actual (real) thickness of boundary layer and the design thickness of boundary layer, affect the property of transistor
Energy and stable type.
Further, the temperature of described first annealing is 300 ~ 1000 degrees Celsius, and the first annealing time is 5 ~ 200
Second, the pressure of the first annealing chamber is 0.5 ~ 780 torr so that the first annealing forms nitrogen silicon compound thickness relatively
Thin, compactness is preferable, and covers the surface of polysilicon layer uniformly.
Further, carrying out the second nitrogen treatment, the sidewall surfaces in dummy gate forms relatively thin nitrogen silication
Compound, the nitrogen silicon compound of the sidewall surfaces of pseudo-grid and the nitrogen silicon compound of pseudo-grid top surface so that pseudo-
Grid are isolated with outside, follow-up when carrying out the higher process technique of temperature, such as: use depositing operation shape
When becoming side wall and dielectric layer, the oxygen element in environment is stoped to pass sidewall and the top surface arrival circle of pseudo-grid
The surface of the Semiconductor substrate under surface layer, in an environment of high temperature, with the pasc reaction shape in Semiconductor substrate
Silicon oxide is become to make the thickness of boundary layer thickening, the stability of the transistor that impact is formed.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (12)
1. the forming method of a metal gates, it is characterised in that including:
Semiconductor substrate is provided；
Interface material, high-K dielectric layer and polysilicon layer is sequentially formed at described semiconductor substrate surface；
Described polysilicon layer surface is carried out the first nitrogen treatment, forms nitrogen silication on polysilicon layer surface and close
Thing；
After first nitrogen treatment, forming hard mask layer on the polysilicon layer, it is many that described hard mask layer has exposure
The opening of the nitrogen silicon compound on crystal silicon layer surface；
Etch described polysilicon layer, high-K dielectric layer and interface material along opening, formed and be positioned at quasiconductor lining
The boundary layer of basal surface, the high-K gate dielectric layer being positioned on boundary layer and the pseudo-grid being positioned in high-K dielectric layer；
Dummy gate is carried out the second nitrogen treatment, and the sidewall surfaces in dummy gate forms nitrogen silicon compound；
Interlayer dielectric layer, the surface of interlayer dielectric layer and pseudo-grid top table is formed at described semiconductor substrate surface
Face flushes；
Remove dummy gate, form groove；
Fill full metal in a groove, form metal gates.
2. the forming method of metal gates as claimed in claim 1, it is characterised in that the material of described boundary layer
Material is silicon oxide or silicon oxynitride.
3. the forming method of metal gates as claimed in claim 1, it is characterised in that the thickness of described boundary layer
Degree is 5～30 angstroms.
4. the forming method of metal gates as claimed in claim 1, it is characterised in that at described first nitridation
Reason is the first annealing, is passed through gas NH during the first annealing3。
5. the forming method of metal gates as claimed in claim 4, it is characterised in that described first annealing
Temperature is 300～1000 degrees Celsius, and the first annealing time is 5～200 seconds, and the pressure of the first annealing chamber is
0.5～780 torr.
6. the forming method of metal gates as claimed in claim 4, it is characterised in that during described first annealing
The gas being passed through also includes N2O。
7. the forming method of metal gates as claimed in claim 1, it is characterised in that at described second nitridation
Reason is the second annealing, is passed through gas NH during the second annealing3。
8. the forming method of metal gates as claimed in claim 7, it is characterised in that described second annealing
Temperature is 300～1000 degrees Celsius, and the second annealing time is 5～200 seconds, and the pressure of the second annealing chamber is
0.5～780 torr.
9. the forming method of metal gates as claimed in claim 7, it is characterised in that during described second annealing
The gas being passed through also includes N2O。
10. the forming method of metal gates as claimed in claim 1, it is characterised in that also include: described
High-K dielectric layer surface forms diffusion impervious layer；To described high-K dielectric layer and diffusion in the atmosphere of ammonia
Anneal in barrier layer.
The forming method of 11. metal gates as claimed in claim 1, it is characterised in that also include: described
The both sides sidewall of pseudo-grid forms side wall.
The forming method of 12. metal gates as claimed in claim 1, it is characterised in that also include: described
The sidewall of groove and lower surface form functional layer.
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| CN105826260B (en) * | 2015-01-08 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN105206523A (en) * | 2015-10-14 | 2015-12-30 | 上海华力微电子有限公司 | Method for manufacturing high-K dielectric layer |
| CN106298491B (en) * | 2016-11-09 | 2019-03-26 | 上海华力微电子有限公司 | A kind of forming method of high-K metal gate |
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| US6093590A (en) * | 1999-09-14 | 2000-07-25 | Worldwide Semiconductor Manufacturing Corp. | Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant |
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| US7381619B2 (en) * | 2004-04-27 | 2008-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual work-function metal gates |
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