CN106298491B - A kind of forming method of high-K metal gate - Google Patents
A kind of forming method of high-K metal gate Download PDFInfo
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- CN106298491B CN106298491B CN201610984923.4A CN201610984923A CN106298491B CN 106298491 B CN106298491 B CN 106298491B CN 201610984923 A CN201610984923 A CN 201610984923A CN 106298491 B CN106298491 B CN 106298491B
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- forming method
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- film layer
- metal gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
Abstract
The present invention provides a kind of forming methods of high-K metal gate, comprising: first step: sequentially forming interlayer dielectric layer, TiO2 film layer and polysilicon layer on substrate；Second step: dummy gate structure is patterned to form to interlayer dielectric layer, TiO2 film layer and polysilicon layer, and forms grid curb wall in dummy gate structure side；Third step: inter-level dielectric material is deposited around dummy gate structure, and inter-level dielectric material is planarized；Four steps: the top polysilicon silicon layer in removal dummy gate structure is to form groove；5th step: Hf ion implanting is carried out to the TiO2 film layer in dummy gate structure, to form HfTiO film layer；6th step: metal material is filled in a groove to form metal gates.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of high K (high dielectric constant) metal
The forming method of grid.
Background technique
Traditionally active area activation thermal anneal process (S/D active is placed in the growth of high K film and metal gates
Anneal during the technique after) integrates, dummy grid polysilicon and dummy grid oxide are finally all removed.Removing pseudo- grid
It will lead to channel surface roughness during the oxide of pole to become larger, while during etching, either dry etching is also
It is wet etching, can all introduces the objectionable impurities ion of such as F ion or the like.These ions are diffused into channel, to device
Reliability cause to seriously affect.High K film can will almost reduce 4nm in side wall deposition, the fillable gap of grid simultaneously,
Considerably increase the risk that metal empty (metal void) generates.
Accordingly, it is desirable to be able to a kind of critical size that can be improved grid and can be filled be provided, to be conducive to eliminate metal
The high-K metal gate forming method in cavity.
Summary of the invention
The technical problem to be solved by the present invention is to for drawbacks described above exists in the prior art, providing one kind can be improved
The fillable critical size of grid, to be conducive to eliminate the high-K metal gate forming method in metal cavity.
In order to achieve the above technical purposes, according to the present invention, a kind of forming method of high-K metal gate is provided, comprising: the
One step: interlayer dielectric layer, TiO2 film layer and polysilicon layer are sequentially formed on substrate；Second step: to interlayer dielectric layer,
TiO2 film layer and polysilicon layer are patterned to form dummy gate structure, and form gate electrode side in dummy gate structure side
Wall；Third step: inter-level dielectric material is deposited around dummy gate structure, and inter-level dielectric material is planarized；
Four steps: the top polysilicon silicon layer in removal dummy gate structure is to form groove；5th step: in dummy gate structure
TiO2 film layer carries out Hf ion implanting, to form HfTiO film layer；6th step: metal material is filled in a groove with shape
At metal gates.
Preferably, interlayer dielectric layer is SiO2 film layer.Preferably, the growth pattern of interlayer dielectric layer can be chemical gas
Mutually deposition, atomic layer deposition, thermal oxide, low-pressure chemical vapor deposition etc., the preferably thermal oxidation process of boiler tube.Preferably, interlayer is situated between
Matter layer with a thickness of 0.5~1nm.
Preferably, the growth pattern of TiO2 film layer can be chemical vapor deposition, atomic layer deposition, thermal oxide, low pressure
Learn vapor deposition etc..Preferably, TiO2 film layer with a thickness of 0.5~2nm.
Preferably, the energy of Hf ion implanting is 1~10Kev.Preferably, the incident angle of Hf ion implanting is vertically to enter
It penetrates.
Preferably, the rapid thermal annealing or peak value annealing that the thermal annealing after ion implanting is 800~1000 DEG C.It is preferred that
Ground, the locating atmosphere after ion implanting can be N2Or other inert gas atmospheres.
The forming method of high-K metal gate according to the present invention forms high K by ion implanting without removing gate oxide
Film increases fillable critical size because side wall does not have high K film, is conducive to eliminate metal cavity.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 schematically shows the first step of the forming method of high-K metal gate according to the preferred embodiment of the invention.
Fig. 2 schematically shows the second steps of the forming method of high-K metal gate according to the preferred embodiment of the invention.
Fig. 3 schematically shows the third step of the forming method of high-K metal gate according to the preferred embodiment of the invention.
Fig. 4 schematically shows the four steps of the forming method of high-K metal gate according to the preferred embodiment of the invention.
Fig. 5 schematically shows the 5th step of the forming method of high-K metal gate according to the preferred embodiment of the invention.
Fig. 6 schematically shows the 6th step of the forming method of high-K metal gate according to the preferred embodiment of the invention.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that indicating that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to keep the contents of the present invention more clear and understandable, combined with specific embodiments below with attached drawing in of the invention
Appearance is described in detail.
Fig. 1 to Fig. 6 schematically shows each of the forming method of high-K metal gate according to the preferred embodiment of the invention
Step.
Specifically, as shown in Figures 1 to 6, the forming method of high-K metal gate according to the preferred embodiment of the invention includes:
First step: interlayer dielectric layer 10, TiO2 film layer 20 and polysilicon layer 30 are sequentially formed on substrate 100；
Preferably, interlayer dielectric layer 10 is SiO2 film layer.Preferably, the growth pattern of interlayer dielectric layer 10 can be change
Learn vapor deposition, atomic layer deposition, thermal oxide, low-pressure chemical vapor deposition etc., the preferably thermal oxidation process of boiler tube.Preferably, layer
Between dielectric layer 10 with a thickness of 0.5~1nm.
Preferably, the growth pattern of TiO2 film layer 20 can be chemical vapor deposition, atomic layer deposition, thermal oxide, low pressure
Chemical vapor deposition etc..Preferably, TiO2 film layer 20 with a thickness of 0.5~2nm.
Second step: pseudo- grid are patterned to form to interlayer dielectric layer 10, TiO2 film layer 20 and polysilicon layer 30
Pole structure 40, and grid curb wall 41 is formed in 40 side of dummy gate structure；
Third step: inter-level dielectric material 50 is deposited around dummy gate structure 40, and to inter-level dielectric material 50
It is planarized；
Four steps: the top polysilicon silicon layer in removal dummy gate structure 40 is to form groove 31；
5th step: Hf ion implanting is carried out to the TiO2 film layer 20 in dummy gate structure 40, to form HfTiO film
Layer 21；Preferably, thermal anneal process further is implemented to HfTiO film layer 21 in the 5th step.
Preferably, the energy of Hf ion implanting is 1~10Kev.Preferably, the incident angle of Hf ion implanting is vertically to enter
It penetrates.
Preferably, the rapid thermal annealing or peak value annealing (spike that the thermal annealing after ion implanting is 800~1000 DEG C
anneal).Preferably, the locating atmosphere after ion implanting can be N2Or other inert gas atmospheres.
6th step: metal material is filled in groove 31 to form metal gates 60.
The forming method of high-K metal gate according to the preferred embodiment of the invention passes through ion without removing gate oxide
Injection forms high K film, because side wall does not have high K film, increases fillable critical size, is conducive to eliminate metal
Cavity.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two ", the descriptions such as " third " are used only for distinguishing various components, element, the step etc. in specification, each without being intended to indicate that
Component, element, the logical relation between step or ordinal relation etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
And it should also be understood that the present invention is not limited thereto and locate the specific method described, compound, material, system
Technology, usage and application are made, they can change.It should also be understood that term described herein be used merely to describe it is specific
Embodiment, rather than be used to limit the scope of the invention.Must be noted that herein and appended claims used in
Singular "one", "an" and "the" include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
The citation of multiple steps or device, and may include secondary step and second unit.It should be managed with broadest meaning
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as the function of also quoting from the structure
Equivalent.It can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Moreover, the realization of the method and/or system of the embodiment of the present invention may include manual, automatic or selected by executing in combination
Task.Moreover, according to the method for the present invention and/or the real instrument and equipment of the embodiment of system, it is logical using operating system
It crosses hardware, software, or its combination and realizes several selected tasks.
Claims (10)
1. a kind of forming method of high-K metal gate, characterized by comprising:
First step: interlayer dielectric layer, TiO are sequentially formed on substrate2Film layer and polysilicon layer；
Second step: to interlayer dielectric layer, TiO2Film layer and polysilicon layer are patterned to form dummy gate structure, and
And grid curb wall is formed in dummy gate structure side；
Third step: inter-level dielectric material is deposited around dummy gate structure, and inter-level dielectric material is planarized；
Four steps: the top polysilicon silicon layer in removal dummy gate structure is to form groove；
5th step: to the TiO in dummy gate structure2Film layer carries out Hf ion implanting, to form HfTiO film layer；
6th step: metal material is filled in a groove to form metal gates.
2. the forming method of high-K metal gate according to claim 1, which is characterized in that further right in the 5th step
HfTiO film layer 21 implements thermal anneal process.
3. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that interlayer dielectric layer SiO2
Film layer.
4. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that the growth side of interlayer dielectric layer
Formula is thermal oxidation process.
5. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that interlayer dielectric layer with a thickness of
0.5~1nm.
6. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that TiO2The growth of film layer
Mode is one of chemical vapor deposition, atomic layer deposition, thermal oxide, low-pressure chemical vapor deposition.
7. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that TiO2The thickness of film layer
For 0.5~2nm.
8. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that the energy of Hf ion implanting is
1~10Kev.
9. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that the incidence angle of Hf ion implanting
Degree is vertical incidence.
10. the forming method of high-K metal gate according to claim 1 or 2, which is characterized in that the heat after ion implanting is moved back
Fire is annealed for 800~1000 DEG C of rapid thermal annealing or peak value, and the locating atmosphere inert gas gas after ion implanting
Atmosphere.
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| CN201610984923.4A CN106298491B (en) | 2016-11-09 | 2016-11-09 | A kind of forming method of high-K metal gate |
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| CN201610984923.4A CN106298491B (en) | 2016-11-09 | 2016-11-09 | A kind of forming method of high-K metal gate |
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| CN106298491A CN106298491A (en) | 2017-01-04 |
| CN106298491B true CN106298491B (en) | 2019-03-26 |
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| CN113517334A (en) * | 2021-06-07 | 2021-10-19 | 西安电子科技大学 | Power MOSFET device with high-K dielectric groove and preparation method thereof |
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| US7195999B2 (en) * | 2005-07-07 | 2007-03-27 | Micron Technology, Inc. | Metal-substituted transistor gates |
| US8492852B2 (en) * | 2010-06-02 | 2013-07-23 | International Business Machines Corporation | Interface structure for channel mobility improvement in high-k metal gate stack |
| CN102810467A (en) * | 2012-08-16 | 2012-12-05 | 上海华力微电子有限公司 | Metal gate forming method |
| CN103794482B (en) * | 2012-10-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of metal gates |
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