CN102810467A - Metal gate forming method - Google Patents
Metal gate forming method Download PDFInfo
- Publication number
- CN102810467A CN102810467A CN2012102926246A CN201210292624A CN102810467A CN 102810467 A CN102810467 A CN 102810467A CN 2012102926246 A CN2012102926246 A CN 2012102926246A CN 201210292624 A CN201210292624 A CN 201210292624A CN 102810467 A CN102810467 A CN 102810467A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- amorphous carbon
- formation method
- cesl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a metal gate forming method. A polycrystalline silicon layer is replaced by an amorphous carbon layer used as a sacrifice layer in the metal gate forming process, so that damage of a substrate can be avoided when the amorphous carbon layer is removed by oxygen after the a metal gate is formed. Further, a laminated structure of an initial oxide layer and a high-K dielectric layer has high thermal stability and mechanical strength and is used for replacing an existing gate dielectric layer to further replace existing silicon dioxide, so that lower leakage current can be obtained.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of metal gates formation method.
Background technology
Along with the raising of integrated level in the integrated circuit, the characteristic size of semiconductor fabrication process is also more and more littler, and traditional polysilicon gate is substituted by metal gates because of the defective of its electrical property gradually.In 32 nanometers and following technology, grid structure basically all adopts metal level as grid, to satisfy the requirement of device electrical performance.
The technology of existing preparation metal gates; Generally be to prepare polysilicon gate construction with traditional handicraft earlier; Formation source/drain electrode and behind the interlayer dielectric layer that forms on the substrate with the polysilicon gate construction flush in substrate; Polysilicon gate is removed, formed high-k gate dielectric layer and metal level successively in the place at former polysilicon gate place; Last grinding metal layer forms metal gates to exposing interlayer dielectric layer.For example, notification number comprises the steps: at first for the Chinese patent of " CN100364058C " discloses a kind of metal gates formation method, in substrate, forms gate dielectric layer; Then, on said gate dielectric layer, form patterned polysilicon layer; Then, formation is around the side wall of said patterned polysilicon layer; Then, form the interlayer dielectric layer that covers said patterned polysilicon layer and side wall; Then, the said interlayer dielectric layer of planarization and expose said patterned polysilicon layer; Then, remove said patterned polysilicon layer, in said interlayer dielectric layer, form groove; At last, form the metal level of filling said groove and covering said interlayer dielectric layer.
Yet; Said method adopts dry etch process usually when removing patterned polysilicon layer, between said polysilicon layer and substrate, accompany gate dielectric layer even cause; Because said gate dielectric layer is thinner; And be difficult to control the etching selection ratio between said polysilicon layer, gate dielectric layer and the substrate, plasma related in the said dry etch process causes the substrate surface damage of carrying said metal gates in the process of removing said patterned polysilicon layer.Thereby the damage that how to reduce said substrate surface becomes the technical problem that those skilled in the art need to be resolved hurrily.
Summary of the invention
The present invention provides a kind of metal gates formation method, to reduce the damage of substrate surface.
For solving the problems of the technologies described above, the present invention provides a kind of metal gates formation method, comprising:
On substrate, form initial oxide layer and high K dielectric layer successively;
On said high K dielectric layer, form amorphous carbon layer;
On said amorphous carbon layer, form patterned photoresist layer; And
With said patterned photoresist layer is mask, and the said amorphous carbon layer of etching, high K dielectric layer and initial oxide layer form stacked structure.
Optional, form after the stacked structure, also comprise:
Form side wall, and in said substrate, form source electrode and drain electrode around said stacked structure;
In said source electrode and drain electrode, form metal silicide layer;
On said substrate, form the CESL stressor layers and carry out annealing process;
On said CESL stressor layers, form interlayer dielectric layer;
The said interlayer dielectric layer of planarization is until the CESL stressor layers that exposes said stacked structure end face;
Remove the CESL stressor layers of said stacked structure end face;
Remove said amorphous carbon layer, in said interlayer dielectric layer, form groove; And
Form the metal level of filling said groove and covering said interlayer dielectric layer.
Optional, the thickness of said initial oxide layer is less than or equal to 10nm.
Optional, said high K dielectric layer is hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide.
Optional, said CESL stressor layers is a stressed silicon nitride layers.
Optional, adopt wet-etching technology to remove said CESL stressor layers.
Optional, said annealing process is rapid thermal annealing or laser pulse annealing process.
Optional, adopt oxygen ashing process to remove said amorphous carbon layer.
Optional, before forming patterned photoresist layer on the said amorphous carbon layer, also comprise: on said amorphous carbon layer, form ARC.
Compared with prior art, metal gates formation method provided by the invention has the following advantages:
1, the present invention adopts amorphous carbon layer to replace polysilicon layer as the sacrifice layer in the metal gates forming process, makes when oxygen capable of using is removed said amorphous carbon layer after forming said metal gates, avoids the damage to said substrate;
2, the present invention adopts the laminated construction of initial oxide layer and high K dielectric layer to replace existing gate dielectric layer to replace existing silicon dioxide; The laminated construction of said initial oxide layer and high K dielectric layer has thermal stability and mechanical strength preferably, can obtain littler leakage current;
3, the present invention forms CESL stressor layers and interlayer dielectric layer after forming metal silicide layer; And the planarization interlayer dielectric layer is until the CESL stressor layers that exposes the stacked structure end face; Remove the CESL stressor layers of said stacked structure end face subsequently, so, stress memory technique is applied in the manufacture process of metal gates; The stress of memory in grid structure still can be transmitted among the raceway groove, helps improving carrier mobility.
Description of drawings
Fig. 1 is the schematic flow sheet of the metal gates formation method of one embodiment of the invention;
Fig. 2 to Figure 12 is that the metal gates of one embodiment of the invention forms the device profile structural representation in the procedure.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that broad to those skilled in the art, and not as limitation of the present invention.
For clear, whole characteristics of practical embodiments are not described.In following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development possibly be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to description and claims advantage of the present invention and characteristic.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 1, the metal gates formation method of one embodiment of the invention comprises the steps:
Step S1: on substrate, form initial oxide layer and high K dielectric layer successively;
Step S2: on said high K dielectric layer, form amorphous carbon layer;
Step S3: on said amorphous carbon layer, form patterned photoresist layer;
Step S4: with said patterned photoresist layer is mask, and the said amorphous carbon layer of etching, high K dielectric layer and initial oxide layer form stacked structure;
Step S5: form side wall, and in said substrate, form source electrode and drain electrode around said stacked structure;
Step S6: in said source electrode and drain electrode, form metal silicide layer;
Step S7: on said substrate, form the CESL stressor layers and carry out annealing process;
Step S8: on said CESL stressor layers, form interlayer dielectric layer;
Step S9: the planarization interlayer dielectric layer is until the CESL stressor layers that exposes said stacked structure end face;
Step S10: the CESL stressor layers of removing said stacked structure end face;
Step S11: remove said amorphous carbon layer, in said interlayer dielectric layer, form groove; And
Step S12: form the metal level of filling said groove and covering said interlayer dielectric layer.
Be example to form the CMOS transistor below, more specify metal gates formation method of the present invention in conjunction with Fig. 2 to Figure 12.
As shown in Figure 2, at first, execution in step S1 provides the substrate 100 that comprises first area 100a and second area 100b, and on substrate 100, forms initial oxide layer 110 and high K dielectric layer 120 successively.
Said substrate 100 comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Said first area 100a is in order to form the PMOS transistor, and said second area 100b is in order to form nmos pass transistor, and vice versa.Can also be formed with dopant well in the said substrate 100, wherein, said dopant well ion implantation technology capable of using is accomplished, and the dopant well of said P type or N type is used to form the conducting channel of NMOS or PMOS.With NMOS is example, and said dopant well is the P type, and this dopant well is not shown.In addition, also be formed with fleet plough groove isolation structure in the said substrate 100, in order to isolate active area.
Said initial oxide layer 110 can adopt thermal oxidation process, chemical gaseous phase depositing process or ozone process method to form.Form after the initial oxide layer 110, on said interface oxide layer 207, form high K dielectric layer 204.The thickness range of said high K dielectric layer 204 is 10 ~ 100 dusts.The material of said high K dielectric layer can be hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide etc.
Along with the integrated circuit characteristic size is contracted to the field of deep-submicron, transistorized grid size dwindles, and correspondingly the thickness as the silicon dioxide layer of gate dielectric layer also need reduce, and to improve transistorized grid capacitance, prevents that short-channel effect from appearring in device.But when gate dielectric layer thickness dwindles gradually; The thickness of gate dielectric layer is decreased to below 3 nanometers; Produce a lot of problems, for example: leakage current increases, diffusion of impurities, promptly has the impurity concentration gradient between gate dielectric layer and the substrate thereupon; Said impurity can be diffused in the substrate from grid or be fixed in the gate dielectric layer, finally influences the performance of device.Therefore, the present invention adopts the laminated construction of initial oxide layer and high K dielectric layer to replace existing gate dielectric layer to replace existing silicon dioxide.The laminated construction of said initial oxide layer and high K dielectric layer has thermal stability and mechanical strength preferably, can obtain littler leakage current, and can keep the electric capacity of gate dielectric layer constant.
As shown in Figure 3, then, execution in step S2 forms amorphous carbon layer 130 on said high K dielectric layer 120, and said amorphous carbon layer 130 can adopt the mode of PECVD to form.
As shown in Figure 4, then, execution in step S3 through technologies such as gluing, exposure and developments, forms patterned photoresist layer 140 on said amorphous carbon layer 130.
As shown in Figure 5, then, execution in step S4 is a mask with said patterned photoresist layer 140, and the said amorphous carbon layer of etching 130, high K dielectric layer 120 and initial oxide layer 110 form stacked structure 200.In the present embodiment, said patterned photoresist layer 140 is consumed simultaneously, and certainly, extra step also capable of using is removed said patterned photoresist layer 140.
As shown in Figure 6, then, execution in step S5 forms the side wall 150 around said stacked structure 200, and in the 100a of the first area of said substrate 100, forms source electrode, drain electrode 101, in the second area 100b of said substrate 100, forms source electrode, drain electrode 102.
As shown in Figure 7, then, execution in step S6 forms metal silicide layer 160 in said source electrode and drain electrode.Said metal silicide layer 160 can form through following steps: at first, on first area 100a and second area 100b, form metal barrier layer film (SAB); Then, the metal barrier layer film on selective etch falls source electrode and drains; Then, nickel deposited (Ni) or cobalt (Co) metal; Next, carry out annealing process forming metal silicide layer 160, said annealing process can be divided into repeatedly and carrying out, and for example, can be divided into twice annealing technology; At last, remove said metal barrier layer film.
As shown in Figure 8, then, execution in step S7 forms CESL stressor layers 170 and carries out annealing process on said substrate 100.Said CESL stressor layers 170 covers said first area 100a, second area 100b and stacked structure 200.Said CESL stressor layers 170 for example is a stressed silicon nitride layers.Said CESL stressor layers 170 is preferably stressed silicon nitride layers, and it has good stress effect, and the thickness of said CESL stressor layers 170 is the 30-60 nanometer for example, and said annealing process for example is rapid thermal annealing (RTA) or laser pulse annealing (LSA) technology.In annealing process, can produce stress, these stress can be memorized, and the stress of memory in grid structure still can be transmitted among the raceway groove, helps improving carrier mobility.
Continue with reference to shown in Figure 8, then, execution in step S8 forms interlayer dielectric layer 180 on said CESL stressor layers 170.Said interlayer dielectric layer 180 can adopt PECVD (plasma enhanced CVD), SACVD (inferior normal pressure chemical vapor deposition) or LPCVD technologies such as (low-pressure chemical vapor phase depositions) to form.Said inter-level dielectric layer material comprises but is not limited to phosphorosilicate glass (phosphosilicateglass; PSG), Pyrex (borosilicate; BSG), boron-phosphorosilicate glass (borophosphosilicate, BPSG), fluorine silex glass (FSG) or have a kind of or its combination in the advanced low-k materials.Said have advanced low-k materials include but not limited to black diamond (Black Diamond, BD) or coral etc.
As shown in Figure 9, then, execution in step S9, planarization interlayer dielectric layer 180 is until the CESL stressor layers 170 that exposes said amorphous carbon layer end face.Preferable, also can carry out extra etching technics to remove the residual interlayer dielectric layer of stacked structure 200 end faces after the said interlayer dielectric layer 180 of planarization.
Shown in figure 10, then, execution in step S10 adopts wet-etching technology, for example, adopts the CESL stressor layers of the said amorphous carbon layer end face of hot phosphoric acid (HPO) solution removal.
Shown in figure 11, then, execution in step S11 adopts oxygen ashing process to remove said amorphous carbon layer, in said inter-level dielectric 180, forms groove 181.
Shown in figure 12, last, execution in step S12 form the metal level 190 of filling said groove 181 and covering said interlayer dielectric layer 180, and planarization makes said metal level 190.Said metal level 190 comprises metal, metal alloy, metal silicide, metal alloy silicide, contain the conductive oxide of metal or contain the conductive silicide of metal, and wherein metal is from by a kind of or its combination Al, Co, Cr, Fe, h, h, Hf, Mg, Mo, Mn, N1Pd, Pt, La, Os, Nb, Rh, Re, Ru, Sn, Ta, Ti, V, W, Y and the Zr.Can adopt galvanoplastic or physical gas-phase deposition to form said metal level.
In sum, metal gates formation method provided by the invention has the following advantages:
1, the present invention adopts amorphous carbon layer to replace polysilicon layer as the sacrifice layer in the metal gates forming process, makes when oxygen capable of using is removed said amorphous carbon layer after forming said metal gates, avoids the damage to said substrate;
2, the present invention adopts the laminated construction of initial oxide layer and high K dielectric layer to replace existing gate dielectric layer to replace existing silicon dioxide; The laminated construction of said initial oxide layer and high K dielectric layer has thermal stability and mechanical strength preferably, can obtain littler leakage current;
3, after forming metal silicide layer, form CESL stressor layers and interlayer dielectric layer; And the said interlayer dielectric layer of planarization is until the CESL stressor layers that exposes the stacked structure end face; Remove the CESL stressor layers of said stacked structure end face subsequently, so, stress memory technique is applied in the manufacture process of metal gates; The stress of memory in grid structure still can be transmitted among the raceway groove, helps improving carrier mobility.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.
Claims (9)
1. metal gates formation method comprises:
On substrate, form initial oxide layer and high K dielectric layer successively;
On said high K dielectric layer, form amorphous carbon layer;
On said amorphous carbon layer, form patterned photoresist layer; And
With said patterned photoresist layer is mask, and the said amorphous carbon layer of etching, high K dielectric layer and initial oxide layer form stacked structure.
2. metal gates formation method as claimed in claim 1 is characterized in that, forms after the stacked structure, also comprises:
Form side wall, and in said substrate, form source electrode and drain electrode around said stacked structure;
In said source electrode and drain electrode, form metal silicide layer;
On said substrate, form the CESL stressor layers and carry out annealing process;
On said CESL stressor layers, form interlayer dielectric layer;
The said interlayer dielectric layer of planarization is until the CESL stressor layers that exposes said stacked structure end face;
Remove the CESL stressor layers of said stacked structure end face;
Remove said amorphous carbon layer, in said interlayer dielectric layer, form groove; And
Form the metal level of filling said groove and covering said interlayer dielectric layer.
3. metal gates formation method as claimed in claim 1 is characterized in that the thickness of said initial oxide layer is less than or equal to 10nm.
4. metal gates formation method as claimed in claim 1 is characterized in that, said high K dielectric layer is hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide.
5. metal gates formation method as claimed in claim 1 is characterized in that, said CESL stressor layers is a stressed silicon nitride layers.
6. metal gates formation method as claimed in claim 5 is characterized in that, adopts wet-etching technology to remove said CESL stressor layers.
7. metal gates formation method as claimed in claim 1 is characterized in that, said annealing process is rapid thermal annealing or laser pulse annealing process.
8. metal gates formation method as claimed in claim 1 is characterized in that, adopts oxygen ashing process to remove said amorphous carbon layer.
9. metal gates formation method as claimed in claim 1 is characterized in that, before forming patterned photoresist layer on the said amorphous carbon layer, also comprises: on said amorphous carbon layer, form ARC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012102926246A CN102810467A (en) | 2012-08-16 | 2012-08-16 | Metal gate forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012102926246A CN102810467A (en) | 2012-08-16 | 2012-08-16 | Metal gate forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102810467A true CN102810467A (en) | 2012-12-05 |
Family
ID=47234149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012102926246A Pending CN102810467A (en) | 2012-08-16 | 2012-08-16 | Metal gate forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102810467A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103058127A (en) * | 2012-12-14 | 2013-04-24 | 上海集成电路研发中心有限公司 | Surface treatment method of micro-strip |
| CN105632906A (en) * | 2014-10-27 | 2016-06-01 | 中国科学院微电子研究所 | Self-aligned contact manufacture method |
| CN106298491A (en) * | 2016-11-09 | 2017-01-04 | 上海华力微电子有限公司 | A kind of forming method of high-K metal gate |
| CN108400116A (en) * | 2017-02-04 | 2018-08-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593686A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Metal gates formation method |
| CN101728330A (en) * | 2008-11-03 | 2010-06-09 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
| CN102034758A (en) * | 2009-10-07 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Method for fabricating integrated circuit component |
| US8211775B1 (en) * | 2011-03-09 | 2012-07-03 | United Microelectronics Corp. | Method of making transistor having metal gate |
-
2012
- 2012-08-16 CN CN2012102926246A patent/CN102810467A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593686A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Metal gates formation method |
| CN101728330A (en) * | 2008-11-03 | 2010-06-09 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
| CN102034758A (en) * | 2009-10-07 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Method for fabricating integrated circuit component |
| US8211775B1 (en) * | 2011-03-09 | 2012-07-03 | United Microelectronics Corp. | Method of making transistor having metal gate |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103058127A (en) * | 2012-12-14 | 2013-04-24 | 上海集成电路研发中心有限公司 | Surface treatment method of micro-strip |
| CN103058127B (en) * | 2012-12-14 | 2017-02-08 | 上海集成电路研发中心有限公司 | Surface treatment method of micro-strip |
| CN105632906A (en) * | 2014-10-27 | 2016-06-01 | 中国科学院微电子研究所 | Self-aligned contact manufacture method |
| CN105632906B (en) * | 2014-10-27 | 2019-10-29 | 中国科学院微电子研究所 | Self-aligned contacts manufacturing method |
| CN106298491A (en) * | 2016-11-09 | 2017-01-04 | 上海华力微电子有限公司 | A kind of forming method of high-K metal gate |
| CN108400116A (en) * | 2017-02-04 | 2018-08-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN108400116B (en) * | 2017-02-04 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2463897B1 (en) | Integrating n-type and p-type metal gate field effect transistors | |
| TW523914B (en) | Dual metal gate CMOS devices and method for making the same | |
| US8252657B2 (en) | Metal gate transistor and resistor and method for fabricating the same | |
| US10170581B2 (en) | FinFET with reduced parasitic capacitance | |
| US9437714B1 (en) | Selective gate contact fill metallization | |
| US20110210384A1 (en) | Scalable integrated MIM capacitor using gate metal | |
| TWI536571B (en) | Semiconductor device | |
| US9496362B1 (en) | Contact first replacement metal gate | |
| CN102487010B (en) | Method for forming metal grid and MOS (Metal Oxide Semiconductor) transistor | |
| US9553140B2 (en) | Integrated circuit and method of fabricating the same | |
| CN1981386A (en) | Fully silicided metal gates | |
| TW201220356A (en) | Method of fabricating semiconductor device | |
| US8883623B2 (en) | Facilitating gate height uniformity and inter-layer dielectric protection | |
| TW200522270A (en) | Method for fabricating semiconductor devices having silicided electrodes | |
| TWI269430B (en) | Trench capacitor of a DEAM memory cell with metallic collar region and nonmetallic buried strap to the select transistor | |
| US20140179093A1 (en) | Gate structure formation processes | |
| CN102810467A (en) | Metal gate forming method | |
| CN106960875B (en) | Semiconductor device and method for manufacturing the same | |
| CN104701136B (en) | Capacitor, semiconductor devices and forming method thereof | |
| US9893145B1 (en) | On chip MIM capacitor | |
| CN107978564B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN103578945A (en) | Method for manufacturing semiconductor device | |
| US20220068713A1 (en) | Tiered-Profile Contact for Semiconductor | |
| US7682890B2 (en) | Method of fabricating semiconductor device | |
| CN102779790A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20121205 |