CN108400116B - Method for manufacturing semiconductor device - Google Patents
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- CN108400116B CN108400116B CN201710064337.2A CN201710064337A CN108400116B CN 108400116 B CN108400116 B CN 108400116B CN 201710064337 A CN201710064337 A CN 201710064337A CN 108400116 B CN108400116 B CN 108400116B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a grid groove is formed in the interlayer dielectric layer; sequentially forming a high-k dielectric layer and a protective layer on the bottom and the side wall of the gate trench and the surface of the interlayer dielectric layer; removing the part of the protective layer above the surface of the interlayer dielectric layer; removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer; carrying out first annealing treatment; and removing the protective layer. The method can avoid the problem of overlarge stress caused by the difference of the thermal expansion coefficients of a plurality of film layers in the first annealing treatment process, thereby avoiding the formation of crack defects in the film layers such as a high-k dielectric layer and the like, ensuring the isolation performance of a device, further improving the leakage current of a grid electrode and improving the performance and the yield of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, as the semiconductor industry has progressed to the point of nanotechnology process in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limitations.
For smaller nanotechnology process nodes, such as 7nm and below nanotechnology process nodes, PMOS devices may use Ge channels, while NMOS devices may use III-V compound semiconductors (e.g., InGaAs) as channels to improve carrier mobility. Due to the continuous shrinkage of the technical nodes, the physical thickness of the thin film of the gate dielectric layer can be increased by applying the high-k dielectric layer under the condition of keeping the gate capacitance unchanged, so that the aims of reducing the leakage current of the gate dielectric layer and improving the reliability of the device are fulfilled, in addition, an Interface Layer (IL) is usually formed between the high-k dielectric layer and the substrate in order to improve the interface characteristic between the high-k dielectric layer and the substrate, and the quality of the interface layer and the high-k dielectric layer has great influence on the performance of the device.
Currently, PCA annealing is generally used to improve the quality of the high-k dielectric layer and the interfacial layer, wherein the PCA annealing generally forms a protective layer (e.g., an amorphous silicon layer) on the high-k dielectric layer, then performs an annealing process on the high-k dielectric layer, and then removes the protective layer; another post-deposition anneal (PDA) method is also commonly used to improve the quality of the high-k dielectric layer. However, the annealing process may cause stress caused by different thermal expansion coefficients, such as silicon nitride (SiN) of the spacer, a high-k dielectric layer, a capping layer TiN on the high-k dielectric layer, and a protective layer (e.g., amorphous silicon) deposited on the capping layer TiN, which are different in thermal expansion coefficient due to the different materials used, and the difference in thermal expansion coefficient may cause stress between the layers during the annealing process, and once the stress is too large, all the layers may crack to generate crack defects, thereby reducing the isolation performance, resulting in high gate leakage, poor Contact (CT) isolation performance electrically connected to the gate, and the like.
In view of the above problems, it is necessary to provide a new method for manufacturing a semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a grid groove is formed in the interlayer dielectric layer;
sequentially forming a high-k dielectric layer and a protective layer on the bottom and the side wall of the gate trench and the surface of the interlayer dielectric layer;
removing the part of the protective layer above the surface of the interlayer dielectric layer;
removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer;
carrying out first annealing treatment;
and removing the protective layer.
Further, after the high-k dielectric layer is formed and before the protective layer is formed, a step of forming a capping layer on a surface of the high-k dielectric layer is further included.
Further, the step of removing the portion of the protection layer over the surface of the interlayer dielectric layer comprises the steps of:
forming a sacrificial material layer to fill the gate trench and cover the protective layer over the surface of the interlayer dielectric layer;
planarizing the sacrificial material layer until the protective layer is exposed;
and removing the part of the protective layer above the surface of the interlayer dielectric layer.
Further, after the step of removing the high-k dielectric layer located above the surface of the interlayer dielectric layer and before the step of the first annealing treatment, the method further comprises the step of removing the sacrificial material layer.
Further, the temperature range of the first annealing treatment is 900 ℃ to 1100 ℃.
Further, the material of the protective layer comprises amorphous silicon.
Further, the thickness of the protective layer ranges from 40 angstroms to 120 angstroms.
Further, the material of the sacrificial material layer includes at least one of an organic distribution layer, a bottom anti-reflection coating layer and a photoresist.
Further, spacers are formed on sidewalls of the gate trench prior to forming the high-k dielectric layer.
Further, the sacrificial material layer is removed by wet etching using an etchant including tetramethylammonium hydroxide or ammonium hydroxide.
Further, the temperature range of the etchant is 25 ℃ to 75 ℃ when the sacrificial material layer is removed.
Further, after forming the high-k dielectric layer and before forming the protective layer, the method further includes: and performing a second annealing step on the high-k dielectric layer.
According to the manufacturing method, before the first annealing treatment is carried out, the part of the protective layer, which is positioned above the surface of the interlayer dielectric layer, is removed, and the part of the high-k dielectric layer, which is positioned above the surface of the interlayer dielectric layer, is removed, so that the problem of overlarge stress caused by the difference of thermal expansion coefficients among a plurality of film layers in the first annealing treatment process can be avoided, the crack defect formed in the film layers such as the high-k dielectric layer is avoided, the isolation performance of a device is ensured, the leakage current of a grid electrode is improved, and the performance and the yield of the device are improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A to 1I are schematic structural views of a device obtained at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 shows a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the foregoing technical problem and improve the performance of the device, an embodiment of the present invention provides a method for manufacturing a semiconductor device, which, as shown in fig. 2, mainly includes:
step S1, providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a grid groove is formed in the interlayer dielectric layer;
step S2, sequentially forming a high-k dielectric layer and a protective layer on the bottom and the side wall of the gate trench and the surface of the interlayer dielectric layer;
step S3, removing the part of the protective layer above the surface of the interlayer dielectric layer;
step S4, removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer;
step S5, performing a first annealing treatment;
and step S6, removing the protective layer.
According to the manufacturing method, before the first annealing treatment is carried out, the part of the protective layer, which is positioned above the surface of the interlayer dielectric layer, is removed, and the part of the high-k dielectric layer, which is positioned above the surface of the interlayer dielectric layer, is removed, so that the problem of overlarge stress caused by the difference of thermal expansion coefficients among a plurality of film layers in the first annealing treatment process can be avoided, the crack defect formed in the film layers such as the high-k dielectric layer is avoided, the isolation performance of a device is ensured, the leakage current of a grid electrode is improved, and the performance and the yield of the device are improved.
Specifically, a method for manufacturing a semiconductor device of the present invention is described in detail below with reference to fig. 1A to 1I, in which fig. 1A to 1I show schematic structural views of devices obtained at relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Firstly, a first step is executed, a semiconductor substrate is provided, an interlayer dielectric layer is formed on the semiconductor substrate, and a grid groove is formed in the interlayer dielectric layer.
Specifically, as shown in fig. 1A, the semiconductor substrate 100 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In one example, the semiconductor substrate includes an NMOS device region in which a gate trench 1021 is formed and a PMOS device region in which a gate trench 1022 is formed.
Illustratively, the channel material under the gate trench in the NMOS device region may comprise a III-V compound semiconductor, such as a III-V binary or ternary compound semiconductor, in this embodiment the III-V compound semiconductor is InGaAs, and the channel material under the gate trench in the PMOS device region comprises an elemental semiconductor, wherein the elemental semiconductor material may be any elemental semiconductor used as is well known to those skilled in the art, including but not limited to Ge or Si, or the channel material under the gate trench in the PMOS device region comprises SiGe, in this embodiment the elemental semiconductor is Ge, and the carrier mobility may be improved by using the III-V compound semiconductor as the channel of the NMOS device and the elemental semiconductor as the channel of the PMOS device. Illustratively, the channel material in the NMOS device region and the PMOS device region may also use a commonly used Si semiconductor material.
It is worth mentioning that the elemental semiconductor refers to a semiconductor composed of a single element.
Illustratively, the semiconductor device of the present invention is a FinFET device, and then a first fin structure is formed on the semiconductor substrate in the NMOS device region, a second fin structure is formed on the semiconductor substrate in each PMOS device region, the gate trench 1021 exposes a portion of the surface of the first fin structure, and the gate trench 1022 exposes a portion of the surface of the second fin structure.
In one example, taking a FinFET device as an example, to obtain the structure shown in fig. 1A, the following steps a1 through a5 may be performed:
in one example, to obtain the structure shown in fig. 1A, the following process steps may be performed:
first, step a1 is executed to form a plurality of fin structures on a semiconductor substrate, for example, a first fin structure and a second fin structure are respectively formed in the NMOS device region and the PMOS device region on the semiconductor substrate, the fin structures have the same width, or the fins are divided into a plurality of fin structure groups having different widths, and the fin structures may have different lengths.
Specifically, the formation method of the fin structure is not limited to a certain one, and an exemplary formation method is given below: forming a hard mask layer (not shown) on the semiconductor substrate, wherein the hard mask layer may be formed by using various suitable processes, such as a chemical vapor deposition process, which are familiar to those skilled in the art, and the hard mask layer may be a bottom-up stacked oxide layer and a silicon nitride layer; patterning the hard mask layer, forming a plurality of isolated masks for etching the semiconductor substrate to form fins thereon, in one embodiment, the patterning is performed using a self-aligned double pattern (SADP) process; the semiconductor substrate is etched to form fin structures thereon.
Subsequently, step a2 may be performed to deposit a layer of spacer material to cover all of the fin structures described above.
Specifically, a layer of spacer material is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer may be selected from oxides, such as High Aspect Ratio Process (HARP) oxide, and may specifically be silicon oxide.
And then etching back the isolation material layer to the target height of the fin structures to form isolation structures, wherein the top surfaces of the isolation structures are lower than the top surfaces of the first fin structures and the second fin structures. Specifically, the isolation material layer is etched back to expose a portion of the fin structure, thereby forming a fin structure with a specific height.
Next, step a3 is performed to form a first dummy gate structure crossing over the first fin structures and a second dummy gate structure crossing over the second fin structures, wherein the dummy gate structures each include a dummy gate dielectric layer and a dummy gate material layer.
It is noted that the term "cross over" as used in the present invention, such as a dummy gate structure that crosses over a fin structure (e.g., a first fin structure, a second fin structure, etc.), means that the dummy gate structure is formed on both the top surface and the side surface of a portion of the fin structure, and the dummy gate structure is also formed on a portion of the surface of the semiconductor substrate.
In one example, a dummy gate dielectric layer and a dummy gate material layer may be deposited sequentially on a semiconductor substrate.
The dummy gate dielectric layer can be made of common oxide, such as SiO2The dummy gate material layer may be made of a semiconductor material commonly used in the art, such as polysilicon, etc., but is not limited to one of them,
The deposition method of the dummy gate material layer can be chemical vapor deposition or atomic layer deposition.
The dummy gate dielectric layer and the dummy gate material layer are then patterned to form the first dummy gate structure and the second dummy gate structure. Specifically, a photoresist layer is formed on the dummy gate material layer, then exposure and development are carried out to form an opening, then the dummy gate material layer is etched by taking the photoresist layer as a mask, and finally the photoresist layer is removed.
And then, optionally, forming offset side walls (spacers) on the side walls of the first dummy gate structure and the second dummy gate structure.
Specifically, the offset spacer may be formed of one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. As an embodiment of this embodiment, the offset spacer is composed of silicon oxide and silicon nitride, and the specific process includes: and forming a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer on the semiconductor substrate, and then forming the offset side wall by adopting an etching method. Or forming a side wall material layer on both the top surface and the side wall of the dummy gate structure, and removing the side wall material layer on the top surface through a planarization method, such as chemical mechanical polishing, in the subsequent step to form the offset side wall only on the side wall.
Optionally, LDD ion implantation steps are performed and activated for both sides of the first dummy gate structure and the second dummy gate structure.
Optionally, spacers 10 are formed on the offset sidewalls of the dummy gate structure.
Specifically, spacers (spacers) are formed on the offset sidewalls, and the spacers may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an implementation manner of this embodiment, the spacer is composed of silicon oxide and silicon nitride, and the specific process includes: a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are formed on a semiconductor substrate, and then a spacer is formed by an etching method.
Then, step a4 is performed, and source-drain implantation may also be selectively performed, and source/drains of NMOS devices are formed in the first fin structures on two sides of the first dummy gate structure, and source/drains of PMOS devices are formed in the second fin structures on two sides of the second dummy gate structure.
Further comprising the steps of: and growing stress layers in source/drain regions at two sides of the first dummy gate structure and the second dummy gate structure, wherein in the CMOS transistor, a stress layer with tensile stress is usually formed on the NMOS transistor, and a stress layer with compressive stress is formed on the PMOS transistor, and the performance of the CMOS device can be improved by applying the tensile stress to the NMOS and applying the compressive stress to the PMOS. In the prior art, SiC is usually selected as a tensile stress layer in an NMOS transistor, and SiGe is usually selected as a compressive stress layer in a PMOS transistor.
Preferably, when the SiC is grown as the tensile stress layer, the SiC may be epitaxially grown on the substrate, the raised source and drain may be formed after ion implantation, and when the SiGe layer is formed, a groove is usually formed in the substrate, and then the SiGe layer is formed by deposition in the groove. More preferably, a "sigma" shaped recess is formed in the substrate.
Next, step a5 is performed, wherein an interlayer dielectric layer 101 is deposited and planarized to fill the gap between each dummy gate structure, and the interlayer dielectric layer 101 covers the entire surface of the semiconductor substrate and the stress layer.
Specifically, an interlayer dielectric layer 101 is deposited and planarized, planarizing the interlayer dielectric layer 101 to the top of the first dummy gate structure and the second dummy gate structure.
The interlayer dielectric layer 101 may be made of dielectric materials commonly used in the art, such as various oxides, in which case the interlayer dielectric layer may be made of SiO2The thickness is not limited to a certain value.
Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method.
And then, removing the first dummy gate structure and the second dummy gate structure, including sequentially removing the dummy gate dielectric layer and the dummy gate material layer to form a gate trench 1021 on the semiconductor substrate 100 in the NMOS device region and a gate trench 1022 on the semiconductor substrate 100 in the PMOS device region, where the gate trench in the NMOS device region exposes a portion of the first fin structure in the extending direction of the first fin structure and the gate trench in the PMOS device region exposes a portion of the second fin structure in the extending direction of the second fin structure.
Finally, a structure is formed as shown in fig. 1A, in which an interlayer dielectric layer 101 is formed on the semiconductor substrate 100, a gate trench 1021 and a gate trench 1022 are formed in the interlayer dielectric layer 101, and the spacer 10 formed in the foregoing step is located on the sidewall of the gate trench.
And then, executing a second step to form an interface layer at the bottom of the gate trench.
Specifically, as shown in fig. 1B, an interface layer 103 is formed at the bottom of the gate trench. Illustratively, an interface layer 103 is formed at the bottom of the gate trench 1022 of the PMOS device region and the gate trench 1021 of the NMOS device region, and the formation of the Interface Layer (IL))103 serves to improve the interface characteristics between the high-k dielectric layer and the semiconductor substrate.
The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer may be formed using a suitable process such as thermal oxidation, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD).
In this embodiment, the interfacial layer 103 may be a chemical oxide layer. Example (b)For example, a chemical oxidation method using an Ozone (Ozone) treatment liquid may be used to form a chemical oxidation layer as the interface layer 103. Specifically, the material of the interface layer 103 may be determined according to the channel material at the bottom of the gate trench 1022, in this embodiment, the channel of the PMOS device is Ge, and the interface layer 103 is an oxide of germanium, such as GeO2。
The thickness of the interface layer 103 can be set according to the actual process requirements, for example, the thickness of the interface layer 103 can be in the range of 5 angstroms to 10 angstroms.
And then, executing a third step to form a high-k dielectric layer on the bottom and the side wall of the gate groove and the surface of the interlayer dielectric layer.
Illustratively, continuing with fig. 1B, a high-k dielectric layer 104 is formed on the bottom and sidewalls of the gate trenches 1022 and 1021 of the PMOS and NMOS device regions and on the surface of the interlayer dielectric layer 101.
High-k dielectric layer 104 typically has a k value (dielectric constant) of 3.9 or more, and is made of a material including hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like, preferably hafnium oxide, zirconium oxide, or aluminum oxide. The high-k dielectric layer 104 may be formed using a suitable process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD).
High-k dielectric layer 104 may optionally have a thickness in the range of 10 angstroms to 30 angstroms, but may have other suitable thicknesses.
In one example, an annealing step may also be optionally performed after forming the high-k dielectric layer 104.
Optionally, after forming the high-k dielectric layer 104, an annealing process may also be performed on the high-k dielectric layer 104. The annealing process of this step may be any suitable annealing method known to those skilled in the art, such as rapid thermal annealing, furnace tube annealing, spike annealing (spike anneal), etc. For example, hafnium oxide is deposited as the high-k dielectric layer 104 by using atomic layer deposition, and in order to obtain a pure crystalline structure of hafnium oxide, it is necessary to perform an annealing process on the high-k dielectric layer, for example, an annealing temperature ranging from 600 ℃ to 1000 ℃, for example, 650 ℃, 700 ℃, 750 ℃, 800 ℃, 850 ℃, 900 ℃, etc., and an annealing time ranging from 30s to 600s, and this annealing process is called post-deposition annealing (PDA).
And then, executing a step four to form a covering layer on the surface of the high-k dielectric layer.
Specifically, as shown in fig. 1C, a capping layer is formed on a surface of the high-k dielectric layer.
Illustratively, the capping layer 105 is formed on the surface of the high-k dielectric layer 104 on the bottom and sidewalls of the gate trench, and further formed on the surface of the high-k dielectric layer 104 on the interlayer dielectric layer 101.
The material of the capping layer 105 may be La2O3、AL2O3、Ga2O3、In2O3MoO, Pt, Ru, TaCNO, Ir, TaC, MoN, WN, TixN1-x, or other suitable thin film layer. In this embodiment, the capping layer 105 is made of TiN. The capping layer 105 may be formed using a suitable process such as CVD, ALD, or PVD.
The thickness of the capping layer 105 is in the range of 0 a to 20 a, but may be other suitable thicknesses.
And then, executing a fifth step to form a protective layer on the surface of the covering layer.
Illustratively, as shown in fig. 1C, the protection layer 106 is formed on the surface of the capping layer 105 on the bottom and sidewalls of the gate trench, and further formed on the surface of the capping layer 105 on the interlayer dielectric layer 101.
In one example, the protective layer 106 may also be formed directly on the surface of the high-k dielectric layer without first forming a capping layer.
Further, the material of the protective layer 106 is an amorphous semiconductor material. The amorphous semiconductor material comprises amorphous silicon (a-Si) or amorphous germanium (a-Ge), and can be other suitable amorphous semiconductor materials.
Methods for forming the sacrificial layer include Chemical Vapor Deposition (CVD) such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and generally similar methods such as sputtering and Physical Vapor Deposition (PVD) can also be used.
The thickness of the protective layer 106 formed is in the range of 40 to 120 angstroms, but may be other suitable thicknesses.
And fifthly, removing the part of the protective layer above the surface of the interlayer dielectric layer.
In one example, the step of removing the portion of the protection layer over the surface of the interlayer dielectric layer comprises the steps of:
first, as shown in fig. 1D, a sacrificial material layer 107 is formed to fill the gate trench and cover the protection layer 106 over the surface of the interlayer dielectric layer 101. Illustratively, the sacrificial material layer 107 fills the gate trenches of the PMOS device region and the gate trenches of the NMOS device region.
Alternatively, the sacrificial material layer 107 may be any suitable material, including but not limited to at least one of an Organic Distribution Layer (ODL), a Bottom Anti-reflective coating (BARC), and a photoresist, or other suitable material.
The sacrificial material layer 107 may be formed using spin coating or chemical vapor deposition.
Next, as shown in fig. 1E, the sacrificial material layer 107 is planarized until the protection layer 106 is exposed, so that the top surface of the protection layer above the surface of the interlayer dielectric layer is flush with the top surface of the sacrificial material layer, i.e., the planarization stops on the top surface of the protection layer.
Planarization of the surface may be achieved using planarization methods that are conventional in the semiconductor fabrication art. Non-limiting examples of the planarization method include a mechanical planarization method and a Chemical Mechanical Polishing (CMP) planarization method. Wherein, a chemical mechanical polishing planarization method is preferably used.
The introduced sacrificial material layer can play a role in protecting a film layer formed in the gate trench in the subsequent multi-step etching process, and can avoid the problems of complicated process and high cost caused by using a mask for multiple times in the subsequent etching.
Subsequently, as shown in fig. 1F, a portion of the protection layer 106 above the surface of the interlayer dielectric layer 101 is removed.
The protective layer 106 and a portion of the sacrificial material layer 107 may be etched simultaneously using any suitable etching method to remove the portion of the protective layer 106 above the surface of the interlayer dielectric layer 101. illustratively, when a capping layer is formed below the protective layer, the protective layer is etched until the top surface of the capping layer is exposed such that the top surface of the remaining sacrificial material layer 107 and the top surface of the exposed capping layer 105 are flush.
Illustratively, the etching in this step may be performed by a dry etching method or a wet etching method, wherein the dry etching method may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.
Wherein the etching method uses an etching method having a high etching rate for the sacrificial material layer and the protective layer and a low etching rate for the capping layer.
And then, carrying out step six, and removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer.
In one example, as shown in fig. 1G, the portions of the capping layer 105 and the high-k dielectric layer 104 above the surface of the interlayer dielectric layer 101 are removed, and the top surface of the remaining capping layer 105, the top surface of the remaining high-k dielectric layer 104 and the top surface of the interlayer dielectric layer 101 are flush and lower than the top surface of the protection layer 106 and the top surface of the sacrificial material layer 107.
Wherein the capping layer 105 and the high-k dielectric layer 104 may be etched using an etching method having a high etching rate for the capping layer 105 and the high-k dielectric layer 104 and a low etching rate for the protection layer 106, the sacrificial material layer 107 and the interlayer dielectric layer to sequentially remove portions of the capping layer 105 and the high-k dielectric layer 104 above the surface of the interlayer dielectric layer 101 to expose a top surface of the interlayer dielectric layer.
Illustratively, the etching in this step may be performed by a dry etching method or a wet etching method, wherein the dry etching method may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.
And finally, performing a seventh step to remove the sacrificial material layer.
As shown in fig. 1H, the sacrificial material layer may be removed by any suitable method known to those skilled in the art, and particularly, a suitable removal method may be selected according to the material of the sacrificial material layer used, including but not limited to wet etching or dry etching, and preferably, a wet etching method having a high etching rate for the sacrificial material layer and a low etching rate for the interlayer dielectric layer, the spacer, the high-k dielectric layer, the capping layer and the protection layer may be used to remove the sacrificial material layer.
In one example, when the material of the sacrificial material layer is photoresist, the sacrificial material layer can be removed by using an ashing method.
Then, step eight is performed to perform annealing treatment.
In particular, with continued reference to fig. 1H, the device is subjected to an annealing process that serves to improve the quality of the film layers, such as the high-k dielectric layer and the interfacial layer.
Optionally, the temperature range of the annealing treatment is 900 ℃ to 1100 ℃, and other suitable temperatures can be adopted.
The annealing process may use any suitable annealing method, such as furnace tube annealing, spike annealing, laser annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light source (e.g., halogen lamps, arc lamps, graphite heating) rapid annealing. In this embodiment, the annealing process preferably uses spike annealing or laser annealing.
In the annealing process of the step, the film layers such as the high-k dielectric layer, the covering layer and the protective layer which cover the surface of the interlayer dielectric layer are removed, so that the stress generated among the film layers due to different thermal expansion coefficients can be well released in the annealing process, the defect that crack is generated on all the film layers such as a gap wall, the high-k dielectric layer, the covering layer and the protective layer due to overlarge stress is avoided, and the isolation performance is further ensured.
Subsequently, step nine is performed to remove the protective layer.
Specifically, as shown in fig. 1I, the protective layer may be removed using any suitable method known to those skilled in the art, including but not limited to dry etching or wet etching.
In one example, where the material of the protective layer comprises amorphous silicon, the sacrificial material layer may be removed by wet etching using an etchant comprising tetramethylammonium hydroxide or ammonium hydroxide.
Illustratively, the temperature of the etchant ranges from 25 ℃ to 75 ℃ when the protective layer is removed.
Finally, a conventional metal gate structure process is performed, in one example, process steps B1 through B5 are performed:
step B1, forming a first diffusion barrier layer on the bottom and the side wall of the gate trench of the NMOS device area and the PMOS device area;
specifically, the first diffusion barrier layer may also be selectively disposed, and the material of the first diffusion barrier layer 106 may be selected from, but not limited to, TaN, Ta, TaAl, or other suitable thin film layers. In this embodiment, TaN is used as the material of the first diffusion barrier layer. The first diffusion barrier layer 106 may be formed using a suitable process such as CVD, ALD, or PVD. The first diffusion barrier layer 106 has a thickness in the range of 0 to 20 angstroms.
Further, the first diffusion barrier layer is located on a surface of the capping layer.
And step B2, forming a P-type work function layer on the bottom and the side wall of the grid groove of the PMOS device area, wherein the P-type work function layer is positioned on the surface of the first diffusion barrier layer.
Specifically, the material of the P-type work function layer can be selected from but not limited to TixN1-x, TaC, MoN, TaN or their combination or other suitable thin film layer. In this embodiment, the P-type work function layer is made of TiN. The P-type work function layer 107 may be formed using a suitable process such as CVD, ALD, or PVD. The thickness of the P-type work function layer ranges from 10 a to 580 a, but is not limited to this value.
And step B3, forming N-type work function layers on the bottom and the side wall of the grid groove of the NMOS device area and the PMOS device area, wherein the N-type work function layer is positioned on the surface of the first diffusion barrier layer in the NMOS device area, and the N-type work function layer of the PMOS device area is positioned on the surface of the P-type work function layer.
The material of the N-type work function layer may be selected from, but is not limited to, TaAlC, TaC, Ti, Al, TixAl1-x, or other suitable thin film layers. The material of the N-type work function layer is preferably TiAl. The N-type work function layer may be formed using a suitable process such as CVD, ALD, or PVD. The thickness of the N-type work function layer may range from 10 angstroms to 80 angstroms.
And step B4, forming a second diffusion barrier layer on the bottom and the side wall of the gate trench of the NMOS device area and the PMOS device area, wherein the second diffusion barrier layer is positioned on the surface of the N-type work function layer.
The second diffusion barrier layer may also be optionally provided, and the material of the second diffusion barrier layer may be selected from, but not limited to, TaN, Ta, TaAl, or other suitable thin film layers.
After the formation of the above-mentioned layers, a planarization process, such as chemical mechanical polishing, may be performed to stop on the surface of the interlayer dielectric layer 101, so as to remove the excess layers on the surface of the interlayer dielectric layer 101.
Step B5, filling gate electrode layers in the gate trenches of the NMOS device region and the PMOS device region to finally form metal gate structures in both the NMOS device region and the PMOS device region.
The gate electrode layer fills the gate trench, and the material of the gate electrode layer can be selected from, but is not limited to, Al, W, or other suitable thin film layers. The gate electrode layer may be formed by a suitable process such as CVD, ALD, or PVD.
In one example, a gate electrode layer may be deposited to fill the gate trench and cover the surface of the interlayer dielectric layer, and a planarization process, such as chemical mechanical polishing, may be performed to stop on the surface of the interlayer dielectric layer.
Thus, the detailed description of the method for manufacturing the semiconductor device of the present invention is completed, and further process steps may be required for manufacturing the complete device, which is not described herein again.
In summary, according to the manufacturing method of the present invention, before the first annealing treatment is performed, the portion of the protection layer located above the surface of the interlayer dielectric layer is removed, and the portions of the high-k dielectric layer and the capping layer located above the surface of the interlayer dielectric layer are removed, so that the problem of excessive stress caused by the difference of thermal expansion coefficients between the plurality of film layers during the first annealing treatment can be avoided, thereby avoiding crack defects formed in the film layers such as the high-k dielectric layer, the capping layer, and the protection layer, ensuring the isolation performance of the device, further improving the leakage current of the gate electrode, and improving the performance and yield of the device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (12)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a grid groove is formed in the interlayer dielectric layer;
sequentially forming a high-k dielectric layer and a protective layer on the bottom and the side wall of the gate trench and the surface of the interlayer dielectric layer;
removing the part of the protective layer above the surface of the interlayer dielectric layer;
removing the part of the high-k dielectric layer above the surface of the interlayer dielectric layer;
carrying out first annealing treatment;
and removing the protective layer.
2. The method of manufacturing of claim 1, further comprising the step of forming a capping layer on a surface of the high-k dielectric layer after forming the high-k dielectric layer and before forming the protective layer.
3. The method of manufacturing of claim 1, wherein the step of removing the portion of the protective layer over the surface of the interlayer dielectric layer comprises the steps of:
forming a sacrificial material layer to fill the gate trench and cover the protective layer over the surface of the interlayer dielectric layer;
planarizing the sacrificial material layer until the protective layer is exposed;
and removing the part of the protective layer above the surface of the interlayer dielectric layer.
4. The method of manufacturing of claim 3, further comprising the step of removing the layer of sacrificial material after the step of removing the high-k dielectric layer over the surface of the interlevel dielectric layer and before the step of first annealing.
5. The manufacturing method according to claim 1, wherein the temperature range of the first annealing treatment is 900 ℃ to 1100 ℃.
6. The method of manufacturing according to claim 1, wherein a material of the protective layer comprises amorphous silicon.
7. The method of manufacturing of claim 1, wherein the protective layer has a thickness in a range of 40 angstroms to 120 angstroms.
8. The method of claim 3, wherein the material of the sacrificial material layer comprises at least one of an organic distribution layer, a bottom anti-reflective coating, and a photoresist.
9. The method of manufacturing of claim 1, wherein spacers are formed on sidewalls of the gate trench prior to forming the high-k dielectric layer.
10. The manufacturing method according to claim 3, wherein the sacrificial material layer is removed by wet etching using an etchant comprising tetramethylammonium hydroxide or ammonium hydroxide.
11. The manufacturing method according to claim 10, wherein the temperature of the etchant when removing the sacrificial material layer is in a range of 25 ℃ to 75 ℃.
12. The method of manufacturing of claim 1, wherein after forming the high-k dielectric layer and before forming the protective layer, further comprising: and performing a second annealing step on the high-k dielectric layer.
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| US7160767B2 (en) * | 2003-12-18 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
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| US7157378B2 (en) * | 2004-07-06 | 2007-01-02 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
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| US7160767B2 (en) * | 2003-12-18 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
| US8580629B2 (en) * | 2010-11-15 | 2013-11-12 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device using a work function control film |
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