CN105632906B - Self-aligned contacts manufacturing method - Google Patents
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- CN105632906B CN105632906B CN201410585105.8A CN201410585105A CN105632906B CN 105632906 B CN105632906 B CN 105632906B CN 201410585105 A CN201410585105 A CN 201410585105A CN 105632906 B CN105632906 B CN 105632906B
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Abstract
A kind of self-aligned contacts manufacturing method, comprising: the grid curb wall of metal gates and metal gates two sides is formed in interlayer dielectric layer on substrate；Self-aligned etching removes interlayer dielectric layer, exposes grid curb wall and source drain region；Formed contact metal layer, cover substrate source drain region and metal gates at the top of and grid curb wall side wall；And planarized contact metal layer, until at the top of exposure grid curb wall.According to self-aligned contacts manufacturing method of the invention; it is not recessed to metal gates but directly forms protective layer at the top of it; it effectively can suitably relax critical size and be overlapped the limitation of size, improve the stability and device reliability to technological fluctuation, reduce manufacturing cost and technology difficulty.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing methods, more particularly to a kind of self-aligned contacts manufacturing method.
Background technique
MOSFET element equal proportion is reduced to after 45nm, and device needs high dielectric constant (high k) as gate insulating layer
And metal inhibits as the stacked structure of grid conducting layer due to the high gate leakage of polysilicon gate tcam-exhaustion bring
And grid capacitance reduces.In order to more effectively control the pattern (profile) of gate stack, industry generallys use rear grid work at present
Skill, namely usually first the false grid of the materials such as deposit polycrystalline silicon, interlayer dielectric layer (ILD) remove false grid later on substrate
The stacking of high k/ metal gate (HK/MG) film layer is then filled in pole in the gate trench left.Later, etching ILD forms exposure
The contact hole of source-drain area, deposited metal material forms contact plunger (plug) in the contact hole, completes source and drain interconnection.
However, as device integration improves, device feature size continual reductions, the size of grid length and source-drain area is all
Reduce in equal proportion.As the smaller such as Asia 20nm of the size of source-drain area, it will carry out huge choose to contact (contact) process bands
War.This, which is mainly reflected in, has higher requirement to the critical size (CD) of photoetching and overlapping (overlay).For example, in order to drop
The series resistance of low contact itself, it is desirable that contact pore size is substantially closely sized to source-drain area.If it is obviously small to contact pore size
In the size of source-drain area (especially heavy-doped source drain region SD), this is higher for the critical dimensional requirements of photoetching, while smaller ruler
Very little contact hole series resistance itself will be larger.Further, since distance reduces between contact hole and grid, to contact hole photoetching
Plyability is more demanding.If being overlapped the larger short circuit that will cause between contact and grid.
In order to solve this problem, a kind of couple of photoetching CD and overlay is needed to require relatively low technique.Industry at present
Self-aligned contacts (SAC) technique has been proposed and other similar SAC technique intention solves the above problems.
In general, SAC technique include false grid in rear grid technique stack it is graphical, form source-drain area, deposition ILD and remove
False grid, which stacks, to be formed gate openings, deposit gate dielectric layer and double-level-metal grid conducting layer in gate openings.Then
In order to enable source and drain contact can self aligned formation, using return carve (etch-back) or CMP process at the top of metal gates into
Row depression treatment can control quarter because metal gates two sides are grid curb wall (usually silicon nitride material) and ILD
Etching technique parameter or the component of CMP abrasive keep it larger for metal etch, polishing speed, self aligned formation recess.
The hard materials such as silicon nitride are filled in the recess of formation as top layer and etching stop layer, and preferably at the top of it
Lid oxide layer is formed, and subsequent CMP is until exposure ILD.Then, adjusting process parameter performs etching, due to metal gates top
There is silicon nitride hard material covering protection in portion, and vertical etch eliminates metal only for soft materials such as low-k materials, silica
Grid, side wall two sides ILD until exposure Si material substrate, form identical with grid two sides source-drain area size self aligned
Contact hole.This technique is small compared with common process for the CD control errors and overlay size requirements of photoetching.
However as described above, in order to avoid short circuit between contact and grid when photoetching offset is larger, Self-aligned etching is needed
Then the cavity filling SiN that etching is formed as insulating materials and is carried out CMP by the metal inside grid.This requires that grid
What pole was done wants sufficiently high, and most of metal gates will be removed by otherwise returning the recess process such as quarter, CMP, leads to component failure.And grid
Height increases, the miniaturization of unfavorable multilayer interconnection square thereon, and improves and deposit filling metal in gate openings in ILD
The defects of difficulty of layer, bubble easy to form, hole.Simultaneously increase a step CMP, this will will increase technology difficulty and technique at
This.
Summary of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, a kind of new self-aligned contact hole manufacture is proposed
Method effectively can suitably relax critical size and be overlapped the limitation of size, and improving can to the stability and device of technological fluctuation
By property, manufacturing cost and technology difficulty are reduced.
For this purpose, the present invention provides a kind of self-aligned contacts manufacturing methods, comprising: shape in interlayer dielectric layer on substrate
At metal gates and the grid curb wall of metal gates two sides；Self-aligned etching, remove interlayer dielectric layer, expose grid curb wall and
Source drain region；Formed contact metal layer, cover substrate source drain region and metal gates at the top of and grid curb wall side
Wall；And planarized contact metal layer, until at the top of exposure grid curb wall.
Wherein, the step of forming metal gates further comprises: false grid stacking is formed on the substrate；It is stacked in false grid
Two sides form grid curb wall；In the substrate of grid curb wall two sides and/or upper formation source-drain area is formed on the substrate and covers vacation
First interlayer dielectric layer of gate stack；Interlayer dielectric layer is planarized until exposure false grid stacks；Selective etch removal is false
Gate stack leaves gate openings in the first interlayer dielectric layer；Gate dielectric layer and metal gates are formed in gate openings.
Wherein, metal gates and/or contact metal layer material include W simple substance or W alloy.
Wherein, interlayer dielectric layer is silica or low-k materials.
Wherein, grid curb wall compactness is greater than interlayer dielectric layer.
Wherein, grid curb wall material is silicon nitride.
Wherein, metal gates and/or contact contact layer material still further comprise adjusting work content other than W, W alloy
Several materials, it is any and combinations thereof selected from Ti, TiN, Ta, TaN, TiAl, TiC, TiAlC.
According to self-aligned contacts manufacturing method of the invention, etching removal ILD deposition metal layer containing W is simultaneously planarized, and is not necessarily to
Contact hole photoetching effectively can suitably relax critical size and be overlapped the limitation of size, improve to the stability of technological fluctuation and
Device reliability reduces manufacturing cost and technology difficulty.
Detailed description of the invention
Carry out the technical solution that the present invention will be described in detail referring to the drawings, in which:
Fig. 1 to Fig. 4 is the cross-sectional view according to each step of manufacturing method of self-aligned contacts of the invention.
Specific embodiment
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses the method, semi-conductor device manufacturing method that can be effectively controlled grid lines fineness.It should be pointed out that similar
Appended drawing reference indicates that similar structure, term " first " use herein, " second ", "upper", "lower" etc. can be used for repairing
Adorn various device architectures or manufacturing process.These modifications do not imply that modified device architecture or manufacturing process unless stated otherwise
Space, order or hierarchical relationship.
Referring to the schematic diagram of each step of FIG. 1 to FIG. 4, next the technical schemes of the invention are described in detail.
As shown in Figure 1, deposited metal grid conducting layer and being planarized in the gate openings in the first interlayer dielectric layer, directly
To exposing the first interlayer dielectric layer.
Specifically, substrate 1 is first provided, substrate 1 is needed according to device application and reasonably selected, it may include monocrystalline silicon
(Si), monocrystal germanium (Ge), strained silicon (Strained Si), germanium silicon (SiGe) or compound semiconductor materials, such as nitrogen
Change gallium (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb) and carbon-based semiconductors for example graphene, SiC,
Carbon nanotube etc..For the consideration compatible with CMOS technology, substrate 1 is preferably body Si.Before forming false grid insulating layer,
Preferably, HF (dHF) solution is such as diluted using fluorine-based solution-or dilution sustained release etching agent (dBOE) carries out the short time
Surface cleaning removes oxide that may be present between false grid insulating layer and substrate, such as thin layer of silicon oxide.
Then, using CVD technique, such as LPCVD, PECVD, HDPCVD etc. deposits false grid insulating layer on substrate 1
(not shown), material can be silica, high-g value and combinations thereof.High-g value include but is not limited to nitride (such as
SiN, AlN, TiN), metal oxide (predominantly subgroup and lanthanide element oxide, such as MgO, Al2O3、Ta2O5、
TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3), Perovskite Phase oxide (such as PbZrxTi1-xO3(PZT)、BaxSr1- xTiO3(BST)).The thickness of false grid insulating layer cannot be too thick, avoids influencing gate topography, it is therefore preferable to 1~5nm.
Later, using the conventional process such as CVD, PVD, such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputtering etc.
Technique, forms false grid layer (not shown), and material can be polysilicon, amorphous silicon, SiGe, Si:C, amorphous germanium, amorphous carbon etc.
And combinations thereof, it is therefore preferable to polysilicon, amorphous silicon.
False grid layer and false grid insulating layer are patterned using common photoetching/etching technics, form false grid heap
Stack structure.Directly using false grid stacked structure as mask, the first time source and drain doping ion implanting of low dosage, low energy is carried out,
The source drain extension area 1L being lightly doped is formed in the substrate 1 that false grid stacks two sides.Further, it is also possible to carry out angle-tilt ion note
Enter, is formed in Yun Zhuan source and drain doping area (area Halo, be not shown).Due to eliminating the forming step of offset side wall, grid is shortened
The length for controlling lower channel area, is conducive to manufacture fine small size device.
Grid curb wall 2 is formed in false grid stacked structure two sides, forms the source of heavy doping in 2 two sides substrate of grid curb wall
Drain region.Using techniques such as LPCVD, PECVD, HDPCVD, such as silicon nitride, silicon oxynitride, diamond-like are deposited on entire device
Equal finer and close, the biggish insulating materials of hardness and etching of stone amorphous carbon (DLC) form grid curb wall 2.It is with grid curb wall 2
Mask carries out second of source and drain doping ion implanting of high dose, high-energy, and weight is formed in the substrate 1 of 2 two sides of grid curb wall
The source-drain area 1H of doping.Further, it is also possible to epitaxial growth lifting source on source-drain area 1H namely on the substrate of grid curb wall two sides
Drain region forms the higher source-drain area part of doping concentration by ion implantation doping after doping in situ or extension, with into
One step reduces source-drain contact resistance.Preferably, grid curb wall 2 can be multilayered structure (not shown), for example, at least include
Trilaminate stack structure, the respectively L-type on the outside of the first grid side wall contacted with false grid stacking, first grid side wall of inside
On the outside of the grid curb wall wall and grid curb wall wall of (second part with longitudinal first part and transverse direction)
With on second grid side wall (outside of its longitudinal first part for being located at grid curb wall wall, and be located at gate electrode side
On the lateral second part of wall wall).The material of first grid side wall is, for example, amorphous carbon or silicon nitride, can be used
LPCVD, PECVD, HDPCVD technique are formed, and the silicon nitride of preferably LPCVD production.Grid curb wall wall is, for example, CVD method
The silica of preparation, in order to provide the high etching selection ratio with other adjacent layers, to control grid/side wall pattern.Second
Grid curb wall can be silicon nitride, diamond-like amorphous carbon (DLC), silicon oxynitride of CVD method preparation etc..In the present invention one
In a preferred embodiment, the width of side wall 2 is preferably greater than or equal to the half of the difference of grid width and source/drain region width, such as
For 15nm, this corresponds to overlay (namely full-size of contact hole lateral deviation) in subsequent self-aligned contacts formation process
It can avoid and metal gates short circuit less than 15nm namely contact hole offset distance less than 2 width of grid curb wall.It is right therewith
Ratio, due to the sum of gate openings and lateral wall width and source-drain area similar width in common process, contact is being precisely formed
The overlay of higher condition is needed to limit during hole, such as 5nm or less.
By techniques such as spin coating, spraying, silk-screen printing, CVD (such as LPCVD) depositions on entire device, first is formed
Interlayer dielectric layer 3, material are preferably silica, silicon nitride or other low-k materials.Low-k materials are including but not limited to organic
Low-k materials (such as organic polymer containing aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline
Boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials,
Porous silica, porous SiOCH, it mixes C silica, mix the porous amorphous carbon of F, porous diamond, porous organo polysilica conjunction
Object).Then, etching removal false grid layer, leaves gate openings in ILD 3.It, can be with for the false grid layer of silicon material
It is removed using TMAH wet etching；For amorphous carbon material, oxygen plasma etch can be selected, it is possible to prevente effectively to adjacent
The erosion of material helps to improve lines fineness；For other materials, can select fluorine-based or chloro etching gas etc.
Gas ions dry etching or reactive ion etching (RIE).Preferably, for etching stopping on false grid insulating layer, false grid is exhausted
Edge layer is used as boundary layer and is used to that substrate channel region surface to be protected not weather in etching process, is conducive to reduce channel surface
Defect improves device reliability.In addition it is also possible to further remove false grid insulating layer (in figure after removing false grid layer
Be not shown), until exposure substrate 1, and then using chemical oxidation (such as immerse the ozone containing 10ppm deionized water in
20s) method forms the boundary layer of the silica of ultra-thin (being, for example, less than equal to 1nm thickness), for reducing high-k gate dielectric and substrate
Between boundary defect.It is worth noting that, the compactness of grid curb wall 2 is higher than ILD3 in the preferred embodiment of the present invention, such as
So that the corrosion rate of grid curb wall is less than the corrosion rate of interlayer dielectric layer in the etching process of subsequent touch hole.
Sequentially form grid Jie in gate openings in ILD 3 using techniques such as HDPCVD, MOCVD, MBE, ALD, sputterings
Matter layer 4 and metal gates conductive layer 5.The e.g. high-g value of gate dielectric layer 4, including but not limited to nitride (such as SiN,
AlN, TiN), metal oxide (predominantly subgroup and lanthanide element oxide, such as MgO, Al2O3、Ta2O5、TiO2、
ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3), nitrogen oxides (such as HfSiON)；Perovskite Phase oxide (such as PbZrxTi1-xO3
(PZT)、BaxSr1-xTiO3(BST)).It is highly preferred that there is also thermal oxides, change between 1 channel region of gate dielectric layer 4 and substrate
The boundary layer (not shown) for ultra-thin (such as 0.8~1.5nm) oxidation silicon material that oxidation is formed is learned to reduce interface state density.Gold
Belong to 5 material of grid conducting layer may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er,
The nitride of the alloy and these metals of the metal simple-substances such as La or these metals can additionally pass through doping in situ or ion
Injection is adulterated and has the elements such as C, F, N, O, B, P, As to adjust work function.Preferably, metal gates conductive layer 5 and grid are situated between
The barrier layer (not shown) of nitride, barrier layer material are further preferably formed between matter layer 4 by conventional methods such as PVD, CVD, ALD
For MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.At the present invention one
In optimum embodiment, (main) metal gates 5 are tungsten (W) material or its alloy.
Preferably, layer 5,4 is stacked using CMP process and carries out planarization process, until exposing the first ILD 3.It is worth note
Meaning, the embodiment shown in that figure of the present invention are the cross-sectional view according to the cell array transistor of memory device, it is therefore desirable to
Self aligned multiple source and drain contact holes are formed between multiple grids, and adjacent source transistor drain region shares.Naturally, for other
The device of structure can obtain required contact hole width and source and drain by adjusting the thickness and spacing of grid curb wall 2
Area can separate.It is preferable that for highly integrated device of the characteristic size less than 20nm, preferably broadening contact hole
Width is close to the width of source-drain area.
As shown in Fig. 2, Self-aligned etching, completely removes ILD 3.Since ILD3 material is silica, low-k materials, metal
Grid 5 is metal, these materials and the silicon nitride material characteristic as grid curb wall 2 are entirely different, etching selection between three
It is relatively high, therefore ILD3 can be selectively completely removed by adjusting etching technics, expose grid curb wall 2.Such as it adjusts
The proportion of the fluorine-based etching gas of carbon accelerates the etching for silica, low-k materials (with nitrogen to obtain different etch rates
The etching selection ratio of SiClx is greater than 5:1 and preferably greater than 10:1), or use wet etching (such as hot phosphoric acid is directed to silicon nitride,
HF base corrosive liquid is directed to silica).After removing ILD3, the source-drain area in the substrate of 5 two sides of gate metal is exposed, these areas
The gap directly formed between source and drain contact namely side wall 2 is constituted into source and drain contact hole, contact hole width approximation etc. on domain
In (difference less than 10%, and preferably smaller than 5%) source-drain area local width.Preferably, the metal of metal gates 5 mainly includes W
And its alloy, such as W, TiW, TaW, WN, BW, MoW, AlW etc., because of these simple substance or alloy containing W and ILD3, grid curb wall
2 Etch selectivity highest.
As shown in figure 3, forming contact metal layer 6 on entire device.6 formation process of metal layer such as MOCVD, MBE,
ALD, evaporation, sputtering etc., material can include but is not limited to Cu, Al, Ti, Ta, Mo, W, Co and combinations thereof.And further
Preferably, 6 material of metal layer is identical as 5 material of gate metal layer, such as mainly includes W, such as W simple substance, W alloy, this master
If because W filling capacity is good, resistivity is lower and high for CMP process compatibility.In addition, metal gates 5 and/or connecing
6 material of contact layer is touched other than W, W alloy, still further comprise adjust work function material, selected from Ti, TiN, Ta, TaN,
TiAl, TiC, TiAlC's is any and combinations thereof.The thickness of the part on metal layer 5 of metal layer 6 is preferably smaller than in gate electrode side
The 30% of the 5 following segment thickness in top of metal layer between wall 2, in other words namely metal layer 6 is small apart from 1 top surface maximum height of substrate
In 1.3 times of 5 height of metal gates, it is possible thereby to reduce the subsequent CMP time and avoid expanding recess (meeting when CMP of CMP castellation
Both ends are formed in the middle part of lines and are higher than intermediate recess, this recess can be effectively reduced by reducing CMP total amount).
As shown in figure 4, cmp planarization contact metal layer 6, goes to the top of exposed grid curb wall 2 or metal gates 5, by
This leaves source and drain contact 6A between grid curb wall 2.It is worth noting that, this source and drain contact plug 6A directly contacts grid
The side wall of side wall 2, therefore referred to as autoregistration source and drain contact hole reduce source-drain contact resistance conducive to by the width increased.And it is another
Outer one side, although 2 dielectric constant of grid curb wall of silicon nitride material is slightly larger than ILD3, since grid contacts it with source and drain
Between distance reduce significantly, total parasitic capacitance actually greatly reduces.
According to self-aligned contacts manufacturing method of the invention, etching removal ILD deposition metal layer containing W is simultaneously planarized, and is not necessarily to
Contact hole photoetching effectively can suitably relax critical size and be overlapped the limitation of size, improve to the stability of technological fluctuation and
Device reliability reduces manufacturing cost and technology difficulty.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as the disclosed specific embodiment for realizing preferred forms of the invention, and disclosed device architecture
And its manufacturing method will include all embodiments fallen within the scope of the present invention.
Claims (7)
1. a kind of self-aligned contacts manufacturing method, comprising:
The grid curb wall of multiple metal gates and each metal gates two sides, grid are formed in interlayer dielectric layer on substrate
The width of side wall is more than or equal to the half of the difference of metal gates width and source and drain sector width；
Self-aligned etching completely removes interlayer dielectric layer, exposes grid curb wall and source drain region；
Formed contact metal layer, cover substrate source drain region and metal gates at the top of and grid curb wall side wall, directly connect
Touch the grid curb wall of adjacent metal grid；And
Planarized contact metal layer, until at the top of exposure grid curb wall.
2. the step of the method for claim 1, wherein forming metal gates further comprises: vacation is formed on the substrate
Gate stack；Two sides, which are stacked, in false grid forms grid curb wall；In the substrate of grid curb wall two sides and/or upper formation source and drain
Area；The first interlayer dielectric layer for covering false grid stacking is formed on the substrate；Interlayer dielectric layer is planarized until the false grid of exposure
Pole stacks；Selective etch removes false grid and stacks, and leaves gate openings in the first interlayer dielectric layer；The shape in gate openings
At gate dielectric layer and metal gates.
3. the method for claim 1, wherein metal gates and/or contact metal layer material include that W simple substance or W are closed
Gold.
4. method as claimed in claim 3, wherein metal gates and/or contact contact layer material other than w, W alloy,
Still further comprise the material for adjusting work function, any and its group selected from Ti, TiN, Ta, TaN, TiAI, TiC, TiAIC
It closes.
5. the method for claim 1, wherein interlayer dielectric layer is silica or low-k materials.
6. the method for claim 1, wherein grid curb wall compactness is greater than interlayer dielectric layer.
7. the method for claim 1, wherein grid curb wall material is silicon nitride.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855420A (en) * | 2005-04-27 | 2006-11-01 | 上海华虹Nec电子有限公司 | Dimashg process with selective copper deposition |
| CN102810467A (en) * | 2012-08-16 | 2012-12-05 | 上海华力微电子有限公司 | Metal gate forming method |
| CN103545188A (en) * | 2012-07-13 | 2014-01-29 | 中国科学院微电子研究所 | Production method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855420A (en) * | 2005-04-27 | 2006-11-01 | 上海华虹Nec电子有限公司 | Dimashg process with selective copper deposition |
| CN103545188A (en) * | 2012-07-13 | 2014-01-29 | 中国科学院微电子研究所 | Production method of semiconductor device |
| CN102810467A (en) * | 2012-08-16 | 2012-12-05 | 上海华力微电子有限公司 | Metal gate forming method |
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Effective date of registration: 20220225 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 No. 3 Beitucheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |