CN105633004A - Self-aligned contact manufacture method - Google Patents
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Abstract
A self-aligned contact manufacture method provided by the invention comprises: a grid opening is formed in a first interlayer dielectric layer on a substrate, and a grid side wall is arranged at the side wall of the grid opening; a grid insulation layer which does not fully fill the grid opening is formed at the grid opening; mask figures are formed in the grid opening and on the grid insulation layer; and the mask figures are taken as masks, and the interlayer dielectric layer is etched until the top of the substrate and the side wall of the grid are exposed to form a self-aligned source drain contact hole. The self-aligned contact manufacture method is able to fill mask figures on the high K insulation layer in a grid opening to protect the top and the side wall of the grid opening so as to effectively and appropriately extend the limitation of the key size and the overlapping size, improve the stability of the technology fluctuation and the device reliability, and reduce the manufacture cost and the technology difficulty.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to a kind of self-aligned contacts manufacture method.
Background technology
After MOSFET element equal proportion is reduced to 45nm, device need high-k (high k) as gate insulator and metal as the stacked structure of grid conducting layer to suppress high gate leakage owing to polysilicon gate tcam-exhaustion brings and grid capacitance to reduce. For the pattern (profile) that more effective control gate is stacking, the current commonly used rear grid technique of industry, namely generally first at the false grid of the materials such as deposited on substrates polysilicon, remove false grid after interlayer dielectric layer (ILD), in the gate trench stayed, fill the stacking of high k/ metal gate (HK/MG) rete subsequently. Afterwards, etching ILD forms the contact hole in source of exposure drain region, and deposition metal material forms contact plunger (plug) in the contact hole, completes source and drain interconnection.
But, along with device integration improves, device feature size continual reductions, the size of grid length and source-drain area is all reduced in equal proportion. As the smaller such as sub-20nm of source-drain area, it will bring huge challenge to contact (contact) technique. This is mainly reflected in the critical size to photoetching (CD) and overlapping (overlay) has higher requirement. Such as, in order to reduce the series resistance of contact itself, it is desirable to contact hole size is substantially closely sized to source-drain area. If contact hole size is significantly less than the size of source-drain area (particularly heavy-doped source drain region SD), this is higher for the critical dimensional requirements of photoetching, and the series resistance of contact hole of reduced size own will be bigger simultaneously. Additionally, due to the spacing of contact hole and grid reduces, the plyability of contact hole photoetching is required higher. If overlap relatively conference causes the short circuit between contact and grid.
In order to solve this problem, it is necessary to a kind of technique that photoetching CD and overlay requirement is relatively low. Current industry has been proposed for self-aligned contacts (SAC) technique and other similar SAC technique is intended to solve the problems referred to above.
Generally, SAC technique include the false grid in rear grid technique stacking graphical, form source-drain area, deposit ILD and remove the stacking formation gate openings of false grid, deposition of gate dielectric layer and double-level-metal grid conducting layer in gate openings. Subsequent to make the source and drain contact self aligned formation of energy, adopt back quarter (etch-back) or CMP that metal gates top is carried out depression treatment, because metal gates both sides are grid curb wall (being generally silicon nitride material) and ILD, therefore the component that can control etch process parameters or CMP abrasive makes it relatively big for metal etch, polishing speed, and self aligned formation is caved in. The depression formed is filled the hard material such as silicon nitride as top layer and etching stop layer, and preferably forms lid oxide layer at its top, and subsequently CMP until exposing ILD. Subsequently; adjusting process parameter performs etching; owing to silicon nitride hard material covering protection is arranged at metal gates top; vertical etch is only for the soft material such as low-k materials, silicon oxide; eliminate metal gates, side wall both sides ILD until expose Si material substrate, define the self aligned contact hole equivalently-sized with grid both sides source-drain area. This technique is little for CD error control and all more conventional technique of overlay size requirements of photoetching.
However as described above, in order to avoid short circuit between contact and grid when photoetching offsets bigger, it is necessary to the metal within Self-aligned etching grid, the cavity filling SiN then etching formed as insulant and carries out CMP. Thus require that grid does sufficiently high, otherwise return the recess process such as quarter, CMP and will remove major part metal gates, cause component failure. And gate height increases, it is unfavorable for the miniaturization of multilayer interconnection above it, and improves the difficulty depositing filler metal layer in ILD in gate openings, it is easy to form the defect such as bubble, hole. Adding a step CMP, this will increase technology difficulty and process costs simultaneously.
Summary of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, it is proposed to a kind of new self-aligned contact hole manufacture method, can effectively suitably relax critical size and the restriction of overlapping size, improve the stability to technological fluctuation and device reliability, reduce manufacturing cost and technology difficulty.
For this, the invention provides a kind of self-aligned contacts manufacture method, including: the first interlayer dielectric layer on substrate is formed gate openings, gate openings sidewall has grid curb wall; Gate openings is formed the gate insulator not being filled up completely with gate openings; Mask graph is formed in gate openings, on gate insulator; With mask graph for mask, etching interlayer dielectric layer, until exposing substrate top and grid curb wall sidewall, forming self aligned source and drain contact hole.
Wherein, the step forming gate openings farther includes: form false grid on substrate stacking; Grid curb wall is formed at the stacking sidewall of false grid; Substrate is formed and covers the interlayer dielectric layer that false grid is stacking; Planarization interlayer dielectric layer is until exposure false grid is stacking; It is stacking that selective etch removes false grid, leaves gate openings in the first interlayer dielectric layer.
Wherein, grid curb wall material selected from silicon nitride, silicon oxynitride, DLC any one and combination.
Wherein, farther include after forming gate insulator and before forming mask graph, in gate openings, on gate insulator, form work function regulating course.
Wherein, work function regulating course is metal, metal alloy, metal oxynitride, metal carbides or metal nitride, and wherein metal is selected from any one and the combination of Al, Ta, Ti, Hf, Zr, Mo, W.
Wherein, the width of mask graph is be more than or equal to the width of gate openings.
Wherein, the width of mask graph is further less than or equal to the width sum of the twice of single lateral wall width Yu gate openings.
Wherein, mask graph material is selected from any and combination of photoresist, silicon oxide, non-crystalline silicon, amorphous carbon.
Wherein, farther include after forming source and drain contact hole: remove mask graph, again expose gate openings; Deposition metal level, is filled up completely with gate openings and self aligned source and drain contact hole; Planarization metal layer is until exposing gate insulator.
Wherein, metal layer material is selected from W, Al and alloy thereof.
Wherein, gate insulator is hafnium.
Self-aligned contacts manufacture method according to the present invention; gate openings is filled on high K insulating barrier mask graph and protects gate openings top and sidewall; can effectively suitably relax critical size and the restriction of overlapping size; improve the stability to technological fluctuation and device reliability, reduce manufacturing cost and technology difficulty.
Accompanying drawing explanation
Technical scheme is described in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 6 is the sectional view of each step of manufacture method of the self-aligned contacts according to the present invention.
Detailed description of the invention
Referring to accompanying drawing the feature and the technique effect thereof that describe technical solution of the present invention in conjunction with schematic embodiment in detail, disclosing can the method, semi-conductor device manufacturing method of effective control gate lines fineness. It is pointed out that similar accompanying drawing labelling represents similar structure, term " first " use herein, " second ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process. These modifications do not imply that modified device architecture or the space of manufacturing process, order or hierarchical relationship unless stated otherwise.
Referring to the schematic diagram of each step of Fig. 1��Fig. 4, technical scheme is described in detail.
As it is shown in figure 1, gate openings in the first interlayer dielectric layer deposits the gate insulator of hafnium and planarizes, until exposing the first interlayer dielectric layer.
Specifically, substrate 1 is first provided, substrate 1 needs according to device application and rationally selects, monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (StrainedSi), germanium silicon (SiGe) can be included, or compound semiconductor materials, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc. For the consideration compatible with CMOS technology, substrate 1 is preferably body Si. Before forming false grid insulating barrier, preferably, adopt fluorine-based solution--such as dilute HF (dHF) solution or dilution slow release etching agent (dBOE) carries out the surface cleaning of short time, remove oxide that may be present between false grid insulating barrier and substrate, for instance thin layer of silicon oxide.
Subsequently, adopting CVD technique, for instance LPCVD, PECVD, HDPCVD etc., on substrate 1 deposition false grid insulating barrier (not shown), its material can be silicon oxide, high-g value and combination thereof. High-g value includes but not limited to that nitride (such as SiN, AlN, TiN), metal-oxide (are mainly subgroup and lanthanide element oxide, for instance MgO, Al2O3��Ta2O5��TiO2��ZnO��ZrO2��HfO2��CeO2��Y2O3��La2O3), Perovskite Phase oxide (such as PbZrxTi1-xO3(PZT)��BaxSr1-xTiO3(BST)). The thickness of false grid insulating barrier can not be too thick, it is to avoid affects gate topography, it is therefore preferable to 1��5nm.
Afterwards, adopt the conventional process such as CVD, PVD, the techniques such as such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputtering, form false grid layer (not shown), its material can be polysilicon, non-crystalline silicon, SiGe, Si:C, amorphous germanium, amorphous carbon etc. and combination thereof, it is therefore preferable to polysilicon, non-crystalline silicon.
Adopt conventional photoetching/etching technics to pattern false grid layer and false grid insulating barrier, form false grid stacked structure. Directly with false grid stacked structure for mask, carry out low dosage, low-energy first time source and drain doping ion implanting, the substrate 1 of the stacking both sides of false grid is formed lightly doped source drain extension district 1L. Further, it is also possible to carry out angle-tilt ion injection, form Yun Zhuan source and drain doping district (Halo district, not shown). Owing to eliminating the forming step of offset side wall, shorten grid and control the length in lower channel district, be conducive to manufacturing fine small size device.
Form grid curb wall 2 in false grid stacked structure both sides, in the substrate of grid curb wall 2 both sides, form heavily doped source-drain area. Adopt the technique such as LPCVD, PECVD, HDPCVD, whole device deposits such as silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon (DLC) etc. finer and close, insulant that hardness is bigger etch formation grid curb wall 2. With grid curb wall 2 for mask, carrying out high dose, high-octane second time source and drain doping ion implanting, the substrate 1 in grid curb wall 2 both sides reforms heavily doped source-drain area 1H. Preferably, grid curb wall 2 can be multiple structure (not shown), such as at least include trilaminate structure, outside the first grid side wall that respectively inner side stacking with false grid contacts, the grid curb wall wall of the L-type (there is the Part II of longitudinal Part I and transverse direction) outside first grid side wall and grid curb wall wall and on second grid side wall (it is positioned at the outside of longitudinal Part I of grid curb wall wall, and is positioned on the horizontal Part II of grid curb wall wall). The material of first grid side wall is such as amorphous carbon or silicon nitride, it is possible to adopt LPCVD, PECVD, HDPCVD technique to be formed, and the silicon nitride that preferably LPCVD makes. Grid curb wall wall is such as silicon oxide prepared by CVD, in order to provide the high etching selection ratio with other adjacent layers, thus the pattern of control gate/side wall. Second grid side wall can be CVD prepare silicon nitride, diamond like carbon amorphous carbon (DLC), silicon oxynitride etc. In a preferred embodiment of the invention, the width of side wall 2 is preferably more than the half of grid width and the difference of source/drain region width, it is such as 15nm, this is corresponding to overlay (namely full-size of contact hole lateral deviation) in follow-up self-aligned contacts formation process less than 15nm, namely contact hole offset distance can be avoided less than grid curb wall 2 width and metal gates is short-circuit. In contrast, due to gate openings and lateral wall width sum and source-drain area similar width in common process, the overlay of higher condition is therefore needed to limit in contact hole process is precisely formed, for instance below 5nm.
By techniques such as spin coating, spraying, silk screen printing, CVD (such as LPCVD) depositions on whole device, forming the first interlayer dielectric layer 3, its material is preferably silicon oxide, silicon nitride or other low-k materials. Low-k materials includes but not limited to organic low-k materials (such as containing the organic polymer of aryl or many rings), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer). Subsequently, etching removes false grid layer, leaves gate openings 3T in ILD3. For the false grid layer of silicon material, it is possible to adopt TMAH wet etching to remove; For amorphous carbon material, it is possible to select oxygen plasma etch, it is possible to be prevented effectively from the erosion to adjacent materials, be favorably improved lines fineness; For other materials, it is possible to select plasma dry etch or the reactive ion etching (RIE) of fluorine-based or chloro etching gas. Preferably, etching stopping is on false grid insulating barrier, and false grid insulating barrier is used as boundary layer and does not weather for protection surface, substrate channel region in etching process, is conducive to reducing channel surface defect, improving device reliability. In addition, false grid insulating barrier (not shown) can also be removed further after removing false grid layer, until exposing substrate 1, and adopt chemical oxidation (such as immersing 20s in the deionized water containing 10ppm ozone) method to form the boundary layer of silicon oxide of ultra-thin (such as less than or equal to 1nm thickness) subsequently, for reducing the boundary defect between high-k gate dielectric and substrate.
Adopt the techniques such as HDPCVD, MOCVD, MBE, ALD, sputtering that gate openings sequentially forms gate dielectric layer 4 in ILD3, but be formed without metal gates conductive layer. Gate dielectric layer 4 is such as high-g value, includes but not limited to that nitride (such as SiN, AlN, TiN), metal-oxide (are mainly subgroup and lanthanide element oxide, for instance MgO, Al2O3��Ta2O5��TiO2��ZnO��ZrO2��HfO2��CeO2��Y2O3��La2O3), nitrogen oxides (such as HfSiON); Perovskite Phase oxide (such as PbZrxTi1-xO3(PZT)��BaxSr1-xTiO3(BST)). It is highly preferred that there is also the boundary layer (not shown) of ultra-thin (such as 0..8��1..5nm) silicon oxide material of thermal oxide, chemical oxidation formation between gate dielectric layer 4 and substrate 1 channel region to reduce interface state density. It should be noted that high-K gate insulating barrier 4 thinner thickness and the technique adopting step coverage good are formed, therefore only cover bottom and the sidewall of gate openings 3T, and leave mid portion opening 3T and be not filled by. Preferably, work function regulating course (not shown) can be formed on gate dielectric layer 4, being formed preferably for example by conventional methods such as PVD, CVD, ALD, barrier layer material is the simple substance of metal M, alloy, nitrogen oxides, carbide or nitride, for instance MxNy��MxSiyNz��MxAlyNz��MaAlxSiyNz��MxOyNz��MxCy, wherein M is any one and combination of Al, Ta, Ti, Hf, Zr, Mo, W or other element. Work function regulating course adopts the good conformal deposition process of step coverage equally, namely only covers bottom and the sidewall of gate openings 3T, is not filled up completely with.
As in figure 2 it is shown, form mask graph 5 in not complete filling of gate openings 7T. Mask graph 5 can photoetching offset plate figure, for instance form photoresist layer by spin coating, spraying, silk-screen printing technique, and adopt exposure subsequently, developing defines the mask graph 5 of photoresist. In addition, mask graph 5 can also is that the hard mask different from ILD3 material, the such as silicon oxide of the method such as LPCVD, PECVD, oxidation formation, amorphous carbon, non-crystalline silicon etc., or the laminated construction of these materials, thus can improve the precision of mask transfer further. The width of mask graph 5 is greater than the width of the metal gates conductive layer eventually formed namely the width be more than or equal to gate openings 3T. And specifically, the width of mask graph 5 is further less than or equal to single gate side wall 2 width twice and gate openings (namely future gate) width sum, namely the width of layer 5=gate openings 3T remains width+2 �� side wall 2 width. Thus, mask graph 5 be completely covered gate openings 3T and preferably with the lateral surface flush alignment of grid curb wall 2, the critical size making whole technique can allow suitable fluctuation and suitable overlay, namely when the deviation of box lunch gate line bar or contact hole deviation, due to ILD3, being dielectrically separated from of grid curb wall 2, grid without with metal plug short circuit in subsequent touch hole. This improves device reliability, and reduce device cost.
As it is shown on figure 3, with mask graph 5 for mask, adopt anisotropic etch process, be sequentially etched gate insulator 4, ILD3, until source-drain area 1L, 1H of exposing in substrate 1 and expose the side of grid curb wall 2, define contact hole 1C. Etching technics can be a step etching or two steps etching (then first etch layer 4 stops on ILD3 adjusting process parameter etching ILD3 again), etching technics can be dry etching (such as adjusting the proportioning of the fluorine-based etching gas of carbon to obtain different etch rates) can also be wet etching (, for silicon nitride, HF base corrosive liquid is for silicon oxide for such as hot phosphoric acid). Combined Protection due to mask graph 5 and grid curb wall 2; making in contact hole etching process will not the top in space occupied by lateral corrasion metal gates in future and sidewall; thus can obtain the grid lines fine, reliability is high to contact with source and drain, improve device performance and reliability. It should be noted that this source and drain contact hole directly exposes the sidewall of grid curb wall 2, be therefore called autoregistration source and drain contact hole, be beneficial to reduction source-drain contact resistance.
As shown in Figure 4, selective etch removes mask graph 5. For the concrete material of mask graph 5, select various suitable etching technics. Such as, when mask graph 5 is soft photoetching offset plate figure, cineration technics (such as oxygen plasma dry etching) or strong oxidizer and strong acid/weak base wet etching is adopted to remove the figure 5 of organic material. When other materials that mask graph 5 is non-crystalline silicon, amorphous carbon, silicon oxide, can select, with grid curb wall 2 and high-K gate dielectric layer 4, there is dry etch process or the wet-etching technology of relatively high etch selectivity, such as adopt TMAH wet etching for non-crystalline silicon, amorphous carbon adopts oxygen plasma dry etching, and silicon oxide adopts HF base corrosive liquid wet method to remove. Thus, gate openings 3T is again exposed.
As it is shown in figure 5, form contact metal layer 6 on whole device, it is filled with gate openings 3T and source and drain contact hole 1C simultaneously. Metal level 6 formation process such as MOCVD, MBE, ALD, evaporation, sputtering etc., its material can include but not limited to the alloy of the metal simple-substances such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals and the nitride of these metals, has the elements such as C, F, N, O, B, P, As to regulate work function also by original position doping or ion implantation doping in addition. Further preferably, metal level 6 material mainly includes W, Al and alloy thereof, such as W simple substance, W alloy (WN, WTi, WMo), Al alloy (TiAl, TaAl, MoAl), this is primarily due to these material filling capacity is good, resistivity is relatively low and be high for CMP compatibility. Metal level 6 thickness of part on gate insulator 4 top is preferably smaller than between grid curb wall 2 the 30% of the following segment thickness in gate insulator 4 top, in other words namely metal level 6 apart from less than gate insulator 4 overhead height 1..3 times of substrate 1 end face maximum height, thus can reduce the subsequent CMP time and avoid expanding CMP castellation depression (two ends can be formed during CMP in the middle part of lines higher than middle depression, reduce CMP total amount and can effectively reduce this depression).
As shown in Figure 6, planarization metal layer 6, until exposing gate insulator 4, defining grid conducting layer 7 and contacting 8 with self aligned source and drain. Flatening process such as CMP or time quarter. It should be noted that this source and drain contact plug 8 directly contacts the sidewall of grid curb wall 2, be therefore called autoregistration source and drain contact hole, be beneficial to the width by increasing and reduce source-drain contact resistance. And still further aspect, although grid curb wall 2 dielectric constant of silicon nitride material is a bit larger tham ILD3, but the spacing contacted with source and drain due to grid is reduced significantly, and total parasitic capacitance is actually greatly reduced.
Self-aligned contacts manufacture method according to the present invention; gate openings is filled on high K insulating barrier mask graph and protects gate openings top and sidewall; can effectively suitably relax critical size and the restriction of overlapping size; improve the stability to technological fluctuation and device reliability, reduce manufacturing cost and technology difficulty.
Although the present invention being described with reference to one or more exemplary embodiments, those skilled in the art could be aware that and device architecture is made without departing from the scope of the invention various suitable change and equivalents. Additionally, many amendments that can be adapted to particular condition or material can be made without deviating from the scope of the invention by disclosed instruction. Therefore, the purpose of the present invention does not lie in and is limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will include all embodiments fallen within the scope of the present invention.
Claims (11)
1. a self-aligned contacts manufacture method, including:
The first interlayer dielectric layer on substrate is formed gate openings, gate openings sidewall has grid curb wall;
Gate openings is formed the gate insulator not being filled up completely with gate openings;
Mask graph is formed in gate openings, on gate insulator;
With mask graph for mask, etching interlayer dielectric layer, until exposing substrate top and grid curb wall sidewall, forming self aligned source and drain contact hole.
2. the step the method for claim 1, wherein forming gate openings farther includes: form false grid on substrate stacking; Grid curb wall is formed at the stacking sidewall of false grid; Substrate is formed and covers the interlayer dielectric layer that false grid is stacking; Planarization interlayer dielectric layer is until exposure false grid is stacking; It is stacking that selective etch removes false grid, leaves gate openings in the first interlayer dielectric layer.
3. the method for claim 1, wherein grid curb wall material selected from silicon nitride, silicon oxynitride, DLC any one and combination.
4. the method for claim 1, wherein farther include after forming gate insulator and before forming mask graph, in gate openings, on gate insulator, form work function regulating course.
5. method as claimed in claim 4, wherein, work function regulating course is metal, metal alloy, metal oxynitride, metal carbides or metal nitride, and wherein metal is selected from any one and the combination thereof of Al, Ta, Ti, Hf, Zr, Mo, W.
6. the method for claim 1, wherein the width of mask graph be more than or equal to the width of gate openings.
7. method as claimed in claim 6, wherein, the width of mask graph is further less than or equal to the width sum of the twice of single lateral wall width Yu gate openings.
8. the method for claim 1, wherein mask graph material is selected from any and combination of photoresist, silicon oxide, non-crystalline silicon, amorphous carbon.
9. farther include after the method for claim 1, wherein forming source and drain contact hole: remove mask graph, again expose gate openings; Deposition metal level, is filled up completely with gate openings and self aligned source and drain contact hole; Planarization metal layer is until exposing gate insulator.
10. method as claimed in claim 9, wherein, metal layer material is selected from W, Al and alloy thereof.
11. the method for claim 1, wherein gate insulator is hafnium.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112151386A (en) * | 2020-09-27 | 2020-12-29 | 中国科学院微电子研究所 | Stacked nanowire ring gate device and manufacturing method thereof |
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| CN102468174A (en) * | 2010-11-18 | 2012-05-23 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| CN103681604A (en) * | 2012-09-07 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semi-conductor device with self-aligning contact holes and manufacture method of semi-conductor device |
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| US20010053594A1 (en) * | 1999-05-03 | 2001-12-20 | Qi Xiang | High-k gate dielectric process with self aligned damascene contact to damascene gate and a low-k inter level dielectric |
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Application publication date: 20160601 |