CN103578945A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN103578945A CN103578945A CN201210258449.9A CN201210258449A CN103578945A CN 103578945 A CN103578945 A CN 103578945A CN 201210258449 A CN201210258449 A CN 201210258449A CN 103578945 A CN103578945 A CN 103578945A
- Authority
- CN
- China
- Prior art keywords
- grid structure
- interlayer dielectric
- dielectric layer
- etch
- methods according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 106
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 91
- 239000011229 interlayer Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 17
- 239000000470 constituent Substances 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000006073 displacement reaction Methods 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000012937 correction Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004110 Zinc silicate Substances 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- NKZSPGSOXYXWQA-UHFFFAOYSA-N dioxido(oxo)titanium;lead(2+) Chemical compound [Pb+2].[O-][Ti]([O-])=O NKZSPGSOXYXWQA-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
- XSMMCTCMFDWXIX-UHFFFAOYSA-N zinc silicate Chemical compound [Zn+2].[O-][Si]([O-])=O XSMMCTCMFDWXIX-UHFFFAOYSA-N 0.000 description 1
- 235000019352 zinc silicate Nutrition 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for manufacturing a semiconductor device. The method includes the steps that a substrate is provided, and a first interlayer dielectric layer and a gate structure are formed on the substrate, wherein the gate structure is located in the first interlayer dielectric layer; etching back is executed on the gate structure, and then the upper surface of the gate structure is lower than the upper surface of the first interlayer dielectric layer; a gate structure covering layer is formed on the substrate; planarization is executed on the gate structure covering layer, and then the upper surface of the gate structure covering layer is flush with the upper surface of the first interlayer dielectric layer. According to the method, the interval between a contact plug and a metal grid electrode can be increased, bridge connection between the contact plug and the metal grid electrode is improved, and then the semiconductor device with the improved electrical property can be manufactured.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method being used for producing the semiconductor devices, the method can be improved the bridge joint problem between contact plunger (contact plug) and metal gates.
Background technology
Along with grid size foreshortens to tens nanometers, the thickness of gate dielectric is down to below 3nm, has caused that resistance is excessive, the problems such as vague and general phenomenon appear in the electric increase of grid leak and polysilicon gate.Therefore, people invest metal gate technique again by sight again, wherein, adopt and have more low-resistance metal as grid, and adopt the material with high-k (high k) as gate dielectric.
Yet, in metal gates manufacturing process, between contact plunger and metal gates, easily there is bridge joint, for yield loss, there is high risk in this.The basic reason that bridge joint occurs is, the allowance (being 20nm) of the process window of the gap ratio chemical etching technique between contact plunger and metal gates (for example, Overlay control and CD homogeneity) is little.
Therefore, need a kind of method being used for producing the semiconductor devices, to solve problems of the prior art.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
For solving above-mentioned problems of the prior art, the invention provides a kind of method being used for producing the semiconductor devices, comprising: provide substrate, the grid structure that is formed with the first interlayer dielectric layer and is arranged in described the first interlayer dielectric layer on described substrate; Described grid structure is carried out to etch-back and process, so that its upper surface is lower than the upper surface of described the first interlayer dielectric layer; Above described substrate, form grid structure cover layer; And described grid structure cover layer is carried out to planarization, so that the upper surface flush of the tectal upper surface of described grid structure and described the first interlayer dielectric layer.
Preferably, described etch-back is processed and is adopted dry etching to process.
Preferably, the processing gas that described dry etching processing is used comprises Cl
2.
Preferably, the processing gas that described dry etching processing is used also comprises N
2, CH
4, CHF
3with at least one in Ar.
Preferably, described etch-back is processed and is adopted wet etch process.
Preferably, the etch-rate of institute's wet etch process is not more than 5nm/ minute.
Preferably, 1/5 ~ 1/2 of the height that the etch depth that described etch-back is processed is described grid structure.
Preferably, the etch depth that described etch-back is processed is 10 ~ 40nm.
Preferably, the tectal constituent material of described grid structure is silica, silicon nitride, mixes the carbide of silicon and at least one in silicon oxynitride.
Preferably, described grid structure cover layer forms by chemical vapour deposition technique or atomic layer deposition method.
Preferably, the tectal thickness of described grid structure is 20 ~ 60nm.
Preferably, described planarization is the time to control technique.
Preferably, after described planarization, further comprise: remove described the first interlayer dielectric layer.
Preferably, after described planarization, further comprise: above described substrate, form the second interlayer dielectric layer; And form contact hole in described the second interlayer dielectric layer.
Preferably, when forming described contact hole, by regulating alignment displacement to regulate the spacing between described contact hole and described grid structure.
Preferably, described grid structure both sides are formed with side wall.
Preferably, described grid structure comprises gate dielectric and is positioned at the metal gates on described gate dielectric.
Preferably, be also included in the step that deposits contact etch stop layer in whole described Semiconductor substrate.
Preferably, adopt wet etching to remove described the first interlayer dielectric layer.
Preferably, described the first interlayer dielectric layer is oxide.
In sum, the method according to this invention has the following advantages: first, can increase the spacing between contact plunger and metal gates, thereby improve bridge joint problem between the two; Secondly, for optical proximity correction (Optical Proximity Correction, OPC), photoetching or etch process, can obtain preferably process window.Therefore, the method according to this invention can finally realize the raising to the integrated electronic performance of semiconductor device.In addition, the method easily compatible with traditional cmos process, without increasing extra mask and exposure imaging step and simple, thereby can reduce manufacturing cost and realize reliably technology controlling and process online.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In accompanying drawing:
Fig. 1 is for manufacturing according to an exemplary embodiment of the present the process chart of semiconductor device;
Fig. 2 A-2F is for manufacturing according to an exemplary embodiment of the present the schematic cross sectional view of the device that in semiconductor device technology flow process, each step obtains; And
Fig. 3 A and Fig. 3 B are respectively according to the present invention and the schematic cross sectional view of the semiconductor device structure that prior art is made.
Embodiment
Next, in connection with accompanying drawing, the present invention is more intactly described, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In accompanying drawing, for the sake of clarity the size in ，Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, it can directly be positioned at other element or layer is upper, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.
Fig. 1 shows the process chart of manufacturing according to an exemplary embodiment of the present semiconductor device, and Fig. 2 A-2F shows the schematic cross sectional view of manufacturing according to an exemplary embodiment of the present the device that in semiconductor device technology flow process, each step obtains.Should be noted that, part of devices structure in semiconductor device can be made flow process by polysilicon gate CMOS (Complementary Metal Oxide Semiconductor) (CMOS) and be manufactured, therefore before method of the present invention, among or can provide extra technique afterwards, and wherein some technique is only done simple description at this.Below in conjunction with accompanying drawing, describe exemplary embodiment of the present invention in detail.
First, execution step S101: provide substrate, the grid structure that is formed with the first interlayer dielectric layer and is arranged in described the first interlayer dielectric layer on described substrate.
As shown in Figure 2 A, provide substrate 210, the grid structure that is formed with the first interlayer dielectric layer 230 and is arranged in the first interlayer dielectric layer 230 on substrate 210.
As shown in the figure, for example in substrate 210, form active/drain region 216 and isolation channel 212(, shallow-trench isolation (STI)) etc.On substrate 210, be formed with grid structure.As example, in the present embodiment, grid structure comprises gate dielectric 222 and is positioned at the metal gates (forming the gate material layers of grid structure) 224 on gate dielectric 222.Preferably, in these grid structure both sides, be formed with side wall 226, it is injury-free that it is mainly used in when forming source/drain region by plasma injection technology grill-protected electrode structure, and effectively control the relative position relation between source/drain region and grid structure.Here, it should be understood that grid technique after grid structure in this example is for high-k/metal gate, but the present invention is not limited to this, but can also adopt other grid structure, the polysilicon gate construction being formed by polysilicon gate and gate dielectric for example generally adopting at present.
As example, the constituent material of substrate 210 can be not doped monocrystalline silicon, the monocrystalline silicon doped with N-type or p type impurity, polysilicon, germanium silicon or silicon-on-insulator (SOI) etc.The constituent material of gate dielectric 222 can be a kind of such as in the such high k material of hafnium oxide, hafnium silicate, lanthana, zinc oxide, zinc silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanates, yittrium oxide, aluminium oxide, ferroelectric thin film, niobium zincic acid, lead lead-titanate.The constituent material of metal gates 224 for example can comprise one or more in hafnium, titanium, tantalum, aluminium, zirconium, ruthenium, palladium, platinum, cobalt, nickel and oxide thereof and carbide.The constituent material of side wall 226 can be nitride, oxide or its combination.
As example, the constituent material of the first interlayer dielectric layer 230 can be silica, silicon oxynitride, silicon nitride etc., and can adopt the methods such as chemical vapour deposition technique, high density plasma CVD method, method of spin coating, sputter to form.In addition, after forming, can also carry out planarization to the first interlayer dielectric layer 230, to expose the upper surface of described grid structure.The limiting examples of planarization comprises mechanical planarization method and chemico-mechanical polishing flattening method.
In addition, as shown in the figure, in source/drain region, 216 near surfaces can also be formed with metal silicide layer 214.As example, the constituent material of metal silicide 214 is nickel-silicon metal.The effect of metal silicide layer in semiconductor device structure and form technological parameter and condition known to those skilled in the art, be not described in detail in this.
As shown in the figure, between the first interlayer dielectric layer 230 and substrate 210, can also be formed with contact etch stop layer (referred to as CESL layer) 220.It should be understood that this CESL 220 is preferred and nonessential, technical staff can be accepted or rejected according to actual needs.
Then, execution step S102: described grid structure is carried out to etch-back and process, so that its surface is lower than the upper surface of described the first interlayer dielectric layer.
As shown in Figure 2 B, grid structure is carried out to etch-back and process, so that its upper surface is lower than the upper surface of the first interlayer dielectric layer 230.Particularly, described etch-back is processed and can be adopted dry etching to process or wet etch process.When adopting dry etching to process, the processing gas using can comprise Cl
2.In addition, process in gas and can also comprise N
2, CH
4, CHF
3with at least one in Ar as diluent gas.When adopting wet etch process, etch-rate is preferably 5nm/ minute such low rate, to control preferably etched thickness in metal gate layers 224.No matter it should be understood that it is to adopt dry etching or wet etch process, the etch depth that above-mentioned etch-back is processed be all preferably metal gate layers 224 height 1/5 ~ 1/2, and 10 ~ 40nm more preferably.
Then, execution step S103: form grid structure cover layer above described substrate.
As shown in Figure 2 C, above substrate 210, form grid structure cover layer 240, contact etch stop layer when it also can be used as subsequent etch contact hole.The constituent material of grid structure cover layer 240 can be identical with the constituent material of contact etch stop layer 220, for example, can be silica, silicon nitride, mix the carbide of silicon and at least one in silicon oxynitride.Grid structure cover layer 240 equally also can form by conventional chemical vapor deposition (CVD) method or ald (ALD) method.In addition, preferably, grid structure cover layer 240 can be 20 ~ 60nm.In the present embodiment, as example, grid structure cover layer 240 is silicon nitride.The more tectal constituent material of grid structure and form process accordingly and condition is well known to the skilled person, does not repeat them here.
Then, execution step S104: described grid structure cover layer is carried out to planarization, so that the flush of described grid structure cover layer and described the first interlayer dielectric layer.
As shown in Figure 2 D, by flatening process such as chemico-mechanical polishings (CMP), the upper surface of grid structure cover layer 240 is carried out to planarization, so that the upper surface flush of its upper surface and the first interlayer dielectric layer 230.Described planarization is that (more Alternative parameter and the condition of time controlled process planarization are known to those skilled in the art, are not described in detail in this for time control technique.
Here, after planarization, can remove the first interlayer dielectric layer 230, as shown in Figure 2 E.Remove the first interlayer dielectric layer 230 and for example can adopt wet etch process.Those skilled in the art can be adjusted the composition of existing wet treatment solution and proportioning according to the constituent material of the first interlayer dielectric layer 230, to obtain best process results.
Then, further, as shown in Figure 2 F, form CESL layer 250 above substrate 210, it is identical that its constituent material and formation technique all can adopt with CESL layer 220, do not repeat them here.This layer is also preferred and nonessential, for protecting lower floor's rete injury-free when crossing etching.
Then, form the second interlayer dielectric layer (not shown) on CESL layer 250, it forms materials and methods can be identical with described the first interlayer dielectric layer.And afterwards, by etch processs such as plasma dry etchings, in the second interlayer dielectric layer, form contact hole (not shown).The step that forms contact hole specifically can be as follows: on interlayer dielectric layer, form the figuratum photoresist layer of tool; Then, take this photoresist layer as mask, etching interlayer dielectric layer and CESL layer, thus form described contact hole.Certainly, the mask that etching adopts is not limited to the photoresist in the present embodiment, but can also adopt other mask technique, such as metal hard mask etc.In forming the chemical etching technique of contact hole, can be by regulating alignment displacement (overlay shift) to increase the spacing between contact hole and grid structure.
By the final semiconductor device structure obtaining as shown in Figure 3A of method step as above, wherein Reference numeral 360 represents the second interlayer dielectric layer, and Reference numeral 352 represents contact hole.Fig. 3 B is depicted as the schematic cross sectional view of the semiconductor device structure of making according to prior art.Compare with semiconductor device structure shown in Fig. 3 B, spacing in Fig. 3 A between contact hole 352 and metal gates 324 (in figure shown in four-headed arrow) increases, this is equivalent to have increased and will be formed on contact plunger in contact hole 352 and the spacing between metal gates 324, thereby can effectively prevent bridge joint between the two.
In addition, what need be understood is, although the first interlayer dielectric layer is removed after planarization in the present embodiment and then is formed contact etch stop layer, the second interlayer dielectric layer etc., also can not remove the first interlayer dielectric layer and directly form contact etch stop layer, the second interlayer dielectric layer etc. thereon and and then continues execution subsequent process steps.
In addition, also need to be understood, for the object of cost control, above-mentioned every procedure is preferentially selected conventional process of the prior art.In addition, for the object of cost control, can implement above-mentioned every procedure with legacy equipment, to reduce manufacturing cost.And the method according to this invention is due to simple, thereby can realize reliably online technology controlling and process.
Here, although those skilled in the art will appreciate that description above around grid technique after high-k/metal gate and launch, the present invention is not merely applicable to this class technique, but can also be applicable to other semiconductor fabrication process, conventional CMOS technique for example.
In sum, the method according to this invention has the following advantages: first, can increase the spacing between contact plunger and metal gates, thereby improve bridge joint problem between the two; Secondly, for optical proximity correction (Optical Proximity Correction, OPC), photoetching or etch process, can obtain preferably process window.Therefore, the method according to this invention can finally realize the raising to the integrated electronic performance of semiconductor device.In addition, the method easily compatible with traditional cmos process, without increasing extra mask and exposure imaging step and simple, thereby can reduce manufacturing cost and realize reliably technology controlling and process online.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (20)
1. the method being used for producing the semiconductor devices, comprising:
Provide substrate, the grid structure that is formed with the first interlayer dielectric layer and is arranged in described the first interlayer dielectric layer on described substrate;
Described grid structure is carried out to etch-back and process, so that its upper surface is lower than the upper surface of described the first interlayer dielectric layer;
Above described substrate, form grid structure cover layer; And
Described grid structure cover layer is carried out to planarization, so that the upper surface flush of the tectal upper surface of described grid structure and described the first interlayer dielectric layer.
2. method according to claim 1, wherein, described etch-back is processed and is adopted dry etching to process.
3. method according to claim 2, wherein, described dry etching is processed the processing gas using and is comprised Cl
2.
4. method according to claim 3, wherein, described dry etching is processed the processing gas using and is also comprised N
2, CH
4, CHF
3with at least one in Ar.
5. method according to claim 1, wherein, described etch-back is processed and is adopted wet etch process.
6. method according to claim 5, wherein, the etch-rate of institute's wet etch process is not more than 5nm/ minute.
7. method according to claim 1, wherein, 1/5 ~ 1/2 of the height that the etch depth that described etch-back is processed is described grid structure.
8. method according to claim 1, wherein, the etch depth that described etch-back is processed is 10 ~ 40nm.
9. method according to claim 1, wherein, the tectal constituent material of described grid structure is silica, silicon nitride, mix the carbide of silicon and at least one in silicon oxynitride.
10. method according to claim 9, wherein, described grid structure cover layer forms by chemical vapour deposition technique or atomic layer deposition method.
11. methods according to claim 9, wherein, the tectal thickness of described grid structure is 20 ~ 60nm.
12. methods according to claim 1, wherein, described planarization is the time to control technique.
13. methods according to claim 1 wherein, further comprise after described planarization:
Remove described the first interlayer dielectric layer.
14. methods according to claim 1 wherein, further comprise after described planarization:
Above described substrate, form the second interlayer dielectric layer; And
In described the second interlayer dielectric layer, form contact hole.
15. methods according to claim 14, wherein, when forming described contact hole, by regulating alignment displacement to regulate the spacing between described contact hole and described grid structure.
16. methods according to claim 1, wherein, described grid structure both sides are formed with side wall.
17. methods according to claim 1, wherein, described grid structure comprises gate dielectric and is positioned at the metal gates on described gate dielectric.
18. methods according to claim 13, wherein, are also included in the step that deposits contact etch stop layer in whole described Semiconductor substrate.
19. methods according to claim 13, wherein, adopt wet etching to remove described the first interlayer dielectric layer.
20. methods according to claim 1, wherein, described the first interlayer dielectric layer is oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210258449.9A CN103578945A (en) | 2012-07-24 | 2012-07-24 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210258449.9A CN103578945A (en) | 2012-07-24 | 2012-07-24 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103578945A true CN103578945A (en) | 2014-02-12 |
Family
ID=50050469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210258449.9A Pending CN103578945A (en) | 2012-07-24 | 2012-07-24 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103578945A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097689A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing semiconductor device |
| CN107527814A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic installation |
| CN108807514A (en) * | 2017-05-05 | 2018-11-13 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor devices and forming method thereof |
| CN110571189A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and forming method thereof and integrated circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070187727A1 (en) * | 2006-02-16 | 2007-08-16 | Shyh-Fann Ting | Semiconductor mos transistor device and method for making the same |
| CN102194680A (en) * | 2010-03-09 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Method for fabricating a gate structure |
| US20110298061A1 (en) * | 2010-06-08 | 2011-12-08 | International Business Machines Corporation | Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric |
| US8120114B2 (en) * | 2006-12-27 | 2012-02-21 | Intel Corporation | Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate |
-
2012
- 2012-07-24 CN CN201210258449.9A patent/CN103578945A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070187727A1 (en) * | 2006-02-16 | 2007-08-16 | Shyh-Fann Ting | Semiconductor mos transistor device and method for making the same |
| US8120114B2 (en) * | 2006-12-27 | 2012-02-21 | Intel Corporation | Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate |
| CN102194680A (en) * | 2010-03-09 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Method for fabricating a gate structure |
| US20110298061A1 (en) * | 2010-06-08 | 2011-12-08 | International Business Machines Corporation | Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097689A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing semiconductor device |
| CN105097689B (en) * | 2014-05-12 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for making semiconductor devices |
| CN107527814A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic installation |
| CN108807514A (en) * | 2017-05-05 | 2018-11-13 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor devices and forming method thereof |
| CN108807514B (en) * | 2017-05-05 | 2021-06-08 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and method of forming the same |
| CN110571189A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and forming method thereof and integrated circuit |
| CN110571189B (en) * | 2018-06-05 | 2022-04-29 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and forming method thereof and integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI523237B (en) | Finfet having source-drain sidewall spacers with reduced heights | |
| TWI484567B (en) | Semiconductor structure and method for fabricating the same | |
| US8679923B2 (en) | Method for forming metal gate | |
| TWI536571B (en) | Semiconductor device | |
| US8765588B2 (en) | Semiconductor process | |
| US8580625B2 (en) | Metal oxide semiconductor transistor and method of manufacturing the same | |
| JP2015516679A (en) | Integration of non-volatile charge trap memory devices and logic CMOS devices | |
| US8802518B2 (en) | Semiconducor device and method for manufacturing the same | |
| CN103578945A (en) | Method for manufacturing semiconductor device | |
| CN102956466B (en) | Fin transistor and its manufacture method | |
| CN100576513C (en) | The manufacture method of semiconductor device | |
| CN103187367B (en) | The preparation method of the semiconductor element with metal gates | |
| TWI235450B (en) | Method for producing semiconductor device | |
| TW201409701A (en) | Semiconductor element structure and the manufacturing method thereof | |
| TWI689040B (en) | Semiconductor device and method of fabricating the same | |
| CN103681263A (en) | Method for reducing stray capacitance between contact plugs and gate structure | |
| TWI575576B (en) | Method for fabricating semiconductor device | |
| JP2006339597A (en) | Semiconductor device and manufacturing method thereof | |
| TW201714277A (en) | Semiconductor structure and method of forming the same | |
| CN104253049B (en) | Semiconductor device manufacturing method | |
| TWI524394B (en) | Manufacturing method for semiconductor device having metal gate | |
| CN104217951A (en) | Semiconductor device and manufacture method thereof | |
| CN110047755A (en) | A kind of manufacturing method of semiconductor devices | |
| CN109037213A (en) | A kind of semiconductor devices and preparation method thereof and electronic device | |
| TWI517261B (en) | Semiconductor process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140212 |
|
| RJ01 | Rejection of invention patent application after publication |