JP4428376B2 - Manufacturing method of semiconductor chip mounting substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor chip mounting substrate having a columnar pattern for interlayer connection by etching, and a semiconductor device using the semiconductor chip mounting substrate.

  As electronic devices become smaller and faster, there is an increasing need for mounting semiconductor chips on a printed wiring board at a high density. For this reason, lead packages such as QFP (Quad Flat Package) are often mounted on a printed wiring board. However, as the number of input / output terminals increases, a pin insertion type PGA (Pin Grid Array) in which input / output terminals are provided two-dimensionally around a semiconductor chip has been developed. Since this PGA is not suitable for surface mounting, a surface mounting type BGA (Ball Grid Array) in which solder balls are formed on input / output terminals has been developed. In order to further reduce the size of the package, a CSP (Chip Size Package) has been developed in which a connection terminal with a semiconductor chip is provided around the semiconductor chip, and wiring and input / output terminals are provided in the mounting area. Yes. These are known as chip carrier packages, and take a form in which a semiconductor chip is mounted on an interposer made of a ceramic, a plastic substrate, or a film, and transfer molded with a sealing material. When a ceramic substrate is used as an interposer in such a package, mounting on a printed wiring board made of an organic base material is disadvantageous because reliability at the connection portion is lowered due to mismatch of thermal expansion coefficients. Moreover, the ceramic substrate has a high dielectric constant, which is disadvantageous for reducing the propagation delay.

  On the other hand, the case where a plastic substrate or film is used as an interposer is advantageous and relatively inexpensive. However, there is a drawback that heat dissipation is low. In such an interposer, bonding of a semiconductor chip is mainly performed by bonding of a gold wire, and improvement in noise resistance, reduction in propagation delay, and improvement in heat dissipation are important. From such a background, attention is paid to a mounting form called face-down in which the electrodes of the semiconductor chip are opposedly connected to the connection terminals on the interposer side. Thereby, since the chip | tip back surface leaves | separates from a mounting surface, heat dissipation is improved. Further, the distance between the electrode of the semiconductor chip and the connection terminal on the interposer side is significantly shortened, and the noise resistance due to the reduction in propagation delay and the decrease in inductance is improved. However, in order to apply this mounting form to the CSP, it is indispensable for the interposer to reliably route and connect the connection terminals with the semiconductor chip and the input / output terminals in the mounting area at high density. As a general input / output terminal in the mounting area, circular electrodes are arranged at predetermined intervals by solder ball connection. For this reason, there is a problem that the area of the above-described routing wiring is remarkably reduced.

  The present invention relates to a method for manufacturing a semiconductor chip mounting substrate and a semiconductor chip mounting substrate in which the density of the routing wiring between the connection terminal to the semiconductor chip and the input / output terminal in the mounting area is improved in the face down mounting interposer and the semiconductor chip mounting substrate A semiconductor device is provided.

The method for producing a semiconductor chip mounting substrate of the present invention includes:
A. B. providing a first circuit forming material comprising a first metal layer and a second metal layer; C. etching the first metal layer to form a columnar pattern for interlayer connection; The surface on which the columnar pattern is formed and a second circuit forming material having a third metal layer are pressed through an insulating material layer to electrically connect the columnar pattern and the third metal layer. Process,
D. A step of etching the second and third metal layers to form a predetermined wiring pattern is provided.

  In the semiconductor device of the present invention, the wiring pattern formed by etching the second metal layer of the semiconductor chip mounting substrate manufactured by the method described above is used as an external connection terminal, and the third metal layer is etched. A semiconductor device in which a wiring pattern formed in this manner is used as a semiconductor connection terminal, and a semiconductor chip terminal is connected to the semiconductor connection terminal.

  By the method for manufacturing a semiconductor chip mounting substrate of the present invention, a narrow pitch protruding electrode having a uniform height can be obtained, and the wiring layer and the solder connecting electrode can be separated and connected, thereby greatly increasing the area of the wiring layer. In addition, the layer separation and connection of the wiring layer and the solder connection electrode can be reliably and stably performed.

  In the semiconductor device of the present invention, the chip mounting substrate has high-density protruding electrodes, and is small in size and excellent in reliability.

The method for producing a semiconductor chip mounting substrate of the present invention includes:
1a. Providing a first circuit-forming material comprising a first intermediate metal layer that can be selectively etched with respect to the first metal layer between the second metal layer and the first metal layer;
1b. Etching the first metal layer to form a columnar pattern for interlayer connection;
1c. A second metal layer including a third metal layer and a fourth metal layer, and a second intermediate metal layer which is selectively etched with respect to the third metal layer between the fourth metal layer and the third metal layer. Preparing a circuit forming material of
1d. Pressurizing the surface on which the columnar pattern is formed and the second circuit forming material through an insulating material layer to contact (electrically connect) the columnar pattern and the fourth metal layer;
1e. Etching the second metal layer and the first intermediate layer to form a predetermined wiring pattern;
1f. Etching the third metal layer to form a columnar pattern for semiconductor connection;
1g. Selectively etching the second intermediate metal layer;
1h. A step of etching the fourth metal layer to form a predetermined wiring pattern may be provided.

In addition, a method for manufacturing a semiconductor chip mounting substrate of the present invention includes:
2a. Providing a first circuit-forming material comprising a first intermediate metal layer that can be selectively etched with respect to the first metal layer between the second metal layer and the first metal layer;
2b. Etching the first metal layer to form a columnar pattern for interlayer connection;
2c. Preparing a second circuit-forming material comprising a third metal layer;
2d. Pressing the surface on which the columnar pattern is formed and the second circuit forming material through an insulating material layer, and contacting (electrically connecting) the columnar pattern and the third metal layer;
2e. Etching the second metal layer and the first intermediate layer to form a predetermined wiring pattern;
2f. The third metal layer may be etched to form a predetermined wiring pattern (for example, a semiconductor connection terminal).

In addition, a method for manufacturing a semiconductor chip mounting substrate of the present invention includes:
3a. Providing a first circuit-forming material comprising a first intermediate metal layer that can be selectively etched with respect to the first metal layer between the second metal layer and the first metal layer;
3b. Etching the first metal layer to form a columnar pattern for interlayer connection;
3c. Selectively etching the first intermediate metal layer;
3d. A second metal layer including a third metal layer and a fourth metal layer, and a second intermediate metal layer which is selectively etched with respect to the third metal layer between the fourth metal layer and the third metal layer. Preparing a circuit forming material of
3e. Pressing the surface on which the columnar pattern is formed and the second circuit forming material through an insulating material layer, and bringing the columnar pattern and the fourth metal layer into contact with each other;
3f. Etching the second metal layer and the first intermediate layer to form a predetermined wiring pattern;
3g. Etching the third metal layer to form a columnar pattern for semiconductor connection;
3h. Selectively etching the second intermediate metal layer;
3i. The fourth metal layer may be etched to form a predetermined wiring pattern.

In addition, a method for manufacturing a semiconductor chip mounting substrate of the present invention includes:
4a. Providing a first circuit-forming material comprising a first intermediate metal layer that can be selectively etched with respect to the first metal layer between the second metal layer and the first metal layer;
4b. Etching the first metal layer to form a columnar pattern for interlayer connection;
4c. Selectively etching the first intermediate metal layer;
4d. Preparing a second circuit-forming material comprising a third metal layer;
4e. Pressurizing the surface on which the columnar pattern is formed and the second circuit forming material through an insulating material layer to contact (electrically connect) the columnar pattern and the fourth metal layer;
4f. Etching the second metal layer and the first intermediate layer to form a predetermined wiring pattern;
4g. The method may comprise a step of etching the third metal layer to form a predetermined wiring pattern (for example, a semiconductor connection terminal).

  In the method for manufacturing a semiconductor chip mounting substrate of the present invention, after the step of pressing the surface on which the columnar pattern is formed and the second circuit forming material through the insulating material layer to contact the columnar pattern and the metal layer, A low electrical resistance treatment between the columnar pattern and the metal layer can be performed. As such electrical resistance reduction treatment, voltage migration is applied to the metal that is in contact with the metal ions, ion migration due to the movement of metal ions, and application of ultrasonic waves to reduce the resin residue between the metals that are in contact with each other, increasing the contact probability. The technique of letting it be used can be used. In addition, it is possible to give a smaller connection resistance value by performing at least one of the metal to be contacted by roughening by oxidation and performing oxidation / reduction treatment to reduce the oxidized rough surface in advance.

  In the method for manufacturing a semiconductor chip mounting substrate of the present invention, in order to etch the first metal layer to form a columnar pattern for interlayer connection, between the first metal layer and the second metal layer, A first intermediate metal layer that can be selectively etched with respect to one metal layer can be provided (even if the first intermediate metal layer can be selectively etched with respect to the second metal layer, it cannot be selectively etched). It is possible to selectively etch the first metal layer and the second metal layer without providing the first intermediate metal layer between the first metal layer and the second metal layer. Also good.

  Also, a third metal layer and a fourth metal layer are provided, and a second intermediate metal layer that can be selectively etched with respect to the third metal layer is provided between the fourth metal layer and the third metal layer. The same applies to the second circuit forming material. Furthermore, the first metal layer and the second metal layer, and the third metal layer and the fourth metal layer are a single metal layer, and a predetermined etching resist pattern is formed on the surface of the single metal layer. In the same manner as in the case where the first metal layer and the second metal layer, and the third metal layer and the fourth metal layer are formed by half etching the surface on which the resist is not formed, It is also possible to form a columnar pattern and a predetermined wiring pattern (for example, a semiconductor connection terminal).

  In the present invention, a second metal layer that can be selectively etched with the metal layer is formed on the first metal layer, and the thickness of the second metal layer is the same as that of the first metal layer. In a three-layer metal foil (hereinafter referred to as a three-layer foil) in which a third metal layer different from the first metal layer is formed, a protruding electrode group having a predetermined size is formed on the first metal layer by etching. Using this member, the surface of the projection group of this member is made to face a third metal layer of a separately prepared three-layer foil, and the surface of the projection group is placed on the surface of the third metal layer via a thermosetting resin. Pressure contact. In order to make the mechanical connection more reliable, a predetermined voltage is applied between a third metal having the projection group and a first metal having a third metal layer in contact with the surface of the projection electrode group at a predetermined temperature, humidity, and atmospheric pressure. A step of applying for a predetermined time in an atmosphere to reduce and stabilize the contact resistance between the protruding electrode group and the third metal can be included. The third metal side of the outermost layer of the above member is etched so that at least solder ball connectable terminals are formed.

  FIG. 1 shows a process cross section for forming a protruding electrode group on a first metal of a three-layer foil. In the three-layer foil shown in FIG. 1A, the first intermediate metal layer indicated by 2 in the drawing can be selectively etched with the first metal layer 1 and has a lower ionization tendency than the first metal layer 1. In the structural specifications, the thickness of the first metal layer is 18 to 70 μm, and the thickness of the first intermediate metal layer is 1 to 5 μm. The thickness of the second metal layer 3 is 5 to 18 μm. Although not shown in the drawing for the sake of simplicity, guide holes necessary for mask alignment in a subsequent photolithography process are made in advance in this member.

  A photosensitive resist HN640 made by Hitachi Chemical, for example, is laminated on both surfaces of the three-layer foil, and an etching resist 4 having a projection electrode image, which will be described later, is formed on the first metal layer 1 as shown in FIG. The electrode shape at this time is preferably circular rather than square. Thereafter, the first metal layer is selectively etched as shown in FIG. Next, the etching resist 4 is peeled off to obtain a member having a protruding electrode group having a uniform height as shown in FIG. Thus, a narrow pitch protruding electrode having a uniform height can be obtained. Further, the first intermediate metal layer of this member has a low ionization tendency and can suppress migration of the second metal of the outermost layer.

  FIG. 2 shows a step of bringing the member of FIG. 1 into contact with the three-layer foil under pressure. FIG. 2A shows the member shown in FIG. FIG. 2 (b) shows a cross section of the member arranged through a thermosetting resin so that the tip of the protruding electrode group of this member faces the third metal side of a separately prepared three-layer foil. With this configuration, the bump electrode group is embedded in a thermosetting resin by vacuum hot pressing, and is in mechanical and thermal contact with the third metal layer 3 ′. Thereby, the member shown in FIG.2 (c) is obtained. At this time, a voltage is applied to the surface of the protruding electrode and 3 'under predetermined temperature, humidity, and atmospheric pressure conditions to give a sufficiently small connection resistance value. The wiring layer and the solder connection electrode can be separated and connected, and the area of the wiring layer can be greatly increased.

  FIG. 3 shows a step of sequentially etching the second metal 3 and the first intermediate metal layer 2 of the outermost layer using the members of FIG. 2 to form predetermined solder ball connection electrodes and guide mark patterns, and the outermost layer. The first ', 2', and 3 'metal layers are connected to the protruding electrodes and the solder ball connecting electrodes to be described later so that the guide marks can be seen through from the first' metal layer side, leaving a wiring region to the solder ball connection electrodes. The process of etching is shown. Fig.3 (a) is the member of FIG. In FIG. 3B, a resist 4 is laminated on both surfaces of this member, and a solder ball connecting electrode and a guide mark pattern image to be described later are formed on the second metal layer side indicated by 3 by exposure and development. As shown in c), after etching the second metal layer and the first intermediate metal layer shown by 3 and 2, the resist is peeled off. As shown in FIG. 3D, an etching resist is formed, and after etching the third metal layer 1 ', the second intermediate metal layer 2', and the fourth metal layer 3 ', the resist is peeled off. In this way, the layer separation connection between the wiring layer and the solder connection electrode can be ensured and stabilized.

  FIG. 4 shows a cross section of a manufacturing process of an interposer having a protruding electrode using the members of FIG. FIG. 4A shows a member according to the invention of FIG. The resist 4 is laminated on both surfaces of this member, and an image for forming a projection electrode, which will be described later, is formed on the third metal layer side indicated by the outermost layer 1 'by exposure and development. The second intermediate metal layer indicated by 2 'is selectively etched using the protruding electrode formed by etching the third metal layer 1' as a mask. After the resist is peeled off, a wiring is formed by electrically joining the fourth metal layer indicated by 3 'to at least one protruding electrode in the resin layer indicated by 5 in the same photolithography process. In the structure obtained by FIG. 4C, the metal layer indicated by 1 ′ and 2 ′ is not etched away, but only the metal layer indicated by 1 ′ and 2 ′ is removed by etching. A wiring electrically connected to one protruding electrode may be formed. However, in this case, it is necessary to make a protruding electrode separately. Electroless nickel / palladium / gold plating 6 is performed on the wiring of the substrate including the protruding electrode group of the substrate thus obtained to obtain the interposer shown in FIG. In this manner, a member for producing a high-density interposer can be obtained even if the outermost layer has protruding electrodes or is not provided.

  FIG. 5 is a cross-sectional view showing a process of manufacturing a semiconductor device using the members of FIG. Fig.5 (a) is the member of FIG.4 (d). As shown in FIG. 5B, the semiconductor chip 8 is aligned via the anisotropic conductive adhesive sheet 7, heated and pressurized as shown in FIG. 5C, and as shown in FIG. 5D. The semiconductor device can be obtained by sealing with resin 9 and cutting it out. An anisotropic conductive adhesive sheet is used in which conductive particles are dispersed in an amount of 0.5 to 15% by weight in a resin matrix such as an epoxy resin.

It is sectional drawing which shows the manufacturing process of the board | substrate for semiconductor chip mounting of this invention. It is sectional drawing which shows the manufacturing process of the board | substrate for semiconductor chip mounting of this invention. It is sectional drawing which shows the manufacturing process of the board | substrate for semiconductor chip mounting of this invention. It is sectional drawing which shows the manufacturing process of the board | substrate for semiconductor chip mounting of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of this invention.

Explanation of symbols

1: 1st metal layer 2: 1st intermediate metal layer 3: 2nd metal layer 1 ': 3rd metal layer 2': 2nd intermediate metal layer 3 ': 4th metal layer 4: Resist 5: Insulating material layer 6 : Nickel / Palladium / Gold plating 7: Anisotropic conductive adhesive sheet 8: Semiconductor chip 9: Resin sealing

Claims (3)

A. Preparing a first circuit forming material comprising a first metal layer and a second metal layer;
B. Etching the first metal layer to form a columnar pattern for interlayer connection;
C. The surface on which the columnar pattern is formed and a second circuit forming material having a third metal layer are pressed through an insulating material layer to electrically connect the columnar pattern and the third metal layer. Process,
D. Etching the second and third metal layers to form a predetermined wiring pattern;
A method for manufacturing a semiconductor chip mounting substrate comprising:
A method for manufacturing a substrate for mounting a semiconductor chip, wherein the thickness of the first metal layer is 18 μm to 70 μm. The thickness of the second metal layer is 5Myuemu～18myuemu, semiconductor chip manufacturing method of a substrate for mounting according to claim 1. The first circuit forming material further includes a first intermediate metal layer that can be selectively etched with the third metal layer between the first metal layer and the second metal layer, the thickness of the intermediate metal layer is 1 m to 5 m, the semiconductor chip manufacturing method of a substrate for mounting according to claim 1 or 2.

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